JPS54109350A - Bit transmission system - Google Patents

Bit transmission system

Info

Publication number
JPS54109350A
JPS54109350A JP1619878A JP1619878A JPS54109350A JP S54109350 A JPS54109350 A JP S54109350A JP 1619878 A JP1619878 A JP 1619878A JP 1619878 A JP1619878 A JP 1619878A JP S54109350 A JPS54109350 A JP S54109350A
Authority
JP
Japan
Prior art keywords
bit
data
abnormal
transmission
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1619878A
Other languages
Japanese (ja)
Inventor
Koichi Shinohara
Tadao Ichizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1619878A priority Critical patent/JPS54109350A/en
Publication of JPS54109350A publication Critical patent/JPS54109350A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE: To attain highly-reliable data transmission by reducing the data error of defect of more than one bit to its minimum by accurately orientating the defective bit position of a transmission line when transmitting numeric data with several fixed bits in parallel via bit parallel transmitter.
CONSTITUTION: The transmission system which transmits several pieces of data equivalent to several bit areas 0 to n between 1st and 2nd data processors 1a and 1b is allowed to transmit two kinds of test data, "1" and "0", from processor 1a to processor 1b. From input 31 of a test pattern from processor 1a, bit (i) (0≤i≤) equivalent to a defective bit is detected through detection 32 of an abnormal bit, and pattern 33 of this abnormal bit is inputted to abnormal-bit pattern input 23 to make decision 24 of the existence of the abnormal bit. In case of abnormality, bit areas 0 to (i-1) and (1+i)-n are used for recomposition in transmission data recomposition 25, thereby reducing the transmission error of data to the minimum.
COPYRIGHT: (C)1979,JPO&Japio
JP1619878A 1978-02-15 1978-02-15 Bit transmission system Pending JPS54109350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1619878A JPS54109350A (en) 1978-02-15 1978-02-15 Bit transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1619878A JPS54109350A (en) 1978-02-15 1978-02-15 Bit transmission system

Publications (1)

Publication Number Publication Date
JPS54109350A true JPS54109350A (en) 1979-08-27

Family

ID=11909803

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1619878A Pending JPS54109350A (en) 1978-02-15 1978-02-15 Bit transmission system

Country Status (1)

Country Link
JP (1) JPS54109350A (en)

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