JPS54102957A - Programable divider - Google Patents
Programable dividerInfo
- Publication number
- JPS54102957A JPS54102957A JP977578A JP977578A JPS54102957A JP S54102957 A JPS54102957 A JP S54102957A JP 977578 A JP977578 A JP 977578A JP 977578 A JP977578 A JP 977578A JP S54102957 A JPS54102957 A JP S54102957A
- Authority
- JP
- Japan
- Prior art keywords
- division
- fixed
- speed
- division ratio
- ratio data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004606 Fillers/Extenders Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/193—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J5/00—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner
- H03J5/02—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner with variable tuning element having a number of predetermined settings and adjustable to a desired one of these settings
- H03J5/0245—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form
- H03J5/0272—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form the digital values being used to preset a counter or a frequency divider in a phase locked loop, e.g. frequency synthesizer
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
- H03K23/667—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Numerical Control (AREA)
Abstract
PURPOSE:To ensire the high-speed and accurate operation by leading out the control signal to be the output, which is divided by the division ratio data of the fixed digit number set up by the binary code through the coaction of the high- and low-speed division steps in the form of the division output. CONSTITUTION:High-speed division step I consists of divider 13, 15 and 17 which divide the input pulse signals in sequence with the fixed division ratio in the vertical connection relation and pulse control circuit 12, 14 and 16 which draw out the fixed pulse from the input pulse signal or from the output of each divider in accordance with the division ratio data of a higher-order digit among the fixed division ratio data of the binary code and which are located among the fixed steps. While low- speed division step II comprises divider 21, 22, 23 and 24 which divide the output of step I according to the fixed division ratio data and frequency extender 25 and 26 which deliver the control signal to drive the pulse control circuit with every division cycle. Thus, the control signals are led out with the fixed digit number division ratio data of the binary code through coation of step I and II, ensuring a high-speed operation.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP977578A JPS54102957A (en) | 1978-01-31 | 1978-01-31 | Programable divider |
US06/006,490 US4357527A (en) | 1978-01-31 | 1979-01-25 | Programmable divider |
GB7903316A GB2016764B (en) | 1978-01-31 | 1979-01-31 | Programmable divider |
DE2903700A DE2903700C2 (en) | 1978-01-31 | 1979-01-31 | Programmable divider |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP977578A JPS54102957A (en) | 1978-01-31 | 1978-01-31 | Programable divider |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54102957A true JPS54102957A (en) | 1979-08-13 |
Family
ID=11729613
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP977578A Pending JPS54102957A (en) | 1978-01-31 | 1978-01-31 | Programable divider |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54102957A (en) |
-
1978
- 1978-01-31 JP JP977578A patent/JPS54102957A/en active Pending
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