JPS5381026A - Latch circuit with log in-out feature - Google Patents

Latch circuit with log in-out feature

Info

Publication number
JPS5381026A
JPS5381026A JP15867876A JP15867876A JPS5381026A JP S5381026 A JPS5381026 A JP S5381026A JP 15867876 A JP15867876 A JP 15867876A JP 15867876 A JP15867876 A JP 15867876A JP S5381026 A JPS5381026 A JP S5381026A
Authority
JP
Japan
Prior art keywords
latch circuit
log
out feature
dots
gates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15867876A
Other languages
Japanese (ja)
Other versions
JPS5926132B2 (en
Inventor
Tatsuro Yoshimura
Takamitsu Tsuchimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP51158678A priority Critical patent/JPS5926132B2/en
Publication of JPS5381026A publication Critical patent/JPS5381026A/en
Publication of JPS5926132B2 publication Critical patent/JPS5926132B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only

Abstract

PURPOSE:To form the high-speed latch circuit having the small number of gates utilizing the features of CML gates such as emitter dots and collector dots.
JP51158678A 1976-12-27 1976-12-27 Latch circuit with log in/out function Expired JPS5926132B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP51158678A JPS5926132B2 (en) 1976-12-27 1976-12-27 Latch circuit with log in/out function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP51158678A JPS5926132B2 (en) 1976-12-27 1976-12-27 Latch circuit with log in/out function

Publications (2)

Publication Number Publication Date
JPS5381026A true JPS5381026A (en) 1978-07-18
JPS5926132B2 JPS5926132B2 (en) 1984-06-25

Family

ID=15676963

Family Applications (1)

Application Number Title Priority Date Filing Date
JP51158678A Expired JPS5926132B2 (en) 1976-12-27 1976-12-27 Latch circuit with log in/out function

Country Status (1)

Country Link
JP (1) JPS5926132B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59228410A (en) * 1983-06-09 1984-12-21 Nec Corp Latch circuit
JPS6055726A (en) * 1983-09-07 1985-04-01 Hitachi Ltd Multi-output logic circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4847257A (en) * 1971-10-18 1973-07-05

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4847257A (en) * 1971-10-18 1973-07-05

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59228410A (en) * 1983-06-09 1984-12-21 Nec Corp Latch circuit
JPS6055726A (en) * 1983-09-07 1985-04-01 Hitachi Ltd Multi-output logic circuit
JPH0352688B2 (en) * 1983-09-07 1991-08-12 Hitachi Seisakusho Kk

Also Published As

Publication number Publication date
JPS5926132B2 (en) 1984-06-25

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