JPS5360129A - Full adder circuit - Google Patents

Full adder circuit

Info

Publication number
JPS5360129A
JPS5360129A JP13508976A JP13508976A JPS5360129A JP S5360129 A JPS5360129 A JP S5360129A JP 13508976 A JP13508976 A JP 13508976A JP 13508976 A JP13508976 A JP 13508976A JP S5360129 A JPS5360129 A JP S5360129A
Authority
JP
Japan
Prior art keywords
circuit
adder circuit
full adder
exclusive
comination
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13508976A
Other languages
English (en)
Japanese (ja)
Other versions
JPS551619B2 (enrdf_load_stackoverflow
Inventor
Ryota Kasai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP13508976A priority Critical patent/JPS5360129A/ja
Publication of JPS5360129A publication Critical patent/JPS5360129A/ja
Publication of JPS551619B2 publication Critical patent/JPS551619B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
JP13508976A 1976-11-10 1976-11-10 Full adder circuit Granted JPS5360129A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13508976A JPS5360129A (en) 1976-11-10 1976-11-10 Full adder circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13508976A JPS5360129A (en) 1976-11-10 1976-11-10 Full adder circuit

Publications (2)

Publication Number Publication Date
JPS5360129A true JPS5360129A (en) 1978-05-30
JPS551619B2 JPS551619B2 (enrdf_load_stackoverflow) 1980-01-16

Family

ID=15143565

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13508976A Granted JPS5360129A (en) 1976-11-10 1976-11-10 Full adder circuit

Country Status (1)

Country Link
JP (1) JPS5360129A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2516675A1 (fr) * 1981-11-19 1983-05-20 Labo Cent Telecommunicat Cellule d'addition binaire a trois entrees a propagation rapide de la retenue
JPS60247733A (ja) * 1984-05-24 1985-12-07 Toshiba Corp 論理演算回路

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52116034A (en) * 1976-02-23 1977-09-29 Intel Corp Binary adder for adding multiple bit binary number

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52116034A (en) * 1976-02-23 1977-09-29 Intel Corp Binary adder for adding multiple bit binary number

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2516675A1 (fr) * 1981-11-19 1983-05-20 Labo Cent Telecommunicat Cellule d'addition binaire a trois entrees a propagation rapide de la retenue
JPS60247733A (ja) * 1984-05-24 1985-12-07 Toshiba Corp 論理演算回路

Also Published As

Publication number Publication date
JPS551619B2 (enrdf_load_stackoverflow) 1980-01-16

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