JPS5291624A - High speed addition circuit - Google Patents

High speed addition circuit

Info

Publication number
JPS5291624A
JPS5291624A JP796976A JP796976A JPS5291624A JP S5291624 A JPS5291624 A JP S5291624A JP 796976 A JP796976 A JP 796976A JP 796976 A JP796976 A JP 796976A JP S5291624 A JPS5291624 A JP S5291624A
Authority
JP
Japan
Prior art keywords
high speed
addition circuit
speed addition
adder
digit adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP796976A
Other languages
Japanese (ja)
Inventor
Mamoru Asagami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP796976A priority Critical patent/JPS5291624A/en
Publication of JPS5291624A publication Critical patent/JPS5291624A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/505Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/507Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using selection between two conditionally calculated carry or sum values

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To enable the operation of an upper digit adder simultaneously with that of a lower digit adder without waiting for the carry-up from the lower digit adder by constituting the adder in a divided form.
JP796976A 1976-01-29 1976-01-29 High speed addition circuit Pending JPS5291624A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP796976A JPS5291624A (en) 1976-01-29 1976-01-29 High speed addition circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP796976A JPS5291624A (en) 1976-01-29 1976-01-29 High speed addition circuit

Publications (1)

Publication Number Publication Date
JPS5291624A true JPS5291624A (en) 1977-08-02

Family

ID=11680282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP796976A Pending JPS5291624A (en) 1976-01-29 1976-01-29 High speed addition circuit

Country Status (1)

Country Link
JP (1) JPS5291624A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60140424A (en) * 1983-12-28 1985-07-25 Fujitsu Ltd Arithmetic processing method
JPS61110237A (en) * 1984-11-01 1986-05-28 レイセオン カンパニ− Multi-bit digital adder
JPS61110236A (en) * 1984-11-01 1986-05-28 レイセオン カンパニー Multi-bit digital adder
JPS61122747A (en) * 1984-11-14 1986-06-10 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Data processor
JPS61187038A (en) * 1985-02-15 1986-08-20 Agency Of Ind Science & Technol Adding circuit
JPH02245948A (en) * 1989-03-20 1990-10-01 Fujitsu Ltd In-main-storage data transfer system
US11778842B2 (en) 2013-03-15 2023-10-03 Apple Inc. Light emitting diode display with redundancy scheme

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60140424A (en) * 1983-12-28 1985-07-25 Fujitsu Ltd Arithmetic processing method
JPS61110237A (en) * 1984-11-01 1986-05-28 レイセオン カンパニ− Multi-bit digital adder
JPS61110236A (en) * 1984-11-01 1986-05-28 レイセオン カンパニー Multi-bit digital adder
JPH0476133B2 (en) * 1984-11-01 1992-12-02 Raytheon Co
JPS61122747A (en) * 1984-11-14 1986-06-10 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Data processor
JPS61187038A (en) * 1985-02-15 1986-08-20 Agency Of Ind Science & Technol Adding circuit
JPH02245948A (en) * 1989-03-20 1990-10-01 Fujitsu Ltd In-main-storage data transfer system
US11778842B2 (en) 2013-03-15 2023-10-03 Apple Inc. Light emitting diode display with redundancy scheme

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