JPS5329071A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5329071A
JPS5329071A JP10378376A JP10378376A JPS5329071A JP S5329071 A JPS5329071 A JP S5329071A JP 10378376 A JP10378376 A JP 10378376A JP 10378376 A JP10378376 A JP 10378376A JP S5329071 A JPS5329071 A JP S5329071A
Authority
JP
Japan
Prior art keywords
semiconductor device
heat sink
pellet
chassis
meet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10378376A
Other languages
Japanese (ja)
Other versions
JPS5541530B2 (en
Inventor
Masao Kachi
Hiroshi Asami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP10378376A priority Critical patent/JPS5329071A/en
Publication of JPS5329071A publication Critical patent/JPS5329071A/en
Publication of JPS5541530B2 publication Critical patent/JPS5541530B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE: To prevent broken pellet when a heat sink is attached to the chassis, by fixing such that the crystal directions of the pellet and the length direction of the heat sink do not meet at right angles.
COPYRIGHT: (C)1978,JPO&Japio
JP10378376A 1976-08-30 1976-08-30 Semiconductor device Granted JPS5329071A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10378376A JPS5329071A (en) 1976-08-30 1976-08-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10378376A JPS5329071A (en) 1976-08-30 1976-08-30 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5329071A true JPS5329071A (en) 1978-03-17
JPS5541530B2 JPS5541530B2 (en) 1980-10-24

Family

ID=14363001

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10378376A Granted JPS5329071A (en) 1976-08-30 1976-08-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5329071A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4826470A (en) * 1971-08-10 1973-04-07

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4826470A (en) * 1971-08-10 1973-04-07

Also Published As

Publication number Publication date
JPS5541530B2 (en) 1980-10-24

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