Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/01—Manufacture or treatment
  • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
  • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/10—Isolation regions comprising dielectric materials
  • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]

Landscapes

• Semiconductor Memories (AREA)

Applications Claiming Priority (1)

Publications (2)

Family

ID=23020055

Family Applications (1)

Country Status (6)

Families Citing this family (7)

Family Cites Families (5)

• 1973
  • 1973-04-14 DE DE2318912A patent/DE2318912A1/de not_active Ceased
  • 1973-05-15 IT IT24074/73A patent/IT987426B/it active
  • 1973-05-18 JP JP48054847A patent/JPS528229B2/ja not_active Expired
  • 1973-06-01 GB GB2620873A patent/GB1422586A/en not_active Expired
  • 1973-06-04 CA CA173,051A patent/CA1005925A/en not_active Expired
  • 1973-06-06 FR FR7321783A patent/FR2191270B1/fr not_active Expired

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