JPS528229B2 - - Google Patents

Info

Publication number
JPS528229B2
JPS528229B2 JP48054847A JP5484773A JPS528229B2 JP S528229 B2 JPS528229 B2 JP S528229B2 JP 48054847 A JP48054847 A JP 48054847A JP 5484773 A JP5484773 A JP 5484773A JP S528229 B2 JPS528229 B2 JP S528229B2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP48054847A
Other languages
Japanese (ja)
Other versions
JPS4945688A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS4945688A publication Critical patent/JPS4945688A/ja
Publication of JPS528229B2 publication Critical patent/JPS528229B2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
JP48054847A 1972-06-30 1973-05-18 Expired JPS528229B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US26777172A 1972-06-30 1972-06-30

Publications (2)

Publication Number Publication Date
JPS4945688A JPS4945688A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1974-05-01
JPS528229B2 true JPS528229B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1977-03-08

Family

ID=23020055

Family Applications (1)

Application Number Title Priority Date Filing Date
JP48054847A Expired JPS528229B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1972-06-30 1973-05-18

Country Status (6)

Country Link
JP (1) JPS528229B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CA (1) CA1005925A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE2318912A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
FR (1) FR2191270B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB (1) GB1422586A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
IT (1) IT987426B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2554450A1 (de) * 1975-12-03 1977-06-16 Siemens Ag Verfahren zur herstellung einer integrierten schaltung
DE2720533A1 (de) * 1977-05-06 1978-11-09 Siemens Ag Monolithisch integrierte schaltungsanordnung mit ein-transistor- speicherelementen
CA1186808A (en) * 1981-11-06 1985-05-07 Sidney I. Soclof Method of fabrication of dielectrically isolated cmos device with an isolated slot
JPS58100441A (ja) * 1981-12-10 1983-06-15 Toshiba Corp 半導体装置の製造方法
JPS58212165A (ja) * 1983-05-23 1983-12-09 Nec Corp 半導体装置
JPH0616549B2 (ja) * 1984-04-17 1994-03-02 三菱電機株式会社 半導体集積回路装置
JP2003124514A (ja) * 2001-10-17 2003-04-25 Sony Corp 半導体発光素子及びその製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL153374B (nl) * 1966-10-05 1977-05-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting voorzien van een oxydelaag en halfgeleiderinrichting vervaardigd volgens de werkwijze.
FR2079612A5 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1970-02-06 1971-11-12 Radiotechnique Compelec
US3698966A (en) * 1970-02-26 1972-10-17 North American Rockwell Processes using a masking layer for producing field effect devices having oxide isolation
US3859717A (en) * 1970-12-21 1975-01-14 Rockwell International Corp Method of manufacturing control electrodes for charge coupled circuits and the like
US3751722A (en) * 1971-04-30 1973-08-07 Standard Microsyst Smc Mos integrated circuit with substrate containing selectively formed resistivity regions

Also Published As

Publication number Publication date
CA1005925A (en) 1977-02-22
FR2191270A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1974-02-01
FR2191270B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1977-07-29
DE2318912A1 (de) 1974-01-17
IT987426B (it) 1975-02-20
GB1422586A (en) 1976-01-28
JPS4945688A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1974-05-01

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