JPS5226124A - Buffer memory control unit - Google Patents

Buffer memory control unit

Info

Publication number
JPS5226124A
JPS5226124A JP50101750A JP10175075A JPS5226124A JP S5226124 A JPS5226124 A JP S5226124A JP 50101750 A JP50101750 A JP 50101750A JP 10175075 A JP10175075 A JP 10175075A JP S5226124 A JPS5226124 A JP S5226124A
Authority
JP
Japan
Prior art keywords
buffer memory
control unit
memory control
processing
specifying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50101750A
Other languages
English (en)
Japanese (ja)
Inventor
Takashi Chiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP50101750A priority Critical patent/JPS5226124A/ja
Priority to DE2637054A priority patent/DE2637054C3/de
Priority to US05/715,862 priority patent/US4115855A/en
Priority to FR7625371A priority patent/FR2321747A1/fr
Priority to GB35084/76A priority patent/GB1551450A/en
Publication of JPS5226124A publication Critical patent/JPS5226124A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G06F12/125—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list being generated by decoding an array or storage

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Information Transfer Systems (AREA)
JP50101750A 1975-08-22 1975-08-22 Buffer memory control unit Pending JPS5226124A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP50101750A JPS5226124A (en) 1975-08-22 1975-08-22 Buffer memory control unit
DE2637054A DE2637054C3 (de) 1975-08-22 1976-08-18 Steuervorrichtung für einen Pufferspeicher
US05/715,862 US4115855A (en) 1975-08-22 1976-08-19 Buffer memory control device having priority control units for priority processing set blocks and unit blocks in a buffer memory
FR7625371A FR2321747A1 (fr) 1975-08-22 1976-08-20 Dispositif de commande d'une memoire tampon
GB35084/76A GB1551450A (en) 1975-08-22 1976-08-23 Buffer memory apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50101750A JPS5226124A (en) 1975-08-22 1975-08-22 Buffer memory control unit

Publications (1)

Publication Number Publication Date
JPS5226124A true JPS5226124A (en) 1977-02-26

Family

ID=14308905

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50101750A Pending JPS5226124A (en) 1975-08-22 1975-08-22 Buffer memory control unit

Country Status (5)

Country Link
US (1) US4115855A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS5226124A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE2637054C3 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
FR (1) FR2321747A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB (1) GB1551450A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58121455A (ja) * 1982-01-13 1983-07-19 Mamoru Tanaka 優先回路
JPS6165350A (ja) * 1984-09-05 1986-04-03 シーメンス、アクチエンゲゼルシヤフト 優先順位割当て装置
JPH0354372B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1982-09-22 1991-08-20

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2659662C3 (de) * 1976-12-30 1981-10-08 Ibm Deutschland Gmbh, 7000 Stuttgart Prioritätsstufengesteuerte Unterbrechungseinrichtung
US4361878A (en) * 1980-10-27 1982-11-30 Control Data Corporation Degradable LRU circuit
JPS58102381A (ja) * 1981-12-15 1983-06-17 Nec Corp バツフアメモリ
US4511994A (en) * 1982-09-27 1985-04-16 Control Data Corporation Multi-group LRU resolver
US4680702A (en) * 1984-04-27 1987-07-14 Honeywell Information Systems Inc. Merge control apparatus for a store into cache of a data processing system
EP0173556A3 (en) * 1984-08-31 1987-05-27 Texas Instruments Incorporated Hierarchical architecture for determining the least recently used cache memory
GB2167583B (en) * 1984-11-23 1988-11-02 Nat Res Dev Apparatus and methods for processing an array of items of data
EP0309712A3 (de) * 1987-09-30 1990-06-20 Siemens Aktiengesellschaft Anordnung zur Realisierung eines LRU (Least Recently Used) - ähnlichem Mechanismus für mehr als drei Elemente durch Binär-Matrix-Bäume
EP0309737A3 (de) * 1987-09-30 1990-06-20 Siemens Aktiengesellschaft Anordnung zur Realisierung eines LRU (Least Recently Used) - ähnlichem Mechanismus für mehr als drei Elemente durch Binär-Matrix-Bäume
US5089957A (en) * 1989-11-14 1992-02-18 National Semiconductor Corporation Ram based events counter apparatus and method
US5532841A (en) * 1990-07-31 1996-07-02 Minolta Camera Kabushiki Kaisha Facsimile apparatus comprising a plurality of image reading units
US5983313A (en) * 1996-04-10 1999-11-09 Ramtron International Corporation EDRAM having a dynamically-sized cache memory and associated method
US6260090B1 (en) * 1999-03-03 2001-07-10 International Business Machines Corporation Circuit arrangement and method incorporating data buffer with priority-based data storage
US7284064B1 (en) 2000-03-21 2007-10-16 Intel Corporation Method and apparatus to determine broadcast content and scheduling in a broadcast system
US7275254B1 (en) 2000-11-21 2007-09-25 Intel Corporation Method and apparatus for determining and displaying the service level of a digital television broadcast signal
US20020144265A1 (en) * 2001-03-29 2002-10-03 Connelly Jay H. System and method for merging streaming and stored content information in an electronic program guide
US20020144269A1 (en) * 2001-03-30 2002-10-03 Connelly Jay H. Apparatus and method for a dynamic electronic program guide enabling billing broadcast services per EPG line item
US7328455B2 (en) * 2001-06-28 2008-02-05 Intel Corporation Apparatus and method for enabling secure content decryption within a set-top box
US20030046683A1 (en) * 2001-08-28 2003-03-06 Jutzi Curtis E. Server-side preference prediction based on customer billing information to generate a broadcast schedule
US8943540B2 (en) 2001-09-28 2015-01-27 Intel Corporation Method and apparatus to provide a personalized channel
US20030135605A1 (en) * 2002-01-11 2003-07-17 Ramesh Pendakur User rating feedback loop to modify virtual channel content and/or schedules
US6831587B1 (en) * 2003-07-31 2004-12-14 Micron Technology, Inc. Priority encoding
US8984198B2 (en) * 2009-07-21 2015-03-17 Microchip Technology Incorporated Data space arbiter

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3331055A (en) * 1964-06-01 1967-07-11 Sperry Rand Corp Data communication system with matrix selection of line terminals
US3353160A (en) * 1965-06-09 1967-11-14 Ibm Tree priority circuit
US3588829A (en) * 1968-11-14 1971-06-28 Ibm Integrated memory system with block transfer to a buffer store
NL154023B (nl) * 1969-02-01 1977-07-15 Philips Nv Prioriteitscircuit.
US3611305A (en) * 1969-02-10 1971-10-05 Scanders Associates Inc Data processor interrupt system
US3820078A (en) * 1972-10-05 1974-06-25 Honeywell Inf Systems Multi-level storage system having a buffer store with variable mapping modes
US3911401A (en) * 1973-06-04 1975-10-07 Ibm Hierarchial memory/storage system for an electronic computer
US3964028A (en) * 1973-08-02 1976-06-15 International Business Machines Corporation System and method for evaluating paging behavior
US3840862A (en) * 1973-09-27 1974-10-08 Honeywell Inf Systems Status indicator apparatus for tag directory in associative stores
US3979726A (en) * 1974-04-10 1976-09-07 Honeywell Information Systems, Inc. Apparatus for selectively clearing a cache store in a processor having segmentation and paging
FR116049A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1975-03-20

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58121455A (ja) * 1982-01-13 1983-07-19 Mamoru Tanaka 優先回路
JPH0354372B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1982-09-22 1991-08-20
JPS6165350A (ja) * 1984-09-05 1986-04-03 シーメンス、アクチエンゲゼルシヤフト 優先順位割当て装置

Also Published As

Publication number Publication date
DE2637054A1 (de) 1977-02-24
US4115855A (en) 1978-09-19
GB1551450A (en) 1979-08-30
DE2637054C3 (de) 1981-10-22
FR2321747B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1982-02-05
FR2321747A1 (fr) 1977-03-18
DE2637054B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1981-01-08

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