JPS5128829B1 - - Google Patents
Info
- Publication number
- JPS5128829B1 JPS5128829B1 JP43076079A JP7607968A JPS5128829B1 JP S5128829 B1 JPS5128829 B1 JP S5128829B1 JP 43076079 A JP43076079 A JP 43076079A JP 7607968 A JP7607968 A JP 7607968A JP S5128829 B1 JPS5128829 B1 JP S5128829B1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
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- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/12—Passive devices, e.g. 2 terminal devices
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- H01L2924/12041—LED
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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- H01L2924/19043—Component type being a resistor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Casings For Electric Apparatus (AREA)
- Thermistors And Varistors (AREA)
- Connections Arranged To Contact A Plurality Of Conductors (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP43076079A JPS5128829B1 (ja) | 1968-10-21 | 1968-10-21 | |
GB50245/69A GB1277254A (en) | 1968-10-21 | 1969-10-13 | Hermetically sealed package for use in electronic components |
FR6935663A FR2023323A1 (ja) | 1968-10-21 | 1969-10-17 | |
DE1952789A DE1952789C3 (de) | 1968-10-21 | 1969-10-20 | Luftdichte Kapselung für elektronische Bauelemente |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP43076079A JPS5128829B1 (ja) | 1968-10-21 | 1968-10-21 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5128829B1 true JPS5128829B1 (ja) | 1976-08-21 |
Family
ID=13594790
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP43076079A Pending JPS5128829B1 (ja) | 1968-10-21 | 1968-10-21 |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPS5128829B1 (ja) |
DE (1) | DE1952789C3 (ja) |
FR (1) | FR2023323A1 (ja) |
GB (1) | GB1277254A (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5615059U (ja) * | 1979-07-11 | 1981-02-09 | ||
JPS5651846A (en) * | 1979-10-04 | 1981-05-09 | Fujitsu Ltd | Ic package |
US4320438A (en) * | 1980-05-15 | 1982-03-16 | Cts Corporation | Multi-layer ceramic package |
DE3125360A1 (de) * | 1981-06-27 | 1983-01-13 | Robert Bosch Gmbh, 7000 Stuttgart | "elektronisches bauelement" |
DE3147789A1 (de) * | 1981-12-03 | 1983-06-09 | Brown, Boveri & Cie Ag, 6800 Mannheim | Leistungsmodul und verfahren zu seiner herstellung |
DE3147790A1 (de) * | 1981-12-03 | 1983-06-09 | Brown, Boveri & Cie Ag, 6800 Mannheim | Leistungsmodul und verfahren zu seiner herstellung |
JPS5987893A (ja) * | 1982-11-12 | 1984-05-21 | 株式会社日立製作所 | 配線基板とその製造方法およびそれを用いた半導体装置 |
US4750092A (en) * | 1985-11-20 | 1988-06-07 | Kollmorgen Technologies Corporation | Interconnection package suitable for electronic devices and methods for producing same |
DE3703280A1 (de) * | 1987-02-04 | 1988-08-18 | Licentia Gmbh | Schaltungsanordnung mit einem oder mehreren integrierten schaltkreisen |
GB2209867B (en) * | 1987-09-16 | 1990-12-19 | Advanced Semiconductor Package | Method of forming an integrated circuit chip carrier |
US5702985A (en) * | 1992-06-26 | 1997-12-30 | Staktek Corporation | Hermetically sealed ceramic integrated circuit heat dissipating package fabrication method |
DE19548050A1 (de) * | 1995-12-21 | 1997-06-26 | Siemens Matsushita Components | Elektronisches Bauelement, insbesondere mit akustischen Oberflächenwellen arbeitendes Bauelement - OFW-Bauelement - |
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1968
- 1968-10-21 JP JP43076079A patent/JPS5128829B1/ja active Pending
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1969
- 1969-10-13 GB GB50245/69A patent/GB1277254A/en not_active Expired
- 1969-10-17 FR FR6935663A patent/FR2023323A1/fr not_active Withdrawn
- 1969-10-20 DE DE1952789A patent/DE1952789C3/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
DE1952789A1 (de) | 1970-04-30 |
GB1277254A (en) | 1972-06-07 |
DE1952789B2 (de) | 1971-09-30 |
DE1952789C3 (de) | 1974-04-18 |
FR2023323A1 (ja) | 1970-08-21 |