JPS5093370A - - Google Patents
Info
- Publication number
- JPS5093370A JPS5093370A JP49144922A JP14492274A JPS5093370A JP S5093370 A JPS5093370 A JP S5093370A JP 49144922 A JP49144922 A JP 49144922A JP 14492274 A JP14492274 A JP 14492274A JP S5093370 A JPS5093370 A JP S5093370A
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/0813—Threshold logic
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Manipulation Of Pulses (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US00425217A US3838393A (en) | 1973-12-17 | 1973-12-17 | Threshold logic gate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5093370A true JPS5093370A (ja) | 1975-07-25 |
| JPS5654092B2 JPS5654092B2 (ja) | 1981-12-23 |
Family
ID=23685656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14492274A Expired JPS5654092B2 (ja) | 1973-12-17 | 1974-12-17 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US3838393A (ja) |
| JP (1) | JPS5654092B2 (ja) |
| CA (1) | CA1008517A (ja) |
| DE (1) | DE2455498C3 (ja) |
| FR (1) | FR2254914B1 (ja) |
| GB (1) | GB1460215A (ja) |
| NL (1) | NL7415048A (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009061269A (ja) * | 2007-09-04 | 2009-03-26 | Lg Electronics Inc | ダクトレス乾燥機 |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4081822A (en) * | 1975-06-30 | 1978-03-28 | Signetics Corporation | Threshold integrated injection logic |
| GB1584724A (en) * | 1977-07-14 | 1981-02-18 | Philips Electronic Associated | Integrated injection logic circuits |
| NL7804673A (nl) * | 1978-05-02 | 1979-11-06 | Philips Nv | Systeem voor het overdragen van binaire informatie over een aantal kanalen. |
| US4251884A (en) * | 1979-02-09 | 1981-02-17 | Bell Telephone Laboratories, Incorporated | Parity circuits |
| US4617475A (en) * | 1984-03-30 | 1986-10-14 | Trilogy Computer Development Partners, Ltd. | Wired logic voting circuit |
| US4638482A (en) * | 1984-12-24 | 1987-01-20 | International Business Machines Corporation | Random logic error detecting system for differential logic networks |
| DE3829164C1 (ja) * | 1988-08-27 | 1989-08-10 | Ant Nachrichtentechnik Gmbh, 7150 Backnang, De | |
| US5608741A (en) * | 1993-11-23 | 1997-03-04 | Intel Corporation | Fast parity generator using complement pass-transistor logic |
| JP3217993B2 (ja) * | 1997-07-09 | 2001-10-15 | 沖電気工業株式会社 | パリティチェック回路 |
| US7114055B1 (en) * | 2003-09-29 | 2006-09-26 | Xilinx, Inc. | Reduced instruction set computer architecture with duplication of bit values from an immediate field of an instruction multiple times in a data word |
| US10003342B2 (en) * | 2014-12-02 | 2018-06-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Compressor circuit and compressor circuit layout |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3150350A (en) * | 1961-01-04 | 1964-09-22 | Gen Precision Inc | Parallel parity checker |
| US3439328A (en) * | 1964-08-19 | 1969-04-15 | Rca Corp | Parity circuits employing threshold gates |
| US3597626A (en) * | 1969-04-01 | 1971-08-03 | Bell Telephone Labor Inc | Threshold logic gate |
| US3678292A (en) * | 1970-08-06 | 1972-07-18 | Rca Corp | Multi-function logic gate circuits |
-
1973
- 1973-12-17 US US00425217A patent/US3838393A/en not_active Expired - Lifetime
-
1974
- 1974-10-22 CA CA211,933A patent/CA1008517A/en not_active Expired
- 1974-10-22 GB GB4565174A patent/GB1460215A/en not_active Expired
- 1974-11-19 NL NL7415048A patent/NL7415048A/xx not_active Application Discontinuation
- 1974-11-23 DE DE2455498A patent/DE2455498C3/de not_active Expired
- 1974-12-16 FR FR7441340A patent/FR2254914B1/fr not_active Expired
- 1974-12-17 JP JP14492274A patent/JPS5654092B2/ja not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009061269A (ja) * | 2007-09-04 | 2009-03-26 | Lg Electronics Inc | ダクトレス乾燥機 |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2254914A1 (ja) | 1975-07-11 |
| JPS5654092B2 (ja) | 1981-12-23 |
| DE2455498C3 (de) | 1981-08-27 |
| DE2455498B2 (de) | 1980-11-13 |
| CA1008517A (en) | 1977-04-12 |
| US3838393A (en) | 1974-09-24 |
| NL7415048A (nl) | 1975-06-19 |
| DE2455498A1 (de) | 1975-06-19 |
| GB1460215A (en) | 1976-12-31 |
| FR2254914B1 (ja) | 1979-06-01 |