FR2254914B1 - - Google Patents

Info

Publication number
FR2254914B1
FR2254914B1 FR7441340A FR7441340A FR2254914B1 FR 2254914 B1 FR2254914 B1 FR 2254914B1 FR 7441340 A FR7441340 A FR 7441340A FR 7441340 A FR7441340 A FR 7441340A FR 2254914 B1 FR2254914 B1 FR 2254914B1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7441340A
Other versions
FR2254914A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Signetics Corp
Original Assignee
Signetics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Signetics Corp filed Critical Signetics Corp
Publication of FR2254914A1 publication Critical patent/FR2254914A1/fr
Application granted granted Critical
Publication of FR2254914B1 publication Critical patent/FR2254914B1/fr
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/0813Threshold logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
FR7441340A 1973-12-17 1974-12-16 Expired FR2254914B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00425217A US3838393A (en) 1973-12-17 1973-12-17 Threshold logic gate

Publications (2)

Publication Number Publication Date
FR2254914A1 FR2254914A1 (fr) 1975-07-11
FR2254914B1 true FR2254914B1 (fr) 1979-06-01

Family

ID=23685656

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7441340A Expired FR2254914B1 (fr) 1973-12-17 1974-12-16

Country Status (7)

Country Link
US (1) US3838393A (fr)
JP (1) JPS5654092B2 (fr)
CA (1) CA1008517A (fr)
DE (1) DE2455498C3 (fr)
FR (1) FR2254914B1 (fr)
GB (1) GB1460215A (fr)
NL (1) NL7415048A (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4081822A (en) * 1975-06-30 1978-03-28 Signetics Corporation Threshold integrated injection logic
GB1584724A (en) * 1977-07-14 1981-02-18 Philips Electronic Associated Integrated injection logic circuits
NL7804673A (nl) * 1978-05-02 1979-11-06 Philips Nv Systeem voor het overdragen van binaire informatie over een aantal kanalen.
US4251884A (en) * 1979-02-09 1981-02-17 Bell Telephone Laboratories, Incorporated Parity circuits
US4617475A (en) * 1984-03-30 1986-10-14 Trilogy Computer Development Partners, Ltd. Wired logic voting circuit
US4638482A (en) * 1984-12-24 1987-01-20 International Business Machines Corporation Random logic error detecting system for differential logic networks
DE3829164C1 (fr) * 1988-08-27 1989-08-10 Ant Nachrichtentechnik Gmbh, 7150 Backnang, De
US5608741A (en) * 1993-11-23 1997-03-04 Intel Corporation Fast parity generator using complement pass-transistor logic
JP3217993B2 (ja) * 1997-07-09 2001-10-15 沖電気工業株式会社 パリティチェック回路
US7114055B1 (en) * 2003-09-29 2006-09-26 Xilinx, Inc. Reduced instruction set computer architecture with duplication of bit values from an immediate field of an instruction multiple times in a data word
KR100901716B1 (ko) * 2007-09-04 2009-06-08 엘지전자 주식회사 덕트리스 건조기
US10003342B2 (en) * 2014-12-02 2018-06-19 Taiwan Semiconductor Manufacturing Company, Ltd. Compressor circuit and compressor circuit layout

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3150350A (en) * 1961-01-04 1964-09-22 Gen Precision Inc Parallel parity checker
US3439328A (en) * 1964-08-19 1969-04-15 Rca Corp Parity circuits employing threshold gates
US3597626A (en) * 1969-04-01 1971-08-03 Bell Telephone Labor Inc Threshold logic gate
US3678292A (en) * 1970-08-06 1972-07-18 Rca Corp Multi-function logic gate circuits

Also Published As

Publication number Publication date
US3838393A (en) 1974-09-24
JPS5654092B2 (fr) 1981-12-23
DE2455498B2 (de) 1980-11-13
FR2254914A1 (fr) 1975-07-11
CA1008517A (en) 1977-04-12
NL7415048A (nl) 1975-06-19
GB1460215A (en) 1976-12-31
DE2455498A1 (de) 1975-06-19
JPS5093370A (fr) 1975-07-25
DE2455498C3 (de) 1981-08-27

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Legal Events

Date Code Title Description
ST Notification of lapse