JPS5013153B1 - - Google Patents
Info
- Publication number
- JPS5013153B1 JPS5013153B1 JP45106832A JP10683270A JPS5013153B1 JP S5013153 B1 JPS5013153 B1 JP S5013153B1 JP 45106832 A JP45106832 A JP 45106832A JP 10683270 A JP10683270 A JP 10683270A JP S5013153 B1 JPS5013153 B1 JP S5013153B1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
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- H10P95/00—
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/02—Contacts, special
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/145—Shaped junctions
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/162—Testing steps
Landscapes
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP45106832A JPS5013153B1 (Direct) | 1970-12-04 | 1970-12-04 | |
| US00203384A US3846167A (en) | 1970-12-04 | 1971-11-30 | Method of manufacturing semiconductor devices |
| DE2159685A DE2159685C3 (de) | 1970-12-04 | 1971-12-01 | Verfahren zum Herstellen einer Halbleiteranordnung mit mehreren bipolaren Transistoren oder anderen wenigstens einen PN-Übergang aufweisenden Halbleiterbauelementen |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP45106832A JPS5013153B1 (Direct) | 1970-12-04 | 1970-12-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5013153B1 true JPS5013153B1 (Direct) | 1975-05-17 |
Family
ID=14443702
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP45106832A Pending JPS5013153B1 (Direct) | 1970-12-04 | 1970-12-04 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US3846167A (Direct) |
| JP (1) | JPS5013153B1 (Direct) |
| DE (1) | DE2159685C3 (Direct) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0296348B1 (de) * | 1987-05-27 | 1993-03-31 | Siemens Aktiengesellschaft | Ätzverfahren zum Erzeugen von Lochöffnungen oder Gräben in n-dotiertem Silizium |
-
1970
- 1970-12-04 JP JP45106832A patent/JPS5013153B1/ja active Pending
-
1971
- 1971-11-30 US US00203384A patent/US3846167A/en not_active Expired - Lifetime
- 1971-12-01 DE DE2159685A patent/DE2159685C3/de not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE2159685A1 (de) | 1972-09-07 |
| DE2159685C3 (de) | 1980-04-10 |
| US3846167A (en) | 1974-11-05 |
| DE2159685B2 (de) | 1974-08-29 |