JPS50131493A - - Google Patents
Info
- Publication number
- JPS50131493A JPS50131493A JP50036536A JP3653675A JPS50131493A JP S50131493 A JPS50131493 A JP S50131493A JP 50036536 A JP50036536 A JP 50036536A JP 3653675 A JP3653675 A JP 3653675A JP S50131493 A JPS50131493 A JP S50131493A
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07231—Techniques
- H10W72/07236—Soldering or alloying
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Structure Of Printed Boards (AREA)
- Semiconductor Integrated Circuits (AREA)
- Static Random-Access Memory (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Combinations Of Printed Boards (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE2415047 | 1974-03-28 | ||
| DE19742415047 DE2415047B2 (de) | 1974-03-28 | 1974-03-28 | Multichip-verdrahtung mit anschlussflaechenkonfigurationen zur kontaktierung von vier gleichen halbleiterspeicher-chips |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS50131493A true JPS50131493A (en:Method) | 1975-10-17 |
| JPS5836512B2 JPS5836512B2 (ja) | 1983-08-09 |
Family
ID=5911463
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50036536A Expired JPS5836512B2 (ja) | 1974-03-28 | 1975-03-26 | 半導体メモリチツプの接続のための端子面配列を持つマルチチツプ配線 |
Country Status (8)
| Country | Link |
|---|---|
| JP (1) | JPS5836512B2 (en:Method) |
| BE (1) | BE827367A (en:Method) |
| DE (1) | DE2415047B2 (en:Method) |
| FR (1) | FR2266305B1 (en:Method) |
| GB (1) | GB1464080A (en:Method) |
| IT (1) | IT1034529B (en:Method) |
| NL (1) | NL7502773A (en:Method) |
| SE (1) | SE7503369L (en:Method) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3033900C3 (de) * | 1980-09-09 | 1994-12-15 | Siemens Ag | Gehäuseloses Schaltungsmodul und Verfahren zu seiner Herstellung |
| DE3123620A1 (de) * | 1981-06-13 | 1983-01-05 | Telefonbau Und Normalzeit Gmbh, 6000 Frankfurt | Anordnung zum verbinden eines speichers mit einer steuereinrichtung |
| JPS57207356A (en) * | 1981-06-15 | 1982-12-20 | Fujitsu Ltd | Semiconductor device |
| JPH0279123U (en:Method) * | 1988-12-02 | 1990-06-18 | ||
| JPH02285910A (ja) * | 1989-04-26 | 1990-11-26 | Seijiro Isoi | 鳥休止防止具 |
| JPH052533U (ja) * | 1991-02-25 | 1993-01-14 | マサル工業株式会社 | 電線保護カバー |
| GB2312562B (en) * | 1996-04-26 | 2000-05-17 | Appliance Control Technology E | A method of interconnecting wiring with a pcb |
-
1974
- 1974-03-28 DE DE19742415047 patent/DE2415047B2/de active Granted
-
1975
- 1975-03-07 NL NL7502773A patent/NL7502773A/xx not_active Application Discontinuation
- 1975-03-21 GB GB1180675A patent/GB1464080A/en not_active Expired
- 1975-03-21 FR FR7508898A patent/FR2266305B1/fr not_active Expired
- 1975-03-24 SE SE7503369A patent/SE7503369L/xx unknown
- 1975-03-26 IT IT21645/75A patent/IT1034529B/it active
- 1975-03-26 JP JP50036536A patent/JPS5836512B2/ja not_active Expired
- 1975-03-28 BE BE154933A patent/BE827367A/xx unknown
Also Published As
| Publication number | Publication date |
|---|---|
| DE2415047A1 (de) | 1975-10-16 |
| JPS5836512B2 (ja) | 1983-08-09 |
| FR2266305A1 (en:Method) | 1975-10-24 |
| DE2415047C3 (en:Method) | 1978-09-21 |
| FR2266305B1 (en:Method) | 1978-02-24 |
| BE827367A (fr) | 1975-07-16 |
| DE2415047B2 (de) | 1978-02-02 |
| GB1464080A (en) | 1977-02-09 |
| NL7502773A (nl) | 1975-09-30 |
| IT1034529B (it) | 1979-10-10 |
| SE7503369L (en:Method) | 1975-09-29 |