JPS4969273A - - Google Patents

Info

Publication number
JPS4969273A
JPS4969273A JP48102290A JP10229073A JPS4969273A JP S4969273 A JPS4969273 A JP S4969273A JP 48102290 A JP48102290 A JP 48102290A JP 10229073 A JP10229073 A JP 10229073A JP S4969273 A JPS4969273 A JP S4969273A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP48102290A
Other languages
Japanese (ja)
Other versions
JPS5244715B2 (en:Method
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS4969273A publication Critical patent/JPS4969273A/ja
Publication of JPS5244715B2 publication Critical patent/JPS5244715B2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/211Design considerations for internal polarisation
    • H10D89/213Design considerations for internal polarisation in field-effect devices
    • H10D89/215Design considerations for internal polarisation in field-effect devices comprising arrangements for charge pumping or biasing substrates
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • G05F3/08Regulating voltage or current wherein the variable is DC
    • G05F3/10Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205Substrate bias-voltage generators
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401Combinations of FETs or IGBTs with BJTs
    • H10D84/403Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors
    • H10D84/406Combinations of FETs or IGBTs with vertical BJTs and with one or more of diodes, resistors or capacitors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85Complementary IGFETs, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Automation & Control Theory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Bipolar Transistors (AREA)
JP48102290A 1972-09-15 1973-09-12 Expired JPS5244715B2 (en:Method)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7212509A NL7212509A (en:Method) 1972-09-15 1972-09-15

Publications (2)

Publication Number Publication Date
JPS4969273A true JPS4969273A (en:Method) 1974-07-04
JPS5244715B2 JPS5244715B2 (en:Method) 1977-11-10

Family

ID=19816940

Family Applications (1)

Application Number Title Priority Date Filing Date
JP48102290A Expired JPS5244715B2 (en:Method) 1972-09-15 1973-09-12

Country Status (9)

Country Link
US (1) US4255677A (en:Method)
JP (1) JPS5244715B2 (en:Method)
AU (1) AU465865B2 (en:Method)
CA (1) CA993571A (en:Method)
DE (1) DE2341899C3 (en:Method)
FR (1) FR2200634B1 (en:Method)
GB (1) GB1450167A (en:Method)
IT (1) IT996680B (en:Method)
NL (1) NL7212509A (en:Method)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS525281A (en) * 1975-06-30 1977-01-14 Ibm Substrate bias circuit

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2839073C2 (de) * 1978-09-07 1983-02-17 Siemens AG, 1000 Berlin und 8000 München Dynamische Stromquelle für Halbleiterbausteine und ihre Verwendung
JPS55162257A (en) * 1979-06-05 1980-12-17 Fujitsu Ltd Semiconductor element having substrate bias generator circuit
JPS6038028B2 (ja) * 1979-07-23 1985-08-29 三菱電機株式会社 基板電位発生装置
JPS5619676A (en) * 1979-07-26 1981-02-24 Fujitsu Ltd Semiconductor device
DE3067215D1 (en) * 1979-12-13 1984-04-26 Fujitsu Ltd Charge-pumping semiconductor memory cell comprising a charge-storage region and memory device using such a cell
JPS5771222U (en:Method) * 1980-10-16 1982-04-30
US4559548A (en) * 1981-04-07 1985-12-17 Tokyo Shibaura Denki Kabushiki Kaisha CMOS Charge pump free of parasitic injection
JPS58122766A (ja) * 1982-01-14 1983-07-21 Toshiba Corp 半導体装置
US4704625A (en) * 1982-08-05 1987-11-03 Motorola, Inc. Capacitor with reduced voltage variability
US4670669A (en) * 1984-08-13 1987-06-02 International Business Machines Corporation Charge pumping structure for a substrate bias generator
ATE75877T1 (de) * 1985-08-26 1992-05-15 Siemens Ag Integrierte schaltung in komplementaerer schaltungstechnik mit einem substratvorspannungs- generator und einer schottky-diode.
US5286986A (en) * 1989-04-13 1994-02-15 Kabushiki Kaisha Toshiba Semiconductor device having CCD and its peripheral bipolar transistors
JPH07105458B2 (ja) * 1989-11-21 1995-11-13 株式会社東芝 複合型集積回路素子
JP2968836B2 (ja) * 1990-11-30 1999-11-02 日本テキサス・インスツルメンツ株式会社 半導体基板電位発生回路
US5364801A (en) * 1990-12-17 1994-11-15 Texas Instruments Incorporated Method of forming a charge pump circuit
US6825878B1 (en) 1998-12-08 2004-11-30 Micron Technology, Inc. Twin P-well CMOS imager

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3816769A (en) * 1969-12-17 1974-06-11 Integrated Photomatrix Ltd Method and circuit element for the selective charging of a semiconductor diffusion region
US3673428A (en) * 1970-09-18 1972-06-27 Rca Corp Input transient protection for complementary insulated gate field effect transistor integrated circuit device
AU461729B2 (en) * 1971-01-14 1975-06-05 Rca Corporation Charge coupled circuits
BE789501A (fr) * 1971-09-30 1973-03-29 Siemens Ag Condensateur electrique dans un circuit integre, utilise notamment comme memoire pour une memoire a semiconducteur

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS525281A (en) * 1975-06-30 1977-01-14 Ibm Substrate bias circuit

Also Published As

Publication number Publication date
FR2200634B1 (en:Method) 1978-01-06
DE2341899A1 (de) 1974-03-21
DE2341899C3 (de) 1979-10-04
DE2341899B2 (de) 1979-02-08
NL7212509A (en:Method) 1974-03-19
JPS5244715B2 (en:Method) 1977-11-10
AU6021473A (en) 1975-03-13
US4255677A (en) 1981-03-10
GB1450167A (en) 1976-09-22
FR2200634A1 (en:Method) 1974-04-19
CA993571A (en) 1976-07-20
AU465865B2 (en) 1975-10-09
IT996680B (it) 1975-12-10

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