JPS4840805B1 - - Google Patents

Info

Publication number
JPS4840805B1
JPS4840805B1 JP45116919A JP11691970A JPS4840805B1 JP S4840805 B1 JPS4840805 B1 JP S4840805B1 JP 45116919 A JP45116919 A JP 45116919A JP 11691970 A JP11691970 A JP 11691970A JP S4840805 B1 JPS4840805 B1 JP S4840805B1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP45116919A
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS4840805B1 publication Critical patent/JPS4840805B1/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1404Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass

Landscapes

  • Bipolar Transistors (AREA)
JP45116919A 1970-02-20 1970-12-24 Pending JPS4840805B1 (https=)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US1297770A 1970-02-20 1970-02-20

Publications (1)

Publication Number Publication Date
JPS4840805B1 true JPS4840805B1 (https=) 1973-12-03

Family

ID=21757664

Family Applications (1)

Application Number Title Priority Date Filing Date
JP45116919A Pending JPS4840805B1 (https=) 1970-02-20 1970-12-24

Country Status (4)

Country Link
US (1) US3676231A (https=)
JP (1) JPS4840805B1 (https=)
DE (1) DE2107991A1 (https=)
FR (1) FR2081021B1 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3959040A (en) * 1971-09-01 1976-05-25 Motorola, Inc. Compound diffused regions for emitter-coupled logic circuits
US4129090A (en) * 1973-02-28 1978-12-12 Hitachi, Ltd. Apparatus for diffusion into semiconductor wafers
US3966515A (en) * 1974-05-17 1976-06-29 Teledyne, Inc. Method for manufacturing high voltage field-effect transistors
DE2838928A1 (de) * 1978-09-07 1980-03-20 Ibm Deutschland Verfahren zum dotieren von siliciumkoerpern mit bor
US4234361A (en) * 1979-07-05 1980-11-18 Wisconsin Alumni Research Foundation Process for producing an electrostatically deformable thin silicon membranes utilizing a two-stage diffusion step to form an etchant resistant layer
US5494852A (en) * 1993-07-28 1996-02-27 Sony Electronics Inc. High capacity semiconductor dopant deposition/oxidization process using a single furnace cycle
DE19840866B4 (de) * 1998-08-31 2005-02-03 IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik Verfahren zur Dotierung der externen Basisanschlußgebiete von Si-basierten Einfach-Polysilizium-npn-Bipolartransistoren
DE102012025429A1 (de) * 2012-12-21 2014-06-26 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur Dotierung von Halbleitersubstraten sowie dotiertes Halbleitersubstrat

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1115140A (en) * 1966-12-30 1968-05-29 Standard Telephones Cables Ltd Semiconductors
US3542609A (en) * 1967-11-22 1970-11-24 Itt Double depositions of bbr3 in silicon

Also Published As

Publication number Publication date
US3676231A (en) 1972-07-11
FR2081021A1 (https=) 1971-11-26
DE2107991A1 (de) 1971-08-26
FR2081021B1 (https=) 1974-03-01

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