JPS48103143A - - Google Patents

Info

Publication number
JPS48103143A
JPS48103143A JP48021161A JP2116173A JPS48103143A JP S48103143 A JPS48103143 A JP S48103143A JP 48021161 A JP48021161 A JP 48021161A JP 2116173 A JP2116173 A JP 2116173A JP S48103143 A JPS48103143 A JP S48103143A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP48021161A
Other languages
Japanese (ja)
Other versions
JPS5734534B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS48103143A publication Critical patent/JPS48103143A/ja
Publication of JPS5734534B2 publication Critical patent/JPS5734534B2/ja
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/328—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for runtime instruction patching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/24—Loading of the microprogram

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
JP2116173A 1972-03-08 1973-02-21 Expired JPS5734534B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US23288072A 1972-03-08 1972-03-08

Publications (2)

Publication Number Publication Date
JPS48103143A true JPS48103143A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1973-12-25
JPS5734534B2 JPS5734534B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1982-07-23

Family

ID=22874973

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2116173A Expired JPS5734534B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1972-03-08 1973-02-21

Country Status (9)

Country Link
US (1) US3792441A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS5734534B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
BE (1) BE795789A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
BR (1) BR7301467D0 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE2306115C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
FR (1) FR2175433A5 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB (1) GB1391412A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
IT (1) IT979382B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
NL (1) NL7302663A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147141A (en) * 1975-06-13 1976-12-17 Hitachi Ltd Micro program controller
JPS5616244A (en) * 1979-07-19 1981-02-17 Fujitsu Ltd Microprogram loading system
JPS58214946A (ja) * 1982-06-08 1983-12-14 Nec Corp マイクロプログラム制御方式

Families Citing this family (60)

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FR2226901A5 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1973-04-19 1974-11-15 Honeywell Bull Soc Ind
IT995721B (it) * 1973-10-10 1975-11-20 Honeywell Inf Systems Italia Apparato per l interpretazione di codici di funzione in calcolatori microprogrammati e per l indirizza mento indipendente di fasi inter pretative ed esecutive di micro programma
FR2249596A5 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1973-10-24 1975-05-23 Honeywell Bull Soc Ind
US3934227A (en) * 1973-12-05 1976-01-20 Digital Computer Controls, Inc. Memory correction system
GB1464570A (en) * 1974-11-27 1977-02-16 Ibm Microprogramme control units
AU3329178A (en) * 1977-03-28 1979-08-23 Data General Corp A micro-control storage system
FR2461301A1 (fr) * 1978-04-25 1981-01-30 Cii Honeywell Bull Microprocesseur autoprogrammable
US4266272A (en) * 1978-10-12 1981-05-05 International Business Machines Corporation Transient microcode block check word generation control circuitry
US4346436A (en) * 1979-03-23 1982-08-24 Burroughs Corporation Interpretive digital data processor comprised of a multi-level hierarchy of processors and having program protection means
DE3138971A1 (de) * 1981-09-30 1983-04-21 Siemens AG, 1000 Berlin und 8000 München Mikroprogrammiertr prozessor und verfahren zu seinembetrieb
US4488219A (en) * 1982-03-18 1984-12-11 International Business Machines Corporation Extended control word decoding
US4862351A (en) * 1983-09-01 1989-08-29 Unisys Corporation Method of executing called activities via depictor-linked low level language microcode, hardware logic, and high level language commands; and apparatus for same
US5481743A (en) * 1993-09-30 1996-01-02 Apple Computer, Inc. Minimal instruction set computer architecture and multiple instruction issue method
US5790874A (en) * 1994-09-30 1998-08-04 Kabushiki Kaisha Toshiba Information processing apparatus for reducing power consumption by minimizing hamming distance between consecutive instruction
US5732255A (en) * 1996-04-29 1998-03-24 Atmel Corporation Signal processing system with ROM storing instructions encoded for reducing power consumpton during reads and method for encoding such instructions
US6081888A (en) * 1997-08-21 2000-06-27 Advanced Micro Devices Inc. Adaptive microprocessor with dynamically reconfigurable microcode responsive to external signals to initiate microcode reloading
US6606704B1 (en) * 1999-08-31 2003-08-12 Intel Corporation Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode
US6668317B1 (en) * 1999-08-31 2003-12-23 Intel Corporation Microengine for parallel processor architecture
US6983350B1 (en) 1999-08-31 2006-01-03 Intel Corporation SDRAM controller for parallel processor architecture
US6427196B1 (en) * 1999-08-31 2002-07-30 Intel Corporation SRAM controller for parallel processor architecture including address and command queue and arbiter
EP1236088B9 (en) 1999-09-01 2008-10-08 Intel Corporation Register set used in multithreaded parallel processor architecture
WO2001016702A1 (en) 1999-09-01 2001-03-08 Intel Corporation Register set used in multithreaded parallel processor architecture
US7191309B1 (en) 1999-09-01 2007-03-13 Intel Corporation Double shift instruction for micro engine used in multithreaded parallel processor architecture
US6532509B1 (en) 1999-12-22 2003-03-11 Intel Corporation Arbitrating command requests in a parallel multi-threaded processing system
US6694380B1 (en) 1999-12-27 2004-02-17 Intel Corporation Mapping requests from a processing unit that uses memory-mapped input-output space
US6307789B1 (en) * 1999-12-28 2001-10-23 Intel Corporation Scratchpad memory
US7620702B1 (en) 1999-12-28 2009-11-17 Intel Corporation Providing real-time control data for a network processor
US6631430B1 (en) * 1999-12-28 2003-10-07 Intel Corporation Optimizations to receive packet status from fifo bus
US6625654B1 (en) * 1999-12-28 2003-09-23 Intel Corporation Thread signaling in multi-threaded network processor
US6661794B1 (en) * 1999-12-29 2003-12-09 Intel Corporation Method and apparatus for gigabit packet assignment for multithreaded packet processing
US6584522B1 (en) * 1999-12-30 2003-06-24 Intel Corporation Communication between processors
US7480706B1 (en) 1999-12-30 2009-01-20 Intel Corporation Multi-threaded round-robin receive for fast network port
US6952824B1 (en) 1999-12-30 2005-10-04 Intel Corporation Multi-threaded sequenced receive for fast network port stream of packets
US6976095B1 (en) 1999-12-30 2005-12-13 Intel Corporation Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch
US6631462B1 (en) * 2000-01-05 2003-10-07 Intel Corporation Memory shared between processing threads
US7681018B2 (en) * 2000-08-31 2010-03-16 Intel Corporation Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
US20020053017A1 (en) * 2000-09-01 2002-05-02 Adiletta Matthew J. Register instructions for a multithreaded processor
US7020871B2 (en) * 2000-12-21 2006-03-28 Intel Corporation Breakpoint method for parallel hardware threads in multithreaded processor
US7216204B2 (en) * 2001-08-27 2007-05-08 Intel Corporation Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
US7225281B2 (en) 2001-08-27 2007-05-29 Intel Corporation Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms
US7487505B2 (en) 2001-08-27 2009-02-03 Intel Corporation Multithreaded microprocessor with register allocation based on number of active threads
US6868476B2 (en) * 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
US7126952B2 (en) * 2001-09-28 2006-10-24 Intel Corporation Multiprotocol decapsulation/encapsulation control structure and packet protocol conversion method
US7158964B2 (en) * 2001-12-12 2007-01-02 Intel Corporation Queue management
US7107413B2 (en) * 2001-12-17 2006-09-12 Intel Corporation Write queue descriptor count instruction for high speed queuing
US7269179B2 (en) * 2001-12-18 2007-09-11 Intel Corporation Control mechanisms for enqueue and dequeue operations in a pipelined network processor
US7895239B2 (en) * 2002-01-04 2011-02-22 Intel Corporation Queue arrays in network devices
US7181573B2 (en) * 2002-01-07 2007-02-20 Intel Corporation Queue array caching in network devices
US6934951B2 (en) 2002-01-17 2005-08-23 Intel Corporation Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section
US7610451B2 (en) 2002-01-25 2009-10-27 Intel Corporation Data transfer mechanism using unidirectional pull bus and push bus
US7181594B2 (en) * 2002-01-25 2007-02-20 Intel Corporation Context pipelines
US7149226B2 (en) * 2002-02-01 2006-12-12 Intel Corporation Processing data packets
US7437724B2 (en) * 2002-04-03 2008-10-14 Intel Corporation Registers for data transfers
US7471688B2 (en) * 2002-06-18 2008-12-30 Intel Corporation Scheduling system for transmission of cells to ATM virtual circuits and DSL ports
US7337275B2 (en) 2002-08-13 2008-02-26 Intel Corporation Free list and ring data structure management
US7352769B2 (en) 2002-09-12 2008-04-01 Intel Corporation Multiple calendar schedule reservation structure and method
US7433307B2 (en) * 2002-11-05 2008-10-07 Intel Corporation Flow control in a network environment
US6941438B2 (en) * 2003-01-10 2005-09-06 Intel Corporation Memory interleaving
US7443836B2 (en) 2003-06-16 2008-10-28 Intel Corporation Processing a data packet
US7213099B2 (en) * 2003-12-30 2007-05-01 Intel Corporation Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matches

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3325788A (en) * 1964-12-21 1967-06-13 Ibm Extrinsically variable microprogram controls
US3391394A (en) * 1965-10-22 1968-07-02 Ibm Microprogram control for a data processing system
US3478322A (en) * 1967-05-23 1969-11-11 Ibm Data processor employing electronically changeable control storage
GB1246130A (en) * 1967-12-14 1971-09-15 Olivetti & Co Spa Stored programme electronic computer
US3569938A (en) * 1967-12-20 1971-03-09 Ibm Storage manager
BE757967A (fr) * 1969-10-25 1971-04-23 Philips Nv Memoire pour microprogramme
US3696340A (en) * 1970-11-09 1972-10-03 Tokyo Shibaura Electric Co Microprogram execution control for fault diagnosis

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147141A (en) * 1975-06-13 1976-12-17 Hitachi Ltd Micro program controller
JPS5616244A (en) * 1979-07-19 1981-02-17 Fujitsu Ltd Microprogram loading system
JPS58214946A (ja) * 1982-06-08 1983-12-14 Nec Corp マイクロプログラム制御方式

Also Published As

Publication number Publication date
JPS5734534B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1982-07-23
DE2306115A1 (de) 1973-09-13
BE795789A (fr) 1973-06-18
DE2306115C2 (de) 1983-01-20
GB1391412A (en) 1975-04-23
IT979382B (it) 1974-09-30
FR2175433A5 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1973-10-19
BR7301467D0 (pt) 1974-05-16
NL7302663A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1973-09-11
US3792441A (en) 1974-02-12

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