JPS4419352B1 - - Google Patents
Info
- Publication number
- JPS4419352B1 JPS4419352B1 JP3816966A JP3816966A JPS4419352B1 JP S4419352 B1 JPS4419352 B1 JP S4419352B1 JP 3816966 A JP3816966 A JP 3816966A JP 3816966 A JP3816966 A JP 3816966A JP S4419352 B1 JPS4419352 B1 JP S4419352B1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/084—Diode-transistor logic
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
- H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
- H03K5/15093—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages using devices arranged in a shift register
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Nonlinear Science (AREA)
- Electronic Switches (AREA)
- Manipulation Of Pulses (AREA)
- Dot-Matrix Printers And Others (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US47892965A | 1965-08-11 | 1965-08-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS4419352B1 true JPS4419352B1 (enExample) | 1969-08-21 |
Family
ID=23901964
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3816966A Pending JPS4419352B1 (enExample) | 1965-08-11 | 1966-06-14 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US3422359A (enExample) |
| JP (1) | JPS4419352B1 (enExample) |
| DE (1) | DE1296180B (enExample) |
| FR (1) | FR1485061A (enExample) |
| GB (1) | GB1150304A (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3969632A (en) * | 1971-07-06 | 1976-07-13 | Thomson-Csf | Logic circuits-employing junction-type field-effect transistors |
| US3921079A (en) * | 1974-05-13 | 1975-11-18 | Gte Automatic Electric Lab Inc | Multi-phase clock distribution system |
| US4119916A (en) * | 1977-05-19 | 1978-10-10 | The United States Of America As Represented By The Secretary Of The Navy | Programmable charge coupled device timing system |
| GB9003535D0 (en) * | 1990-02-16 | 1990-04-11 | Hitachi Europ Ltd | Logic circuit device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3048716A (en) * | 1960-08-31 | 1962-08-07 | Bell Telephone Labor Inc | Logic system including high fan-out stage having variable clamping means |
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1965
- 1965-08-11 US US478929A patent/US3422359A/en not_active Expired - Lifetime
-
1966
- 1966-06-14 JP JP3816966A patent/JPS4419352B1/ja active Pending
- 1966-06-21 FR FR47452A patent/FR1485061A/fr not_active Expired
- 1966-08-05 DE DEA53181A patent/DE1296180B/de active Pending
- 1966-08-11 GB GB36069/66A patent/GB1150304A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| GB1150304A (en) | 1969-04-30 |
| FR1485061A (fr) | 1967-06-16 |
| US3422359A (en) | 1969-01-14 |
| DE1296180B (de) | 1969-05-29 |