JPH1198470A - Pre-stage filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To process an interlaced video signal in a way that a motion is more accurately detected. SOLUTION: An interlaced video signal thinned by a flip-flop 12 is given to a vertical LPF 14 acting like an inter-line interpolation means. In the vertical LPF 14, a coefficient of 0.75 is multiplied with the interlaced video signal and a coefficient of 0.25 is multiplied with the interlaced video signal delayed by one H at an odd number field, a coefficient of 0.25 is multiplied with the interlaced video signal and a coefficient of 0.75 is multiplied with the interlaced video signal delayed by one H at an even number field, and the results are summed to obtain an interpolation video signal. A noise component in the vertical direction is eliminated from the interpolation video signal at a vertical LPF 16 and an offset component in the horizontal direction is eliminated from the interpolation video signal at a horizontal LPF 18 and a noise component in the horizontal direction is eliminated by a horizontal LPF 20. Or a vertical LPF to eliminate an offset component in the vertical direction may be added. Based on the interpolation video signal processed in this way, a motion detection circuit 78 detects a motion.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pre-filter, and more particularly, to a pre-filter arranged, for example, before a motion detection circuit.

[0002]

2. Description of the Related Art Conventionally, when motion detection is performed on a still image of interlaced video, it is often detected that there is a motion of one line in the vertical direction between fields.

[0003]

As described above, since it is detected that there is movement in spite of being originally stationary,
It has been difficult to distinguish a completely still image from an image that actually moves.

It is therefore a primary object of the present invention to provide a pre-filter for processing interlaced video signals so that motion can be more accurately detected.

[0005]

In order to achieve the above object, a prefilter according to claim 1 is a prefilter for processing an interlaced video signal, wherein the prefilter filters an interlaced video signal between lines in a field. An inter-line interpolation unit for interpolating and obtaining an interpolated video signal is provided.

According to a second aspect of the present invention, there is provided the pre-filter according to the first aspect, wherein the inter-line interpolation means converts the first interlaced video signal into an interlaced video signal in an odd field.
First multiplication means for multiplying the coefficient K1 (0 ≦ K1 ≦ 1) by the second coefficient (1−K1) in the even field with the interlaced video signal, and the interlaced video signal by 1
A first delay unit that delays by a line, a second coefficient (1−K1) is added to the interlaced video signal delayed by the first delay unit in the odd field, and a second coefficient (1−K1) is added to the interlaced video signal delayed by the first delay unit in the even field. A second multiplication means for multiplying each coefficient by K1 and a first addition means for adding the first video signal from the first multiplication means and the second video signal from the second multiplication means to obtain an interpolated video signal. Including.

A prefilter according to a third aspect of the present invention is a prefilter for processing an interlaced video signal, the interpolating means for interpolating an interlaced video between lines in a field to obtain an interpolated video signal, and an interpolated video. A first filter that removes a vertical noise component of the signal; a second filter that removes a horizontal offset component of the interpolated video signal; and a third filter that removes a horizontal noise component of the interpolated video signal.

According to a fourth aspect of the present invention, in the pre-filter of the third aspect, the inter-line interpolating means converts the first interlaced video signal into an interlaced video signal in an odd field.
First multiplication means for multiplying the coefficient K1 (0 ≦ K1 ≦ 1) by the second coefficient (1−K1) in the even field with the interlaced video signal, and the interlaced video signal by 1
A first delay unit that delays by a line, a second coefficient (1−K1) is added to the interlaced video signal delayed by the first delay unit in the odd field, and a second coefficient (1−K1) is added to the interlaced video signal delayed by the first delay unit in the even field. A second multiplying means for multiplying each coefficient K1 by one coefficient, and a first multiplying means for adding the first video signal from the first multiplying means and the second video signal from the second multiplying means to obtain an interpolated video signal.
It includes addition means.

The prefilter according to claim 5 is the prefilter according to claim 3 or 4, wherein the first filter is a third multiplying means for multiplying the interpolated video signal by a third coefficient Kv, A second delay means for delaying the output of the filter by one line, and a fourth coefficient (1-K)
v), and second addition means for adding the output of the third multiplication means and the output of the fourth multiplication means to obtain an interpolated video signal from which noise components in the vertical direction have been removed. It is a thing.

A prefilter according to claim 6 is the prefilter according to claim 5, wherein the third coefficient Kv and the fourth coefficient (1-Kv) are variable.

The pre-filter according to claim 7 is the pre-filter according to claims 3 to 6, wherein the second filter is a third delay means for delaying the interpolated video signal, and the third filter is configured to output the third filter from the interpolated video signal. It includes a subtraction means for subtracting the output of the delay means to obtain an interpolated video signal from which a horizontal offset component has been removed.

The prefilter according to claim 8 is the prefilter according to claim 7, wherein the third delay means is connected in multiple stages, and a flip-flop for delaying the interpolated video signal by one clock, and a multistage. It includes first selection means for selecting an output from the connected flip-flop.

The prefilter according to claim 9 is the prefilter according to any one of claims 3 to 8,
A third filter configured to multiply the interpolated video signal by a fifth coefficient Kh; a fourth delay unit configured to delay the output of the third filter by one clock; and a fifth coefficient (1- Kh), and an output of the fifth multiplier and an output of the sixth multiplier are added to obtain an interpolated video signal from which a horizontal noise component has been removed.
It includes addition means.

A prefilter according to a tenth aspect is the prefilter according to the ninth aspect, wherein the fifth coefficient Kh and the sixth coefficient (1-Kh) are variable.

The prefilter according to claim 11 is the prefilter according to any one of claims 3 to 10, further comprising a fourth filter for removing a vertical offset component of the interpolated video signal.

The prefilter according to claim 12 is the prefilter according to claim 11, wherein the fourth filter is a fifth delay means for delaying the interpolated video signal, and a fifth delay means from the interpolated video signal. Is subtracted to obtain an interpolated video signal from which the vertical offset component has been removed.

The prefilter according to claim 13 is the prefilter according to claim 12, wherein the fifth delay means is connected in multiple stages and delays the interpolated video signal by one line. And second selecting means for selecting an output from the sixth delay means connected in multiple stages.

In the prefilter according to the first aspect, the interlaced video signal is interpolated between lines in the field by the interline interpolation means to obtain an interpolated video signal.

At this time, in the pre-filter according to the second aspect, the first multiplication means multiplies the interlaced video signal by the first coefficient K1 in the odd field, and multiplies the interlaced video signal by the second coefficient in the even field.
The coefficient is multiplied by (1−K1). Further, the interlaced video signal is delayed by one line by the first delay means,
In the odd field, the second multiplication means adds the second coefficient (1-K) to the interlace signal delayed by the first delay means.
1), and in an even field, the interlaced signal delayed by the first delay means is multiplied by a first coefficient K1. Then, the first video image signal from the first multiplication unit and the second video signal from the second multiplication are added by the first addition unit to obtain an interpolated video signal.

In the pre-filter according to the third aspect, first, the interlaced video signal is inter-line-interpolated in the field by the inter-line interpolation means to obtain an interpolated video signal.

The first filter removes a vertical noise component of the interpolated video signal, the second filter removes a horizontal offset component of the interpolated video signal, and the third filter removes a horizontal offset component of the interpolated video signal. Noise components are removed.

Here, the interpolated video signal may be generated as follows.

According to a fourth aspect of the present invention, first, an interlaced video signal is multiplied by a first coefficient K1 in an odd field, and a second coefficient (1-K1) is multiplied by an interlaced video signal in an even field. Is multiplied. Further, the interlaced video signal is delayed by one line by the first delay means, and
In the odd field, the interlace signal delayed by the first delay means is multiplied by the second coefficient (1-K1), and in the even field, the interlace signal delayed by the first delay means is multiplied by the first coefficient K1. Then, the first video signal from the first multiplication means and the second video signal
The second video signal from the multiplication is added to obtain an interpolated video signal.

The vertical noise component of the interpolated video signal may be removed as follows.

According to a fifth aspect of the present invention, the interpolated video signal is multiplied by a third coefficient Kv by a third multiplying means.
The output of the first filter is delayed by one line by the delay means, and the output from the second delay means is multiplied by a fourth coefficient (1-Kv) by the fourth multiplication means. Then, the output of the third multiplication means and the output of the fourth multiplication means are added by the second addition means, and as a result, an interpolated video signal from which the noise component in the vertical direction has been removed is obtained.

The third coefficient Kv and the fourth coefficient (1-Kv) may be variable. Therefore, when the interpolated video signal from the pre-filter is supplied to the motion detection circuit, and the motion detection circuit detects a motion in each detection area, the third coefficient Kv and the third coefficient Kv are determined according to the size of the detection area. Four coefficients (1-Kv) are set.

The horizontal offset component of the interpolated video signal may be removed as follows.

According to a seventh aspect of the present invention, the interpolated video signal is delayed by the third delay means, and is subtracted by the subtraction means.
The output of the third delay means is subtracted from the interpolated video signal, and as a result, an interpolated video signal from which a horizontal offset component has been removed is obtained.

In this case, the interpolation video signal may be delayed by the flip-flops connected in multiple stages and the first selection means for selecting the output from the flip-flops. The amount of delay in the third delay means is set depending on which flip-flop selects the output from the first selection means. When the interpolated video signal from the pre-filter is supplied to the motion detection circuit, and the motion detection circuit detects a motion in each detection area, the amount of delay by the third delay means depends on the size of the detection area. Is set.

The horizontal noise component of the interpolated video signal may be removed as follows.

According to a ninth aspect, the fifth multiplication means multiplies the interpolated video signal by the fifth coefficient Kh.
The output of the third filter is delayed by one clock by the delay means, and the output from the fourth delay means is multiplied by a sixth coefficient (1-Kh) by the sixth multiplication means. Then, the output of the fifth multiplication means and the output of the sixth multiplication means are added by the third addition means to obtain an interpolated video signal from which the noise component in the horizontal direction has been removed.

As described in claim 10, the fifth coefficient K
h and the sixth coefficient (1-Kh) may be variable.
Therefore, when the interpolated video signal from the pre-filter is supplied to the motion detection circuit, and the motion detection circuit detects a motion in each detection area, the fifth coefficient Kh and the fifth coefficient Kh are determined according to the size of the detection area. Six coefficients (1-Kh) are set.

Further, as set forth in claim 11, the fourth filter may remove a vertical offset component of the interpolated video signal.

The vertical offset component of the interpolated video signal may be removed as follows.

According to a twelfth aspect, the interpolated video signal is delayed by the fifth delay means, and the output of the fifth delay means is subtracted from the interpolated video signal by the subtraction means.
An interpolated video signal from which the vertical offset component has been removed is obtained.

At this time, as described in claim 13,
The interpolated video signal may be delayed by the sixth delay unit connected in multiple stages and the second selection unit that selects the output from the sixth delay unit. The amount of delay in the fifth delay means is set according to which output from the sixth delay means is selected by the second selection means. When the interpolated video signal from the pre-filter is supplied to the motion detection circuit, and the motion detection circuit detects motion in each detection area, the amount of delay by the fifth delay means depends on the size of the detection area. Is set.

[0037]

Embodiments of the present invention will be described below with reference to the drawings.

Referring to FIG. 1, a prefilter 10 according to an embodiment of the present invention includes a luminance signal component of an interlaced video signal (hereinafter, simply referred to as "interlaced video signal").
12, a vertical LPF 14 for interpolating a given interlaced image between lines in a field to obtain an interpolated video signal, removing a vertical noise component of the interpolated video signal, and sharply interpolating the interpolated video signal. A vertical LPF 16 for preventing a change, a horizontal HPF 18 for removing a horizontal offset component of the interpolated video signal, and a horizontal LPF 20 for removing a horizontal noise component of the interpolated video signal and preventing a sudden change of the interpolated video signal. .

The flip-flop 12 has, for example, NT
An interlaced video signal of various video sources such as an SC TV receiver is provided, and the interlaced video signal is thinned out according to the video source.

In the flip-flop 12, １ ／ or の 間 thinning is performed so that the number of pixels can be increased according to the video source. For example, in the case of an NTSC TV receiver, the flip-flop 12
/ 2 thinning is performed.

Therefore, it is possible to input an interlaced video signal required for normal motion detection without increasing the circuit scale of the motion detection circuit 78 (described later).

The vertical LPF 14 functions as an inter-line interpolating means for preventing interlace.
1H delay circuit 24, multiplication circuit 26 and addition circuit 28 are included.

In the multiplication circuit 22, the interlaced video signal is multiplied by the interpolation coefficient 0.75 in the odd field, and the interlaced video signal is multiplied by the interpolation coefficient 0.25 in the even field. In the 1H delay circuit 24,
The interlaced video signal is delayed by one line and applied to the multiplication circuit 26.

The multiplication circuit 26 multiplies the given interlaced video signal delayed by one line in the odd field by the interpolation coefficient 0.25, and multiplies the given interlaced video signal delayed by one line in the even field. The interpolation coefficient is multiplied by 0.75. in this way,
The interpolation coefficients multiplied by the multiplication circuits 26 and 28 are switched for each field.

In the adding circuit 28, the output from the multiplying circuit 22 and the output from the multiplying circuit 26 are added to obtain an interpolated video signal.

As described above, the interpolation coefficients multiplied by the multiplication circuits 22 and 26 are fixed at 0.25 and 0.75, so that the frequency characteristics of the vertical LPF 14 are fixed.

The vertical LPF 14 is specifically configured, for example, as shown in FIG.

The vertical LPF 14 has a flip-flop 30
And 32. The interlaced video signal of the odd field is applied to the flip-flop 30,
The signal is applied to flip-flop 32 via 1H delay circuit 24. The interlaced video signal of the even field is supplied to the flip-flop 32 and to the flip-flop 30 via the 1H delay circuit 24. Then, the interlaced video signal from the flip-flop 30 is provided to the adding circuit 34 and the doubling circuit 36.

In the doubling circuit 36, more specifically, the interlaced video signal can be doubled by shifting the given interlaced video signal by one bit. 2
The doubled interlaced video signal is supplied to an adding circuit 34, and is added to the interlaced video signal from the flip-flop 30. The tripled interlaced video signal is output from the adding circuit 34 and supplied to the adding circuit 38. Can be The adding circuit 38 adds the interlaced video signal from the adding circuit 34 and the interlaced video signal from the flip-flop 32 and supplies the result to the quarter circuit 40.

Specifically, in the 1/4 circuit 40, the given interlaced video signal can be multiplied by 1/4 by shifting the given interlaced video signal to the lower order by 2 bits.

Therefore, in the odd-numbered field, the tripled interlaced video signal from the adder circuit 34 and the 1H-delayed interlaced video signal from the flip-flop 32 are added and then multiplied by 1/4. , An interpolated video signal is obtained. On the other hand, in the even-numbered field, after the interlaced video signal from the flip-flop 32 and the interlaced video signal delayed by 1H and tripled from the adding circuit 34 are added together,
By multiplying, an interpolated video signal is obtained.

These interpolated video signals are output to the vertical LPF 16 via the selection circuit 42.

Further, FIGS. 3 (a), (e) and (f)
The operation of the vertical LPF 14 will be described more specifically with reference to FIG.

FIG. 3A shows an example of the luminance of a pixel in an odd field and an even field. The luminance value is shown in the white circle “○”.

First, in the odd field, the interpolated video signals shown in FIGS. 3A to 3E are obtained. For example, in the odd field shown in FIG. 3A, a pixel having a luminance value of “74” on the second line and a luminance value of “70” on the first line.
The pixel having the luminance value of “73” on the first line in FIG.

On the other hand, in the even-numbered fields, the interpolated video signals shown in FIGS. 3A to 3F are obtained. For example, in the even-numbered field of FIG. 3A, the pixel whose luminance value on the second line is “76” and the luminance value on the first line is “72”
The pixel having the luminance value of “73” on the first line in FIG.

As described above, the luminance value on the same line is generated by the calculation in a pseudo manner.

The luminance signal component of the video signal is directly supplied to one input terminal of the selection circuit 42.
It is a path for non-interlaced video signals such as personal computers. By the way, in the case of the VGA system or the XGA system among the displays of the personal computer, the flip-flop 12 performs the thinning of 1/2, and in the case of the HDTV or the SXGA system of the display of the personal computer, the thinning of the flip-flop 12 is performed. Decimation is performed.

Returning to FIG. 1, the interpolated video signal from the vertical LPF 14 is given to the vertical LPF 16.

The vertical LPF 16 includes a multiplication circuit 44, an addition circuit 46, a 1H delay circuit 48, and a multiplication circuit 50.

The multiplication circuit 44 multiplies the interpolated video signal by the coefficient Kv and supplies the multiplied signal to the addition circuit 46.
The output from the adder circuit 46 is delayed by one line by a 1H delay circuit 48, and the multiplier circuit 50 multiplies the output from the 1H delay circuit 48 by a coefficient (1−Kv) and supplies the result to the adder circuit 46. The addition circuit 46 outputs an interpolated video signal from which noise components in the vertical direction have been removed. Here, the coefficient Kv is changed to 1/4 or 1/8. Therefore, the vertical LPF 16 can make the frequency characteristics variable.

The interpolated video signal from the vertical LPF 16 is given to the horizontal HPF 18.

The horizontal HPF 18 has a flip-flop 52
64, a selection circuit 66 and a subtraction circuit 68.

The flip-flops 52 to 64 are connected in multiple stages. In each of the flip-flops 52 to 64, the applied interpolation video signal is delayed by one clock and applied to the subsequent flip-flop. In the selection circuit 66, an output from the corresponding flip-flop is selected according to the set selection signal SEL1 and supplied to the subtraction circuit 68. In the subtraction circuit 68, the output from the selection circuit 66 is subtracted from the interpolation video signal from the vertical LPF 16 to obtain an interpolation video signal from which the horizontal offset component has been removed.

The selection signal SEL1 is set to any one of 3 to 8, and as a result, the horizontal HPF 18 can change the cutoff frequency, and can change the frequency characteristics.

The interlaced video signal from the horizontal HPF 18 is supplied to a horizontal LPF 20.

The horizontal LPF 20 includes a multiplication circuit 70, an addition circuit 72, a flip-flop 74, and a multiplication circuit 76.

The multiplying circuit 70 multiplies the given interpolated video signal by the coefficient Kh and supplies the multiplied signal to the adding circuit 72.
The output from the adder circuit 72 is delayed by one clock by the flip-flop 74 and applied to the multiplier circuit 76. In the multiplication circuit 76, the output from the flip-flop 74 is multiplied by a coefficient (1−Kh), and the result is provided to the addition circuit 72. Then, an interpolation video signal from which horizontal noise components have been removed is output from the addition circuit 72, and is supplied to the motion detection circuit 78.

The coefficient Kh is set to either 1/4 or 1/8. Therefore, the horizontal LPF 20 can make the frequency characteristics variable.

The motion detection circuit 78 performs motion detection based on the interpolated video signal processed as described above.

Next, referring to FIG.
A case where motion detection is performed without using 0 and a case where motion detection is performed using the pre-filter 10 will be described.

First, the detection operation of the motion detection circuit 78 when the pre-filter 10 is not used will be described with reference to FIGS.

A case where a motion vector is detected by a representative point matching method using a pixel whose luminance value is "88" shown in FIG. 3B as a representative point will be described. Here, pixels are searched from the upper line to the lower line, and at each time point, a pixel having the smallest luminance difference from the representative point, that is, a pixel having the smallest correlation value is stored as a candidate, and a pixel having a lower correlation value than the pixel is stored. When a pixel having a small value is detected, a candidate pixel is replaced each time, thereby adopting a first method of detecting a pixel having a minimum correlation value.

A representative point having a luminance value of “88” is shown in FIG.
Are compared with each pixel in the even-numbered field shown in FIG. 3, and a pixel having the closest luminance to the representative point is detected from FIG.
The number shown at the right shoulder of each pixel is the luminance difference from the representative point, that is, the correlation value.

In this case, the luminance value in FIG.
And “92” have the closest luminance to the pixel at the representative point.

In this case, a pixel having a luminance value of “84” is selected. As a result, the representative point shown in FIG.
It is determined that the luminance value shown in (c) has moved to the pixel of “84”. The representative point is located on the second line, and the luminance value is “8”.
Since the pixel “4” is located on the first line, it is detected that there is a movement of one line, assuming that it has moved to the previous line (Y = −1).

Note that, using the first method described above, FIG.
When the motion vector is detected by comparing the representative point with each pixel of the odd field shown in FIG. 3D using the pixel having the luminance value “92” shown in FIG.
It is determined that the representative point of “2” has moved to the pixel whose luminance value shown in FIG. In this case, the representative point,
Since the pixel having the luminance value “88” is located on the second line, there is no motion (Y = 0).

However, pixels are searched from the upper line to the lower line, and at each time point, the pixel having the smallest correlation value with the representative point is stored as a candidate, and the pixel and the correlation value are stored as candidates. When the same or a pixel having a smaller correlation value than that pixel is detected, the candidate pixel is replaced each time, thereby adopting the second method of detecting the pixel having the minimum correlation value, and calculating the motion vector. In the case of detection, it becomes as follows.

A case where a motion vector is detected using a pixel whose luminance value is "84" shown in FIG. 3C as a representative point will be described.

A representative point having a luminance value of "84" is shown in FIG.
Is compared with each pixel in the odd field shown in FIG. 3, and the pixel having the luminance closest to the representative point is detected from FIG.

In this case, the luminance value in FIG.
And “88” have the closest luminance to the pixel at the representative point.

In the second method, a pixel having a luminance value of “88” is selected. As a result, the representative point shown in FIG.
It is determined that the luminance value shown in (d) has moved to the pixel of “88”. The representative point is located on the first line, and the luminance value is “8”.
The pixel “8” is located on the second line.
Assuming that it has moved to the next line, it is detected that there is a movement for one line (Y = 1).

On the other hand, the pre-filter 1 of the present invention
A case where a motion vector is detected using 0 will be described with reference to FIGS.

As a result of inter-line interpolation in odd fields performed by the vertical LPF 14 of the pre-filter 10,
Interpolated video signals as shown in FIGS. 3E and 3G are obtained. Similarly, as a result of performing inter-line interpolation in an even field by the vertical LPF 14, an interpolated video signal as shown in FIG. 3F is obtained.

In this case, the luminance value shown in FIG.
The representative point of “4” is compared with each pixel shown in FIG. Then, as for the representative point, the luminance value shown in FIG.
It is determined that the pixel has moved to the pixel No. 4; however, since both the representative point and the pixel whose luminance value is “94” shown in FIG. 3F are located on the second line, there is no motion, that is, the pixel is stationary. Is determined (Y = 0).

The luminance value shown in FIG.
3G and each pixel shown in FIG. 3G, it is determined that the representative point has moved to the pixel whose luminance value shown in FIG. 3G is “94”. And FIG. 3 (g)
Are located on the second line, it is determined that there is no motion, that is, the pixel is stationary (Y = 0).

When the pre-filter 10 is used, it is determined that the apparatus is stationary irrespective of whether the first method or the second method is used.

By using the pre-filter 10 as described above, it is possible to eliminate the vertical error in the motion detection caused by the nature of the interlace signal, and it has been conventionally detected that there is one line motion in the vertical direction. Even in this case, it can be accurately determined that the vehicle is stationary. As a result, a more easily viewable image can be provided.

Referring to FIG. 4, pre-filter 10
In the case where is not used, as shown in FIG. 4A, a plurality of pixels having a similar correlation value with the representative point may be detected, but the frequency characteristic is improved by using the pre-filter 10. As a result, a frequency characteristic as shown in FIG. 4B is obtained, and a pixel having a minimum correlation value with the representative point can be easily detected.

Further, by making the coefficient Kv of the vertical LPF 16, the coefficient Kh of the horizontal LPF 20, and the selection signal SEL 1 of the horizontal HPF 18 variable,
0 can be made variable, and the subsequent motion detection circuit 78
, An optimal pre-filter 10 according to the size of the detection area can be configured.

Although the detection area of the motion detection circuit 78 is fixed in the prior art, the coefficient K of the vertical LPF 16 is fixed.
v, coefficient Kh of horizontal LPF 20, and horizontal HPF 18
Is variable, the motion detection circuit 78 can also set detection areas in accordance with various video sources, so that the versatility of the circuit can be improved and the cost can be reduced. You can also.

Referring to FIG. 5, a pre-filter 10a according to another embodiment of the present invention includes a vertical HPF 80 between a vertical LPF 16 and a horizontal HPF 18 of the pre-filter 10 shown in FIG. Since the other components are the same as those of the pre-filter 10, duplicate descriptions are omitted.

The vertical HPF 80 of the pre-filter 10a is
1H delay circuits 82 to 94, a selection circuit 96 and a subtraction circuit 98 are included.

In each of the 1H delay circuits 82 to 94, the vertical LP
The interpolated video signal from F16 is delayed by one line and supplied to the subsequent 1H delay circuit. Selection circuit 9
In 6, the output from the corresponding 1H delay circuit is selected according to the selection signal SEL2, and supplied to the subtraction circuit 98. In the subtraction circuit 98, the output of the selection circuit 96 is subtracted from the interpolation video signal from the vertical LPF 16 to obtain an interpolation video signal from which a vertical offset component has been removed, and is provided to the horizontal HPF 18.

The selection signal SEL2 is set to any one of 3 to 8, and as a result, the vertical HPF 80 can change the cutoff frequency, and can change the frequency characteristics. Therefore, like the coefficient Kv, the coefficient Kh, and the selection signal SEL1, by making the selection signal SEL2 variable, the pre-filter 10a according to the size of the detection area in the motion detection circuit 78 can be configured.

According to such a pre-filter 10a,
In addition to the effect of the pre-filter 10, an interpolated video signal from which a vertical offset component has been removed can be obtained.

In the above embodiment, the pre-filters 10 and 10a are arranged before the motion detecting circuit 78, but may be formed as a part of the motion detecting circuit.

A vertical LPF 16, a horizontal HPF 18,
The arrangement of the horizontal LPF 20 and the vertical HPF 80 is not limited to the above embodiment of the invention, and any arrangement is possible.

[0099]

According to the present invention, an interlaced video signal can be processed so that motion can be detected more accurately.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a vertical LPF 14.

FIG. 3 is an illustrative view showing a comparison between a case where motion detection is performed without using the present invention and a case where motion detection is performed using the present invention.

FIG. 4 is a graph for explaining characteristics of the present invention.

FIG. 5 is a circuit diagram showing another embodiment of the present invention.

[Explanation of symbols]

 10, 10a Pre-filter 12, 52-64 Flip-flop 14, 16 Vertical LPF 18 Horizontal HPF 20 Horizontal LPF 22, 26, 44, 50, 70, 76 Multiplier 24, 48, 74, 82-94 1H delay 28 , 46, 72 Addition circuit 66, 96 Selection circuit 68, 98 Subtraction circuit 78 Motion detection circuit 80 Vertical HPF

Claims (13)

[Claims] 1. A pre-filter for processing an interlaced video signal, comprising: an inter-line interpolation means for interpolating the interlaced video signal between lines in a field to obtain an interpolated video signal. 2. An inter-line interpolation unit according to claim 1, wherein said interlaced video signal has a first
First multiplying means for multiplying the coefficient K1 (0 ≦ K1 ≦ 1) by a second coefficient (1−K1) in the even field with the second coefficient (1−K1), respectively;
Delay means, in the odd field, a second coefficient (1-K1) is added to the interlaced video signal delayed by the first delay means;
In the even field, a second multiplying means for multiplying the interlaced video signal delayed by the first delay means by a first coefficient K1, respectively, and a first video signal from the first multiplying means and a signal from the second multiplying means. 2. The pre-filter according to claim 1, further comprising first adding means for obtaining an interpolation video signal by adding the second video signal. 3. A pre-filter for processing an interlaced video signal, comprising: an inter-line interpolation means for interpolating the interlaced video between lines in a field to obtain an interpolated video signal; and a vertical noise component of the interpolated video signal. A pre-filter comprising: a first filter for removing a horizontal offset component of the interpolated video signal; and a third filter for removing a horizontal noise component of the interpolated video signal. 4. An inter-line interpolating means includes a first interlaced video signal for an odd field.
First multiplying means for multiplying the coefficient K1 (0 ≦ K1 ≦ 1) by a second coefficient (1−K1) in the even field with the second coefficient (1−K1), respectively;
Delay means, in the odd field, a second coefficient (1-K1) is added to the interlaced video signal delayed by the first delay means;
In the even field, a second multiplying means for multiplying the interlaced video signal delayed by the first delay means by a first coefficient K1, respectively, and a first video signal from the first multiplying means and a signal from the second multiplying means. 4. The pre-filter according to claim 3, further comprising first adding means for obtaining an interpolation video signal by adding the second video signal. 5. The first filter includes: a third multiplying unit that multiplies the interpolated video signal by a third coefficient Kv; a second delay unit that delays an output of the first filter by one line; And a fourth multiplication means for multiplying the output of the third multiplication means by a fourth coefficient (1−Kv), and an output of the third multiplication means and an output of the fourth multiplication means are added to remove a vertical noise component. 5. The pre-filter according to claim 3, further comprising a second adding means for obtaining an interpolated video signal. 6. The prefilter according to claim 5, wherein the third coefficient Kv and the fourth coefficient (1−Kv) are variable. 7. The second filter, wherein a third delay means for delaying the interpolated video signal, and an output of the third delay means are subtracted from the interpolated video signal, so that a horizontal offset component is removed. 7. The pre-filter according to claim 3, further comprising subtraction means for obtaining an interpolated video signal. 8. The third delay unit includes a flip-flop that is connected in multiple stages and delays the interpolated video signal in units of one clock, and a first selection unit that selects an output from the flip-flop that is connected in multiple stages. A prefilter according to claim 7. 9. The third filter, a fifth multiplying unit that multiplies the interpolated video signal by a fifth coefficient Kh, a fourth delay unit that delays the output of the third filter by one clock, A sixth multiplication means for multiplying the output of the second multiplication means by a fifth coefficient (1−Kh), and adding an output of the fifth multiplication means and an output of the sixth multiplication means to remove a horizontal noise component. 9. The pre-filter according to claim 3, further comprising third adding means for obtaining an interpolated video signal. 10. The prefilter according to claim 9, wherein the fifth coefficient Kh and the sixth coefficient (1−Kh) are variable. 11. The pre-filter according to claim 3, further comprising a fourth filter for removing a vertical offset component of the interpolation video signal. 12. The fourth filter, wherein a fifth delay means for delaying the interpolated video signal, and an output of the fifth delay means being subtracted from the interpolated video signal, a vertical offset component has been removed. The pre-filter according to claim 11, further comprising a subtraction unit for obtaining an interpolated video signal. 13. The fifth delay means, wherein the fifth delay means is connected in multiple stages, the sixth delay means delaying the interpolated video signal in units of one line, and the sixth delay means connected in multiple stages.
13. The pre-filter of claim 12, further comprising a second selection means for selecting an output from the delay means.