JP3463640B2 - Digital noise reduction circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital noise reduction circuit, and more particularly to a digital noise reduction circuit for performing noise reduction on a television signal.

[0002]

2. Description of the Related Art Generally, as a noise reduction method for video signals, a frame recursive type for time-averaging two frame signals continuous in the time axis direction and a two-dimensional processing using a target pixel and its peripheral pixels There is an acyclic type within the field.

The recursive noise reduction has a problem in that after processing is performed in the time axis direction, there is an afterimage in the processed video signal and the dynamic resolution deteriorates. Therefore,
Recursive noise reduction is not suitable for moving video signals.

On the other hand, the non-recursive noise reduction has no deterioration in the dynamic resolution, but has a problem that the two-dimensional processing is performed, so that the planar resolution is deteriorated. The deterioration of resolution is because the pixel signals are averaged and reduced.

As one method for solving this problem,
There is a median filter. This filter is a filter that replaces the pixel corresponding to the median value of all the pixels including the pixel of interest and its peripheral pixels with the pixel of interest, and features that noise is reduced while maintaining the detail part. have.

A method often used to perform the above process is to rearrange all the extracted pixels by some sort method and replace the pixel corresponding to the median value with the pixel of interest. There are various sort methods, and there are a method in which the operation is stable but the processing delay time is long, and a method in which the processing delay time varies depending on conditions. When configuring a median filter in hardware, it is necessary for the processing time to be short and constant, but the circuit configuration using the sort described above performs each processing in series, so the processing delay time is inevitably large. Become.

As an example of such a noise removing technique, a "television signal noise removing circuit" described in Japanese Patent Laid-Open No. 5-167892 is known.

In this publication, in a TV signal noise elimination circuit using a median filter, image deterioration that occurs when removing impulsive noise in a TV signal is reduced by using a pixel order determination function and a correlation function. The technology to do this is described.

[0009]

In the case of the cyclic type, the above-mentioned conventional digital noise reduction circuit performs processing in the time axis direction, so that an afterimage exists in the processed video signal and the dynamic resolution deteriorates. It has the drawback of

In the non-recursive type, the dynamic resolution is not deteriorated at all, but the two-dimensional processing is performed, so that the planar resolution is deteriorated.

An object of the present invention is to provide a non-recursive digital noise reduction circuit that has a short processing time and little deterioration in resolution.

[0012]

SUMMARY OF THE INVENTION The digital noise of the present invention.
The shift reduction circuit receives a video input signal in which one screen of a digital image has a configuration of 3 pixels × 3 pixels, delays one pixel line of the video input signal, and outputs it as a first line delay output. A one-line delay element; the first
Second line delay element for inputting the line delay output of the above, delaying one pixel line for outputting as the second line delay output; and delaying the video input signal for one pixel and outputting as C data 1 A clock delay element C; a 1-clock delay element B that delays the C data by one pixel and outputs it as B data; and a 1-clock delay element A that delays the B data by 1 pixel and outputs it as A data; 1-clock delay element F for delaying the first line delay output by 1 pixel and outputting it as F data; 1-clock delay element E for delaying the F data by 1 pixel and outputting it as E data
A 1-clock delay element D that delays the E data by one pixel and outputs it as D data; and a 1-clock delay element I that delays the second line delay output by 1 pixel and outputs it as I data; The I data is delayed by one pixel, and H
1-clock delay element H for outputting as data; H
1-clock delay element G for delaying data by one pixel and outputting as G data; C data, B data, A data, F data, E data, D data, I data, H A digital noise reduction circuit comprising: a median filter for inputting data, the G data and outputting a video output signal; wherein the median filter comprises the extracted A data, B data, C data, One pixel is selected from the pixel signals of 9 pixels of the D data, the E data, the F data, the G data, the H data, and the I data, and the magnitude of the pixel signal and the pixel signal of the other 8 pixels are selected. The number of pixels having a pixel signal level higher than the pixel signal level of its own pixel (UP) and the number of pixels having a lower pixel signal level (DOWN) are compared. And nine comparator for outputting Re respectively; each of the nine comparator output and (UP) (DOW
N) which output the difference in the number of N); 9 absolute value conversion circuits which take the absolute value of the data output by said 9 subtractors; and these 9 absolute value conversion circuits output A pixel comparator that determines the signal having the smallest signal level from the pixel signals based on the absolute value calculation result, selects a pixel to replace the target pixel, and outputs a data selection signal; A pixel selector for replacing the pixel signal of the target pixel with the pixel signal output as the video output signal;

[0013]

[0014]

Each of the nine comparators contains eight comparators, and the A data, the B data, the C data, the D data, the E data, the F data, the G data, and the H data. Data, any one selected data of the I data is commonly input to one terminal of the eight comparators, and the other eight data other than the selected one data are input to the eight data. By sequentially inputting to the other terminal of the comparator, eight comparison results are counted, and the number of pixels having a pixel signal level higher than the pixel signal level of the own pixel (UP) and the number of pixels having a small pixel signal level (UP) And DOWN) are output respectively.

Further, it is characterized in that it is a video input signal obtained by expanding one screen of a digital image into a structure of m pixels × n pixels (m and n are integers of 1 or more).

Further, it is characterized by an apparatus for handling a television signal using a digital noise reduction circuit.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a digital noise reduction circuit of the present invention.

In the present embodiment shown in FIG. 1, a 1-line delay element 1 for inputting a video input signal 13, delaying one pixel line of the video input signal 13 and outputting it as a line delay output 15, and a line delay output 1 line delay element 2 which inputs 15 and delays one pixel line and outputs it as a line delay output 16; one clock delay element 3 which delays the video input signal 13 by one pixel and outputs it as C data 17; Data 17 is delayed by one pixel and output as B data 18 1
A clock delay element 4, a 1-clock delay element 5 that delays the B data 18 by one pixel and outputs it as A data 19,
The 1-clock delay element 6 which delays the line delay output 15 by one pixel and outputs it as the F data 20, and the F data 20
A 1-clock delay element 7 that delays by one pixel and outputs as E data 21 and a D-data 2 that delays E data 21 by one pixel
1 clock delay element 8 which outputs as 2; the 1 clock delay element 9 which delays the line delay output 16 by 1 pixel and outputs as I data 23; and 1 data which delays the I data 23 by 1 pixel and outputs as H data 24 1 Clock delay element 10
1 clock delay element 11 for delaying H data 24 by one pixel and outputting it as G data 25, C data 17, B
Data 18, A data 19, F data 20, E data 2
1, the D data 22, the I data 23, the H data 24, and the G data 25 are input, and the median filter 12 which outputs the video output signal 14 is comprised.

FIG. 2 is a diagram showing a pixel configuration example of one screen of a digital image.

In this case, one screen is arranged in 3 pixels × 3 pixels, and the pixels are constituted by 9 pixels of A, B, C, D, E, F, G, H, and I. In other words, it has a 9 pixel configuration with a 3 × 3 window.

Next, referring to FIGS. 1 and 2, the pixel in the middle is set as E as the pixel of interest, and the vertical direction of the pixel E,
It will be described as a configuration of a non-recursive noise reduction circuit for horizontal and diagonal peripheral pixels.

1-line delay elements 1 and 2 and 1-clock delay elements 3, 4, 5, 6, 7, 8, 9, 10, 1 for extracting the target pixel and its peripheral pixels from the video input signal 13.
Pixel signals from A data 19 to I data 23, which are composed of 1 and are extracted by the 1-line delay elements 1 and 2 and the 1-clock delay elements 3 to 11, are the median filters 1
Video output signal 1 after being input to 2 and filtered
It is output as 4. Here, the numbers of the 1-line delay elements 1 and 2 and the 1-clock delay elements 3 to 11 vary depending on the number of pixels included in the window targeted for noise reduction.

Now, the video input signal 13 is set to 0H (H: Ho
The data 1H of the line delay output 15 which is horizontally delayed by one line by the one line delay element 1 is created. 1H line delay output 1
5 is input to the 1-line delay element 2, and the data 2H of the line delay output 16 further delayed by 1 horizontal line is produced.

A data 19 which is a pixel signal of the 0H video input signal 13 via the 1-clock delay elements 3, 4, and 5
Is input to the median filter 12, B data 18 which is an output pixel signal of the 1-clock delay element 4, 1 C data 17 which is an output pixel signal of the 1-clock delay element 3,
D data 2 which is an output pixel signal of the 1-clock delay element 8
2, E data 21, which is the output pixel signal of the 1-clock delay element 7, and F, which is the output pixel signal of the 1-clock delay element 6.
The data 20, the G data 25 which is the output pixel signal of the 1-clock delay element 11, the H data 24 which is the output pixel signal of the 1-clock delay element 10, and the I-data 23 which is the output pixel signal of the 1-clock delay element 9, are respectively medians. It is input to the filter 12. The video input signal 13 of the A data 19 to I data 23 is represented by a two-dimensional arrangement as shown in FIG. At this time, the pixel signal of the target pixel is E
The data 21 and the others are pixel signals of peripheral pixels of the E data 21.

FIG. 3 is a detailed block diagram showing an example of the median filter of FIG.

In FIG. 3, the components corresponding to those shown in FIG. 1 are designated by the same reference numerals or symbols, and the description thereof will be omitted.

The median filter 12 extracts the extracted A
One pixel is selected from the pixel signals of 9 pixels from the data 19 to the I data 23, the magnitude of the pixel signal of that pixel signal is compared with that of the other 8 pixels, and the pixel signal level is higher than the pixel signal level of the own pixel. It has comparators 41 to 49 which respectively output the number of pixels (UP) and the number of pixels having a small pixel signal level (DOWN), and these comparators 41 to 49 are provided.
Of each of (UP) and (DOWN) output by each of the subtracters 51-59, and absolute value conversion circuits 61-69 for taking the absolute value of the data output by the subtractor, Determine the median of the signal levels in the input pixel signal,
A pixel to replace the pixel of interest is selected and a data selection signal 73
And a pixel selector 71 that replaces the selected pixel signal with the pixel signal of the pixel of interest and outputs it as the video output signal 14.

Incidentally, the comparators 41 to 49 and the subtractor 51
˜59, the number of absolute value conversion circuits 61 to 69 changes according to the number of pixels included in the window used for noise reduction.

Next, the operation will be described with reference to FIG.

A pixel signal A data 19 to I data 23 input to the median filter 12 is compared by a comparator 41.
Is input to all of ~ 49. That is, when any one data of A data 19 to I data 23 is input to one input terminal of each comparator, all the remaining input data except the one data is input to the other input terminal. Data is entered.

Here, the comparators 41-49 and the subtracters 51-51.
The operations of 59 and the absolute value conversion circuits 61 to 69 will be described.

For the A data 19 which is the pixel signal, the signal levels of the B data 18 to the I data 23 which are the pixel signals are compared, the number of signals larger than the A data 19 is calculated, and UP (A ) Is output. At the same time, the number of signals smaller than A data 19 is calculated, and DOWN
Output as (A). The subtracter 51 calculates the difference between UP (A) and DOWN (A), and outputs it to the absolute value conversion circuit 61. Since this result can take both positive and negative values, the absolute value calculation circuit 61 calculates the absolute value and POIN
It is output to the comparator 70 as T (A).

Each of the comparators 41 to 49 has eight comparators (comparators) built therein. For the comparator 41, for example, the A data 19 is provided at one terminal of the eight comparators. Is commonly input, and B is sequentially input to the other terminal.
Data 18, C data 17, D data 22, E data 2
1, F data 20, G data 25, H data 24, I data 23 are respectively input, eight comparison results with A data 19 are counted, and the above-mentioned UP (A) and DOWN (A) are output. To do. The same applies to other comparators.

Simultaneously with the above processing, the same processing is performed on the B data 18 to the I data 23 which are video signals, and the POINT (B) to POINT (I) are compared by the comparator 7.
It will be output to 0.

In the comparator 70, POINT (A) to POI
The pixel signal A that is the source from which the minimum value is selected from the NT (I) 9 data and the minimum value data is output.
Any one of the data 19 to I data 23 is selected and output as the data selection signal 73. For example, POINT
When (C) is determined to be the minimum value, C is used as the pixel signal.
A data selection signal 73 for selecting the data 17 is output to the pixel selector 71.

Here, if all the video signals of A data 19 to I data 23 have different values, the minimum value becomes 0, and the pixel signal from which the minimum POINT data is output is the own pixel signal. The same number of pixel signals larger than the pixel signal and the pixel signals smaller than the pixel signal exist. Therefore,
The pixel signal which is the source of the minimum POINT data is a signal having a median signal level among all the pixel signals.

In response to the data selection signal 73, the pixel selector 71 converts the data of the pixel signal selected from the A data 19 to I data 23 into the E data 2 which is the pixel signal of the target pixel.
1 and output as the video output signal 14. For example, when POINT (C) is determined to be the minimum value, C
The data 17 is replaced with the E data 21.

Next, the operation of the 1-line delay elements 1 and 2 and the 1-clock delay elements 3 to 11 will be described.

The video input signal 13 outputs digital data corresponding to one pixel every clock of a clock signal (not shown). Digital data of one pixel is composed of arbitrary bits. The median filter 12 needs to determine what window to filter. Here, a method of filtering a window with a 9-pixel window of 3 pixels × 3 pixels as shown in FIG. 2 will be described.

Consider the time when the pixel E becomes the signal of the pixel of interest. The pixel signal D on the left side of the pixel of interest E is a signal whose phase is advanced by one clock when viewed from the pixel of interest E,
In order to match the timing at which the signal of the target pixel E is input to the median filter 12, it is necessary to pass one clock delay element more than the signal of the target pixel E. Therefore, it is output from the 1-clock delay element 8.

Further, since the pixel signal F on the right side of the target pixel E is a signal whose phase is delayed by one clock as viewed from the target pixel E, it is necessary to reduce one clock delay element by one. Therefore, it is output from the 1-clock delay element 6.

Next, consider the pixel signal on the upper side and the pixel signal on the lower side of the target pixel E. The pixel signals G, H, and I on the upper side with respect to the pixel of interest E are one scanning line of the television signal above, that is, one pixel line (G,
Since the (H, I) phase is advanced, one line delay element is added more in order to match the timing when the signal of the target pixel E is input to the median filter 12. Therefore, it is output from the 1-line delay element 2. Similarly, the lower pixel signals A, B, and C have 1 line delay elements set to 1
It is necessary to reduce the number, and the video input signal 13 is output to the through.

That is, the 1-clock delay elements 3 to 11 are set to 1
With respect to the pixel shift, the one-line delay elements 1 and 2 shift all the pixels for one line.

Therefore, the number of 1-clock delay elements changes depending on the positional relationship (phase relationship) with the pixel of interest. For example,
The signal of the pixel H immediately above the target pixel E in a two-dimensional manner passes through the same number of 1-clock delay elements as the target pixel E. The signal of the pixel G corresponding to the upper left passes one more clock delay element.

As described above, the number of 1-line delay elements and 1-clock delay elements is changed according to the positional relationship (phase relationship) with the pixel of interest, and the input timing of all pixel signals is made uniform at the input of the median filter 12. The window of the median filter 12 is configured.

Although the acyclic noise reduction circuit using 9 pixels included in the 3 × 3 window has been described, this window is expanded to m × n (m and n are arbitrary integers of 1 or more). be able to.

Further, even in the same 3 × 3 window, an arbitrary number of pixels can be extracted and implemented from the remaining 8 pixels excluding the pixel of interest among the 9 pixel constituent pixels. For example, it is also possible to treat four pixels above, below, left and right of the pixel of interest as peripheral pixels, and implement a total of five pixels. Of course, even in this case,
It can be extended to × n.

As described above, the intra-field non-recursive structure effective for removing noise from a moving video signal is used.
Therefore, the median filter 12 is used to enable noise reduction while maintaining the detail portion. Inside the median filter 12, the comparators 41 to 49, the subtractors 51 to 59, and the absolute value conversion circuits 61 to 69 are arranged in parallel, and the processing delay time is shortened by performing processing in parallel in time. You can

The digital noise reduction circuit of the present invention uses a television receiver or a CCD in order to perform noise reduction of television signals such as NTSC and PAL.
It can be applied to a device handling a television signal such as a camera.

[0052]

As described above, the digital noise reduction circuit of the present invention uses a median filter, and when selecting the median value of the median filter, the median filter performs time series processing like sorting processing. Since the comparison processing of the pixels can be performed in parallel without performing the processing, there is an effect that a non-cyclic noise reduction circuit having a short processing time and effective for a hardware circuit configuration and having less resolution deterioration can be configured.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital noise reduction circuit of the present invention.

FIG. 2 is a diagram showing a pixel configuration example of one screen of a digital image.

FIG. 3 is a detailed block diagram showing an example of the median filter of FIG.

[Explanation of symbols]

1, 2 1 line delay element 3 to 11 1 clock delay element 12 Median filter 13 Video input signal 14 Video output signal 15 line delay output 16 line delay output 17 C data 18 B data 19 A data 20 F data 21 E data 22 D data 23 I data 24 H data 25 G data 41-49 Comparator 51-59 Subtractor 61-69 Absolute value conversion circuit 70 Comparator 71 Pixel selector 73 Data selection signal

Claims (4)

(57) [Claims] 1. A first input for inputting a video input signal in which one screen of a digital image has a structure of 3 pixels × 3 pixels, delaying one pixel line of this video input signal and outputting as a first line delay output. A one-line delay element; a second one-line delay element which receives the first line delay output, delays one pixel line and outputs the second line delay output; and the video input signal for one pixel 1-clock delay element C that delays and outputs as C data; 1-clock delay element B that delays the C data by 1 pixel and outputs as B data, and 1-clock delay element that delays the B data by 1 pixel, and as A data Output 1 clock delay element A
A 1-clock delay element F that delays the first line delay output by 1 pixel and outputs as F data; and a 1-clock delay element E that delays the F data by 1 pixel and outputs as E data; A 1-clock delay element D for delaying the E data by 1 pixel and outputting it as D data; a 1-clock delay element I for delaying the second line delay output by 1 pixel and outputting it as I data; 1-clock delay element H for delaying data by 1 pixel and outputting as H data; 1-clock delay element G for delaying H data by 1 pixel and outputting as G data; C data, B data, A median filter which inputs the A data, the F data, the E data, the D data, the I data, the H data, and the G data, and outputs a video output signal; A digital noise reduction circuit comprising: the median filter, wherein the median filter includes: the extracted A data, B data, C data, D data, E data, F data, G data, and H data. , The number of pixels having a pixel signal level higher than the pixel signal level of the own pixel by selecting one pixel from the pixel signals of the 9 pixels of the I data and comparing the magnitude of the pixel signal with that of the other 8 pixels (UP) and nine comparators that respectively output the number of pixels having a small pixel signal level (DOWN); and each of these nine comparators outputs (UP) and (DO
WN) nine subtractors that output the difference between the numbers; and nine absolute value conversion circuits that take the absolute value of the data output by the nine subtractors; and these nine absolute value conversion circuits output A pixel comparator that determines the signal having the smallest signal level from the pixel signals based on the absolute value calculation result, selects a pixel to replace the pixel of interest, and outputs a data selection signal; And a pixel selector which outputs the image output signal by replacing it with the pixel signal of the pixel of interest. 2. Each of the nine comparators has eight built-in comparators, the A data, the B data, the C data, the D data, the E data, the F data, the G data, Any one selected data of the H data and the I data is commonly input to one terminal of the eight comparators, and the other eight data excluding the selected one data are replaced by the eight data. The eight comparison results are counted by sequentially inputting to the other terminal of each comparator, and the number of pixels having a pixel signal level higher than the pixel signal level of the own pixel (U
P) and the number of pixels having a small pixel signal level (DOW
Claim 1 Symbol for and outputting N) and respectively
Built- in digital noise reduction circuit. 3. A screen of a digital image handled by the digital noise reduction circuit according to claim 1 or 2 , is configured by m pixels × n pixels (m and n are 1).
A digital noise reduction circuit which is a video input signal extended to the above integer). 4. An apparatus for handling a television signal, characterized in that the digital noise reduction circuit according to any one of claims 1 to 3 is used.