JP3515338B2 - Prefilter - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a prefilter, and more particularly to a prefilter arranged before a motion detection circuit.

[0002]

2. Description of the Related Art Conventionally, when motion detection is performed on a still image of an interlaced video, it is often detected that there is one line of motion in the vertical direction between fields.

[0003]

As described above, since it is detected that there is a movement even though it is originally stationary,
It was difficult to distinguish between a completely static image and an image that is actually moving.

Therefore, a main object of the present invention is to provide a prefilter which processes an interlaced video signal so that motion can be detected more accurately.

[0005]

In order to achieve the above object, a prefilter according to claim 1 is a prefilter for processing an interlaced video signal, wherein the interlaced video signal is lined in a field. Interline interpolating means for interpolating the interlaced video signal to obtain an interpolated video signal. The interline interpolating means adds a first coefficient K1 (K1 = 0.25 or 0.7) to the interlaced video signal in an odd field.
5), in an even field, a first multiplication means for respectively multiplying the interlaced video signal by a second coefficient (1−K1), a first delay means for delaying the interlaced video signal by one line, and in an odd field the first multiplication means. Second multiplication means for multiplying the interlaced video signal delayed by the first delay means by the second coefficient (1−K1) and the interlaced video signal delayed by the first delay means by the first coefficient K1 in the even field, respectively. , And a first video signal from the first multiplication means and a second video signal from the second multiplication means are added to obtain an interpolated video signal.
It is characterized by including addition means.

A prefilter according to a second aspect is the prefilter according to the first aspect, wherein the first filter removes a vertical noise component of the interpolated video signal from the interline interpolation means, A second filter for removing a horizontal offset component of the interpolated video signal and a third filter for removing a horizontal noise component of the interpolated video signal are provided.

A prefilter according to a third aspect is the prefilter according to the second aspect, wherein the first filter is a third multiplication means for multiplying the interpolated video signal by a third coefficient Kv. Second delay means for delaying the output of one filter by one line, fourth multiplying means for multiplying the output from the second delay means by a fourth coefficient (1−Kv), and the third
The present invention further includes second adding means for adding the output of the multiplying means and the output of the fourth multiplying means to obtain an interpolated video signal from which a vertical noise component has been removed.

A prefilter according to a fourth aspect is the prefilter according to the third aspect, wherein the third coefficient Kv and the fourth coefficient (1−Kv) are variable.

The prefilter according to claim 5 is the prefilter according to any one of claims 2 to 4, wherein:
The second filter subtracts an output of the third delay unit from the third delay unit that delays the interpolated video signal, and obtains an interpolated video signal from which a horizontal offset component is removed. Includes subtraction means.

A prefilter according to a sixth aspect is the prefilter according to the fifth aspect, wherein the third delay means is connected in multiple stages and a flip-flop that delays the interpolated video signal in units of one clock, And first selecting means for selecting an output from the flip-flops connected in multiple stages.

The prefilter according to claim 7 is the prefilter according to any one of claims 2 to 6, wherein
The third filter adds a fifth coefficient Kh to the interpolated video signal.
Fifth multiplication means for multiplying the output of the third filter by 1
A fourth delay means for delaying the clock, a sixth multiplier means for multiplying the output from the fourth delay means by a fifth coefficient (1-Kh), and an output of the fifth multiplier means and an output of the sixth multiplier means. Is added to obtain an interpolated video signal from which a horizontal noise component has been removed.

The prefilter according to claim 8 is the prefilter according to claim 7, wherein the fifth coefficient Kh and the sixth coefficient (1-Kh) are variable.

The prefilter according to claim 9 is the prefilter according to any one of claims 2 to 8.
A fourth filter for removing a vertical offset component of the interpolated video signal is further included.

A prefilter according to a tenth aspect is the prefilter according to the ninth aspect, wherein the fourth filter delays the interpolated video signal by fifth delay means, and the interpolated video signal includes the fifth delay means. It includes a subtraction unit for subtracting the output of the fifth delay unit to obtain an interpolated video signal from which the vertical offset component has been removed.

A prefilter according to an eleventh aspect is the prefilter according to the tenth aspect, wherein the fifth delay means is connected in multiple stages and the sixth delay means delays the interpolated video signal in units of one line. Means and second selecting means for selecting an output from the multistage connected sixth delay means.

In the prefilter according to the first aspect, the interlaced video signal is interpolated between the lines in the field by the interline interpolating means to obtain an interpolated video signal.

At this time, the first multiplication means multiplies the interlaced video signal by the first coefficient K1 in the odd field and the second coefficient (1-K1) by the interlaced video signal in the even field. Further, the first delay means delays the interlaced video signal by one line, and the second multiplying means delays the first signal in the odd field.
The interlaced signal delayed by the delay means is multiplied by the second coefficient (1-K1), and the interlaced signal delayed by the first delay means is multiplied by the first coefficient K1 in the even field. Then, the first addition means adds the first video image signal from the first multiplication means and the second video signal from the second multiplication to obtain an interpolated video signal.

In the prefilter according to the second aspect, first, the interlaced video signal is interpolated between the lines in the field by the interline interpolating means to obtain an interpolated video signal.

The first filter removes a vertical noise component of the interpolated video signal, the second filter removes a horizontal offset component of the interpolated video signal, and the third filter removes a horizontal noise component of the interpolated video signal. The noise component is removed.

The vertical noise component of the interpolated video signal may be removed as follows.

As described in claim 3, the third multiplication means multiplies the interpolated video signal by the third coefficient Kv, and the second
The output of the first filter is delayed by one line by the delay means, and the output from the second delay means is multiplied by the fourth coefficient (1-Kv) by the fourth multiplication means. Then, the output of the third multiplication means and the output of the fourth multiplication means are added by the second addition means, and as a result, an interpolated video signal from which the noise component in the vertical direction is removed is obtained.

As described in claim 4, the third coefficient Kv and the fourth coefficient (1−Kv) may be variable. Therefore, when the interpolated video signal from the pre-filter is applied to the motion detection circuit and the motion detection circuit detects motion in each detection region, the third coefficient Kv and the third coefficient Kv are determined according to the size of the detection region. 4 coefficients (1-Kv) are set.

The horizontal offset component of the interpolated video signal may be removed as follows.

As described in claim 5, the interpolated video signal is delayed by the third delay means, and the subtraction means
The output of the third delay means is subtracted from the interpolated video signal, and as a result, the interpolated video signal from which the horizontal offset component is removed is obtained.

At this time, as described in claim 6, the interpolated video signal may be delayed by the flip-flops connected in multiple stages and the first selecting means for selecting the output from the flip-flops. The delay amount in the third delay means is set depending on which flip-flop the output is selected by the first selection means. The interpolated video signal from the pre-filter is given to the motion detection circuit, and when the motion detection circuit detects motion in each detection area, the delay amount in the third delay means depends on the size of the detection area. Is set.

The horizontal noise component of the interpolated video signal may be removed as follows.

As described in claim 7, the fifth multiplication means multiplies the interpolated video signal by the fifth coefficient Kh to obtain a fourth coefficient.
The delay means delays the output of the third filter by one clock, and the sixth multiplying means multiplies the output from the fourth delay means by the sixth coefficient (1-Kh). Then, the output of the fifth multiplying means and the output of the sixth multiplying means are added by the third adding means to obtain an interpolated video signal from which the noise component in the horizontal direction is removed.

As described in claim 8, the fifth coefficient Kh
The sixth coefficient (1-Kh) may be variable. Therefore, when the interpolated video signal from the prefilter is applied to the motion detection circuit and the motion detection circuit detects motion in each detection region, the fifth coefficient Kh and the fifth coefficient Kh are calculated according to the size of the detection region. Six coefficients (1-Kh) are set.

Further, as described in claim 9, the fourth
A vertical offset component of the interpolated video signal may be removed by a filter.

The vertical offset component of the interpolated video signal may be removed as follows.

As described in claim 10, the fifth delay means delays the interpolated video signal, and the subtraction means subtracts the output of the fifth delay means from the interpolated video signal.
An interpolated video signal from which the vertical offset component has been removed is obtained.

At this time, as described in claim 11,
The interpolated video signal may be delayed by the sixth delay means connected in multiple stages and the second selection means for selecting the output from the sixth delay means. The delay amount in the fifth delay means is set depending on which output from the sixth delay means is selected by the second selection means. The interpolated video signal from the pre-filter is given to the motion detection circuit, and when the motion detection circuit detects motion in each detection region, the delay amount in the fifth delay means depends on the size of the detection region. Is set.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

Referring to FIG. 1, prefilter 10 according to the embodiment of the present invention has a luminance signal component of an interlaced video signal (hereinafter, simply referred to as "interlaced video signal").
Flip-flop 12 for thinning and outputting the interlaced video, vertical LPF 14 for interpolating a given interlaced video between lines in the field to obtain an interpolated video signal, removing a noise component in the vertical direction of the interpolated video signal, and It includes a vertical LPF 16 for preventing a change, a horizontal HPF 18 for removing a horizontal offset component of the interpolated video signal, and a horizontal LPF 20 for removing a horizontal noise component of the interpolated video signal to prevent a sudden change of the interpolated video signal. .

The flip-flop 12 has, for example, NT.
Interlaced video signals from various video sources such as SC TV receivers are given, and the interlaced video signals are thinned according to the video sources.

The flip-flop 12 decimates ½ or ¼ so that the number of pixels can be increased according to the video source. For example, in the case of a TV receiver of the NTSC system, the flip-flop 12 has 1
/ 2 is thinned out.

Therefore, it is possible to input the interlaced video signal necessary for normal motion detection without increasing the circuit scale of the motion detection circuit 78 (described later).

The vertical LPF 14 functions as an inter-line interpolating / interpolating means for the interlace countermeasure, and the multiplication circuit 22,
It includes a 1H delay circuit 24, a multiplication circuit 26 and an addition circuit 28.

In the multiplication circuit 22, the interlaced video signal is multiplied by the interpolation coefficient 0.75 in the odd field and the interlaced video signal is multiplied by the interpolation coefficient 0.25 in the even field. In the 1H delay circuit 24,
The interlaced video signal is delayed by one line and given to the multiplication circuit 26.

In the multiplication circuit 26, the interlaced video signal delayed by the given one line in the odd field is multiplied by the interpolation coefficient 0.25, and the interlaced video signal delayed by the given one line in the even field is multiplied. The interpolation coefficient 0.75 is multiplied. in this way,
The interpolation coefficient multiplied by the multiplication circuits 26 and 28 is switched for each field.

The adder circuit 28 adds the output from the multiplier circuit 22 and the output from the multiplier circuit 26 to obtain an interpolated video signal.

In this way, the interpolation coefficients multiplied by the multiplication circuits 22 and 26 are fixed to 0.25 and 0.75, so that the vertical LPF 14 has a fixed frequency characteristic.

The vertical LPF 14 is specifically constructed, for example, as shown in FIG.

The vertical LPF 14 has a flip-flop 30.
And 32 are included. The interlaced video signal of the odd field is given to the flip-flop 30 and
It is given to the flip-flop 32 via the 1H delay circuit 24. The interlaced video signal of the even field is applied to the flip-flop 32 and the flip-flop 30 via the 1H delay circuit 24. Then, the interlaced video signal from the flip-flop 30 is given to the adding circuit 34 and the doubling circuit 36.

In the doubling circuit 36, specifically, the interlaced video signal can be doubled by shifting the given interlaced video signal by 1 bit to the upper side. Two
The doubled interlaced video signal is given to the addition circuit 34 and added to the interlaced video signal from the flip-flop 30, and the tripled interlaced video signal is output from the addition circuit 34 and given to the addition circuit 38. To be In the adder circuit 38, the interlaced video signal from the adder circuit 34 and the interlaced video signal from the flip-flop 32 are added and given to the 1/4 circuit 40.

In the 1/4 circuit 40, specifically, the applied interlaced video signal can be multiplied by 1/4 by shifting the applied interlaced video signal by 2 bits to the lower order.

Therefore, in the odd field, the tripled interlaced video signal from the adder circuit 34 and the 1H delayed interlaced video signal from the flip-flop 32 are added and then multiplied by 1/4. , An interpolated video signal is obtained. On the other hand, in the even field, the interlaced video signal from the flip-flop 32 and the interlaced video signal delayed by 1H and tripled from the adding circuit 34 are added, and then ¼
By being multiplied, an interpolated video signal is obtained.

These interpolated video signals are output to the vertical LPF 16 via the selection circuit 42.

Further, FIGS. 3 (a), 3 (e) and 3 (f).
The operation of the vertical LPF 14 will be described more specifically with reference to FIG.

FIG. 3A shows an example of the luminance of pixels in the odd field and the even field. A brightness value is shown in a white circle “◯”.

First, in the odd field, the interpolated video signals shown in FIGS. 3A to 3E are obtained. For example, in the odd-numbered field of FIG. 3A, the pixel of which the luminance value on the second line is “74” and the luminance value of the first line are “70”.
The pixel of which the luminance value of the first line in FIG. 3E is “73”, that is, the interpolated video signal is generated from the pixel of FIG.

On the other hand, in the even field, the interpolated video signals of FIGS. 3 (a) to 3 (f) are obtained. For example, in the even field of FIG. 3A, the pixel whose luminance value on the second line is “76” and the luminance value on the first line are “72”.
By the above-described calculation processing, the pixel having the luminance value of “73” in the first line in FIG.

In this way, the brightness values on the same line are artificially generated in a pseudo manner.

The luminance signal component of the video signal is given to one input terminal of the selection circuit 42 as it is.
It serves as a path for non-interlaced video signals such as for personal computers. By the way, in the case of the VGA method or the XGA method of the display of the personal computer, 1/2 of the thinning is performed in the flip-flop 12, and in the HDTV or the SXGA method of the display of the personal computer, the flip-flop 12 is reduced to 1/4. Thinning is performed.

Returning to FIG. 1, the interpolated video signal from the vertical LPF 14 is given to the vertical LPF 16.

The vertical LPF 16 includes a multiplication circuit 44, an addition circuit 46, a 1H delay circuit 48 and a multiplication circuit 50.

The multiplying circuit 44 multiplies the supplied interpolated video signal by the coefficient Kv, and supplies it to the adding circuit 46.
The output from the adder circuit 46 is delayed by one line in the 1H delay circuit 48, and in the multiplier circuit 50, the output from the 1H delay circuit 48 is multiplied by a coefficient (1-Kv), and the result is given to the adder circuit 46. Then, the adder circuit 46 outputs the interpolated video signal from which the vertical noise component has been removed. Here, the coefficient Kv is variable to 1/4 or 1/8. Therefore, the vertical LPF 16 can change the frequency characteristic.

The interpolated video signal from the vertical LPF 16 is given to the horizontal HPF 18.

The horizontal HPF 18 has a flip-flop 52.
˜64, a selection circuit 66 and a subtraction circuit 68.

The flip-flops 52 to 64 are connected in multiple stages, and in each of the flip-flops 52 to 64, the given interpolated video signal is delayed by one clock and given to the subsequent flip-flops. In the selection circuit 66, the output from the corresponding flip-flop is selected and given to the subtraction circuit 68 according to the set selection signal SEL1. The subtraction circuit 68 subtracts the output from the selection circuit 66 from the interpolated video signal from the vertical LPF 16 to obtain an interpolated video signal from which the horizontal offset component has been removed.

The selection signal SEL1 is set to any of 3 to 8, and as a result, the horizontal HPF 18 can change the cutoff frequency and the frequency characteristic can be made variable.

The interlaced video signal from the horizontal HPF 18 is given to the horizontal LPF 20.

The horizontal LPF 20 includes a multiplication circuit 70, an addition circuit 72, a flip-flop 74 and a multiplication circuit 76.

In the multiplication circuit 70, the supplied interpolated video signal is multiplied by the coefficient Kh and supplied to the addition circuit 72.
The output from the adder circuit 72 is delayed by one clock by the flip-flop 74 and given to the multiplier circuit 76. In the multiplication circuit 76, the output from the flip-flop 74 is multiplied by the coefficient (1-Kh), and the result is given to the addition circuit 72. Then, the adder circuit 72 outputs the interpolated video signal from which the horizontal noise component has been removed, and supplies it to the motion detection circuit 78.

The coefficient Kh is set to either 1/4 or 1/8. Therefore, the horizontal LPF 20 can change the frequency characteristic.

The motion detection circuit 78 detects motion based on the interpolated video signal processed as described above.

Next, referring to FIG. 3, the prefilter 1
A case of performing motion detection without using 0 and a case of performing motion detection using the prefilter 10 will be described.

First, the detection operation of the motion detection circuit 78 when the prefilter 10 is not used will be described with reference to FIGS.

A case will be described below in which a motion vector is detected by the representative point matching method with the pixel having a luminance value of "88" shown in FIG. 3B as a representative point. Here, pixels are searched from the upper line toward the lower line, and at each time point, the pixel having the smallest luminance difference from the representative point, that is, the correlation value, is stored as a candidate, and the correlation is more than that pixel. When a pixel with a small value is detected, the candidate pixel is replaced each time to detect the pixel with the smallest correlation value.

A representative point having a luminance value of "88" and FIG.
3 is compared with each pixel in the even field, and the pixel having the closest brightness to the representative point is detected from FIG.
The number shown on the right side of each pixel is a luminance difference with the representative point, that is, a correlation value.

In this case, the brightness value of FIG. 3C is "84".
And the luminance of the two pixels of "92" are closest to the pixel of the representative point.

In this case, a pixel having a brightness value of "84" is selected, and as a result, the representative point shown in FIG.
It is determined that the luminance value shown in (c) has moved to the pixel of “84”. The representative point is located on the second line, and the brightness value is "8.
Since the "4" pixel is located on the first line, it is detected that there is a movement for one line even if it moves to the previous line (Y = -1).

It should be noted that, using the above-mentioned first method, FIG.
When the pixel having the luminance value “92” shown in FIG. 3 is used as the representative point and the representative point is compared with each pixel in the odd field shown in FIG. 3D to detect the motion vector, the luminance value is “9”.
It is determined that the representative point of "2" has moved to the pixel having the luminance value of "88" shown in FIG. In this case, the representative point,
Since the pixel having the luminance value of “88” and the pixel having the luminance value of “88” are both located on the second line, there is no movement (Y = 0).

However, pixels are searched from the upper line toward the lower line, and at each time point, the pixel having the smallest correlation value with the representative point is stored as a candidate, and the pixel and the correlation value are stored. If a pixel that is the same or has a smaller correlation value than that pixel is detected, the candidate pixel is replaced each time, and the second method for detecting the pixel with the smallest correlation value is adopted to calculate the motion vector. When detecting, it becomes as follows.

A case will be described below in which a motion vector is detected with a pixel having a luminance value of "84" shown in FIG. 3C as a representative point.

A representative point having a luminance value of "84" and FIG.
3 is compared with each pixel in the odd-numbered field shown in FIG. 3B, and the pixel having the closest brightness to the representative point is detected from FIG.

In this case, the luminance value of FIG. 3 (d) is "80".
And two pixels of "88" have the closest luminance to the pixel of the representative point.

In the second method, a pixel having a luminance value of "88" is selected, and as a result, the representative point shown in FIG.
It is determined that the pixel having the luminance value shown in (d) has moved to “88”. The representative point is located on the first line and the brightness value is "8.
Since the 8 "pixel is located on the second line, here, 1"
If it moves to the next line, it is detected that there is a movement of one line (Y = 1).

On the other hand, the prefilter 1 of the present invention
A case where a motion vector is detected using 0 will be described with reference to FIGS.

As a result of interline interpolation in the odd field by the vertical LPF 14 of the prefilter 10,
Interpolated video signals as shown in FIGS. 3E and 3G are obtained. Similarly, as a result of inter-line interpolation in the even field by the vertical LPF 14, an interpolated video signal as shown in FIG. 3F is obtained.

In this case, the luminance value shown in FIG.
The representative point of "4" is compared with each pixel shown in FIG. Then, at the representative point, the brightness value shown in FIG.
Although it is determined that the pixel has moved to the 4 "pixel, the representative point and the pixel having the luminance value of" 94 "shown in FIG. 3 (f) are both located on the second line, so there is no motion, that is, the pixel is stationary. (Y = 0).

The luminance value shown in FIG. 3 (f) is "94".
Also in the comparison between the representative point of FIG. 3 and each pixel shown in FIG. 3G, it is judged that the representative point has moved to the pixel having the luminance value of “94” shown in FIG. And FIG. 3 (g)
Since the pixels having the luminance value of “94” shown in are both located on the second line, it is determined that there is no motion, that is, still (Y = 0).

When the prefilter 10 is used, it is determined to be stationary regardless of which of the first method and the second method described above is adopted.

By using the prefilter 10 in this way, it is possible to eliminate the vertical error in the motion detection which has occurred due to the nature of the interlaced signal, and it has been conventionally detected that there is one line motion in the vertical direction. Even in this case, it can be accurately determined that the user is stationary. As a result, it is possible to provide a more legible image.

Further, referring to FIG. 4, prefilter 10
In the case where is not used, as shown in FIG. 4A, a plurality of pixels whose correlation values with the representative points are similar to each other may be detected, but the frequency characteristics are improved by using the prefilter 10. By doing so, the frequency characteristic as shown in FIG. 4B is obtained, and the pixel having the minimum correlation value with the representative point can be easily detected.

Further, by varying the coefficient Kv of the vertical LPF 16, the coefficient Kh of the horizontal LPF 20, and the selection signal SEL1 of the horizontal HPF 18, the prefilter 1
The frequency characteristic of 0 can be made variable, and the subsequent motion detection circuit 78
It is possible to configure the optimum prefilter 10 according to the size of the detection area in.

Further, although the detection area in the motion detection circuit 78 is fixed in the past, the coefficient K of the vertical LPF 16 is fixed.
v, the coefficient Kh of the horizontal LPF 20, and the horizontal HPF 18
By making the selection signal SEL1 of (1) variable, it is possible to set the detection area according to various video sources also in the motion detection circuit 78, the versatility of the circuit can be improved, and the cost can be reduced. You can also

Further, referring to FIG. 5, a prefilter 10a according to another embodiment of the present invention includes a vertical HPF 80 between the vertical LPF 16 and the horizontal HPF 18 of the prefilter 10 shown in FIG. Since the other components are the same as those of the prefilter 10, the redundant description will be omitted.

The vertical HPF 80 of the prefilter 10a is
1H delay circuits 82 to 94, a selection circuit 96 and a subtraction circuit 98 are included.

In each of the 1H delay circuits 82 to 94, the vertical LP
The interpolated video signal from F16 is delayed by one line and is given to the subsequent 1H delay circuit. Selection circuit 9
In 6, the output from the corresponding 1H delay circuit is selected according to the selection signal SEL2 and is given to the subtraction circuit 98. In the subtraction circuit 98, the output of the selection circuit 96 is subtracted from the interpolated video signal from the vertical LPF 16 to obtain an interpolated video signal from which the vertical offset component is removed, and the interpolated video signal is given to the horizontal HPF 18.

The selection signal SEL2 is set to any of 3 to 8, and as a result, the vertical HPF 80 can change the cutoff frequency and the frequency characteristic can be made variable. Therefore, by varying the selection signal SEL2 like the coefficients Kv, Kh, and the selection signal SEL1, it is possible to configure the prefilter 10a according to the size of the detection region in the motion detection circuit 78.

According to such a prefilter 10a,
In addition to the effect of the prefilter 10, an interpolated video signal from which the vertical offset component is removed is obtained.

Although the prefilters 10 and 10a are arranged in front of the motion detecting circuit 78 in the embodiment of the invention described above, they may be formed as a part of the motion detecting circuit.

Further, the vertical LPF 16, the horizontal HPF 18,
The arrangement of the horizontal LPF 20 and the vertical HPF 80 is not limited to the embodiment of the invention described above, and any arrangement is possible.

[0095]

According to the present invention, the interlaced video signal can be processed so that the motion can be detected more accurately.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a vertical LPF 14.

FIG. 3 is an illustrative view showing a comparison between a case where motion detection is performed without using the present invention and a case where motion detection is performed using the present invention.

FIG. 4 is a graph for explaining the characteristics of the present invention.

FIG. 5 is a circuit diagram showing another embodiment of the present invention.

[Explanation of symbols]

10, 10a prefilter 12, 52-64 flip-flops 14, 16 Vertical LPF 18 Horizontal HPF 20 horizontal LPF 22, 26, 44, 50, 70, 76 Multiplier circuit 24, 48, 74, 82 to 94 1H delay circuit 28, 46, 72 Adder circuit 66, 96 selection circuit 68, 98 Subtraction circuit 78 Motion detection circuit 80 Vertical HPF

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-8-107548 (JP, A) JP-A-8-107546 (JP, A) JP-A-5-83602 (JP, A) JP-A-5- 183873 (JP, A) JP 63-250986 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N ⁷ /00-7/088 H04N 5/14-5/217 H03H 17/00-17/08

Claims (11)

(57) [Claims] 1. A prefilter for processing an interlaced video signal, comprising interline interpolating means for interpolating the interlaced video signal between lines in a field to obtain an interpolated video signal , wherein the interline interpolating means comprises: In odd fields
The first coefficient K1 (K1 = 0.25 or
Is 0.75), and in the even field the interlace
The video signal is multiplied by the second coefficient (1−K1), respectively.
First multiplying means for delaying the interlaced video signal by one line
Delay means, in the odd field, delayed by the first delay means
The second coefficient (1-K1) is added to the interlaced video signal.
In the even field, it is delayed by the first delay means.
The first coefficient K1 is added to the interlaced video signal
Second multiplying means for multiplying, and the first video signal from the first multiplying means and the second multiplying means
Interpolation video signal is obtained by adding the second video signal from the stage
A prefilter comprising a first adding means . 2. The interpolation image from the interline interpolation means
A first fill for removing a vertical noise component of an image signal
Removes the horizontal offset component of the interpolated video signal
A second filter for removing noise components in the horizontal direction of the interpolated video signal,
The prefilter according to claim 1 , comprising three filters . 3. The first filter, the interpolated video signal
And a third delay means for delaying the output of the first filter by one line.
Means for outputting a fourth coefficient (1−Kv) to the output from the second delay means.
Fourth multiplying means for multiplying, and an output of the third multiplying means and an output of the fourth multiplying means
Interpolated video from which noise components in the vertical direction have been removed by adding
3. A prefilter according to claim 2 including second adder means for obtaining a signal . 4. The third coefficient Kv and the fourth coefficient
The prefilter according to claim 3, wherein (1-Kv) is variable . 5. The second filter, the interpolated video signal
A third delay means for delaying, and subtracting the output of the third delay means from the interpolated video signal.
The interpolated video signal with the horizontal offset component removed.
5. A subtraction means for obtaining a number is included in any one of claims 2 to 4.
Pre-filter as described in. 6. The third delay means is connected in multiple stages and
A flip that delays the interpolated video signal in units of one clock.
Select the output from the flip-flops and the flip-flops connected in multiple stages.
A prefilter according to claim 5 including first selecting means for performing. 7. The third filter, the interpolated video signal
And a fifth delay means for delaying the output of the third filter by one clock.
A fifth coefficient (1-Kh) is applied to the output from the delay means and the fourth delay means.
Sixth multiplying means for multiplying, and an output of the fifth multiplying means and an output of the sixth multiplying means
Interpolated video from which horizontal noise components have been removed by adding
7. A prefilter according to any one of claims 2 to 6 including third adder means for obtaining a signal . 8. The fifth coefficient Kh and the sixth coefficient
The prefilter according to claim 7, wherein (1-Kh) is variable . 9. A vertical offset of the interpolated video signal.
The second filter further comprising a fourth filter for removing a noise component.
9. The prefilter according to any one of 1 to 8. 10. The fourth filter is configured to receive the interpolated video signal.
Fifth delay means for delaying the signal , and subtracting the output of the fifth delay means from the interpolated video signal
Te, interpolated video signal which offset component in the vertical direction is removed
A prefilter according to claim 9 including subtraction means for obtaining a number . 11. Is the fifth delay means connected in multiple stages?
Sixth delay for delaying the interpolated video signal on a line-by-line basis
Selects the output from the extension unit, and the sixth delay means is cascaded
A prefilter according to claim 10 including second selecting means .