JP2001238184A - Video signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a video signal processing circuit where deterioration in the vertical resolution is reduced in the interpolation in a vertical direction of an interlace signal and further large scale integration LSI is facilitated be cause the processing circuit comprises digital circuits. SOLUTION: A multiplier (1st multiplier) 4 multiplies a coefficient (a) and an input video signal together and a multiplier (2nd multiplier) 5 multiplies a coefficient (1-a) and an output signal of a line memory 2 together. An adder 6 sums output signals from the multipliers 4, 5. A comparison discriminator 9 discriminates a correlation between the input video signal and a 1-field delay signal in an odd number field and a correlation between the input video signal and a (1 field + 1 line) delay signal in an even number field and controls a selector 10 to select an output signal from the line memory 2 when the correlation exists or to select an output signal from the adder 6 when there is no correlation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit, and more particularly to a video signal processing circuit capable of reducing deterioration of vertical resolution when interpolating an interlace signal in a vertical direction.

[0002]

2. Description of the Related Art When a picture is reduced or synthesized by PIP (Picture-in-Picture) or the like, in vertical interpolation (thinning) processing, a vertical resolution is deteriorated. Usually, in order to reduce this, the characteristics of the interpolation (decimation) filter are devised. However, since the interpolation filter is a low-pass filter (LPF), there is a limit to its improvement.

FIG. 3 is a block diagram showing a conventional interpolation filter. In FIG. 3, a video signal input from an input terminal 1 is supplied to a line memory 2 and a multiplier 4. Then, the line memory 2 obtains a one-line delay signal obtained by delaying the input video signal by one line (1H) and supplies it to the multiplier 5. The coefficient control circuit 3 supplies a coefficient a and a coefficient (1-a) to the multipliers 4 and 5, respectively. The sum of these two coefficients is one. The multiplier 4 multiplies the input video signal by a coefficient a and supplies the output signal to the adder 6. Similarly, the multiplier 5 multiplies the output signal of the line memory 2 by the coefficient (1-a) and supplies the output signal to the adder 6. The adder 6 adds the two signals to obtain an interpolation signal, and outputs the interpolation signal from the output terminal 7.

FIG. 4 is a diagram for explaining an interpolation process in a conventional example, and a case of thinning out to 3/4 will be described.
In FIG. 4, scanning lines 1, 2, 4, and 4 of an odd field n are shown.
5 is a level 0% signal (black signal), and scanning line 3 is a level 10
0% signal (white signal). Similarly, the scanning lines 263, 264, 26 of the even field (n-1) which is the previous field
6,267 is a level 0% signal (black signal), and the scanning line 265 is a level 100% signal (white signal).

Then, a filter operation for thinning out to 3/4 by linear interpolation is performed, and the obtained interpolation signals are 1 ', 2',
..., 267 ', 1' is exactly the same as 1 and level 0%
Signal, 2 ′ is (2/3) × scanning line 2+ (1/3) × scanning line 3
33% signal, 3 'is (1/3) × scanning line 3+
(2/3) × scanning line 4, level 33% signal, 5 ′ is 5
Is exactly the same as the above, and becomes a level 0% signal. Similarly, 236 '
Is exactly the same as 263, the level 0% signal, and 264 ′ is (2 /
3) × scanning line 264+ (３) × scanning line 265 becomes a level 33% signal, and 265 ′ is (1/3) × scanning line 265+
(2/3) × scanning line 266, level 33% signal, 26
7 'is exactly the same as 267 and is a level 0% signal.

[0006]

In the conventional example described above, the level 100% signal of the scanning line 3 and the scanning line 265 is used.
The interpolation signal of (white signal) 2 ′, 3 ′, 264 ′ and 265 ′ becomes a gray signal of level 33%, and there is a problem that the vertical resolution is deteriorated. In this example, the resolution is reduced to 3/4. However, the resolution may be further degraded depending on other thinning rates (the number of pixels to be thinned) and interpolation (thinning) places. The present invention has been made in order to solve the above-described problem, and the deterioration of the vertical resolution at the time of vertical interpolation of an interlace signal is reduced.
In addition, an object of the present invention is to provide a video signal processing circuit which can be constituted by a digital circuit and can be easily integrated into an LSI.

[0007]

In order to achieve the above object, in a video signal processing circuit for performing vertical interpolation processing on an interlaced video signal, a one-line delay signal obtained by delaying an input video signal by one line is used. A line memory for outputting, a field memory for outputting a one-field delay signal obtained by delaying the input video signal by one field, a coefficient control circuit for outputting a coefficient a and a coefficient (1-a), A first multiplier for multiplying by a coefficient a, and the coefficient (1-
a) a second multiplier that multiplies a), an adder that adds the output signal of the first multiplier and the output signal of the second multiplier, an output signal of the line memory, and an output of the adder. A selector for inputting two signals and selecting and outputting one of the signals; a correlation between the input video signal and the one-field delay signal in an odd field; and a correlation between the input video signal and (1) in an even field. (Field + 1 line) determine the correlation with the delay signal, if there is a correlation, select the output signal of the line memory, if there is no correlation, select the output signal of the adder, the selector And a comparison / determination device for controlling the video signal processing circuit.

[0008]

FIG. 1 is a block diagram showing an embodiment of the present invention. 1, the same parts as those of the conventional example of FIG. 3 are denoted by the same reference numerals, and the description thereof will be omitted. In FIG. 1, a video signal input from an input terminal 1 is supplied to a line memory 2, a multiplier (first multiplier) 4, a field memory 8, and a comparison / determination unit 9. Then, the line memory 2 obtains a one-line delay signal obtained by delaying the input video signal by one line (1H), and supplies it to the multiplier (second multiplier) 5 and the selector 10. The coefficient control circuit 3 supplies a coefficient a and a coefficient (1-a) to the multipliers 4 and 5, respectively. The sum of these two coefficients is one. Multiplier 4
Multiplies the input video signal by a coefficient a and supplies the output signal to the adder 6. Similarly, the multiplier 5 multiplies the output signal of the line memory 2 by the coefficient (1-a) and supplies the output signal to the adder 6. The adder 6 adds the two signals to obtain an interpolation signal, and supplies the interpolation signal to the selector 10.

A field memory 8 stores an input video signal
A one-field delay signal with a field delay is obtained and supplied to the comparison / determination unit 9. The comparison / determination unit 9 compares the video signal from the field memory 8 with the video signal from the input terminal 1 to determine whether there is a correlation between the two video signals, and supplies the determination result to the selector 10. ing. The selector 10 selects a signal from the line memory 2 if the video signal has a correlation, and selects a signal from the adder 6 if there is no correlation, and outputs the signal from the output terminal 7 based on the determination result of the comparison / determiner 9. are doing.

FIG. 2 is a diagram for explaining the interpolation processing in the present invention, and a case of thinning out to 3/4 will be described.
In FIG. 2, scanning lines 1, 2, 4, and 4 of an odd field n are shown.
5 is a level 0% signal (black signal), and scanning line 3 is a level 10
0% signal (white signal). Similarly, the scanning lines 263, 264, 26 of the even field (n-1) which is the previous field
6,267 is a level 0% signal (black signal), and the scanning line 265 is a level 100% signal (white signal).

First, in the field n, the correlation between the scanning line 1 and the scanning line 263, the scanning line 2 and the scanning line 264, the scanning line 3 and the scanning line 265, Since the scanning line 4 and the scanning line 266 and the scanning line 5 and the scanning line 267 all have a correlation, all the interpolation signals output from the selector 10 are signals from the line memory 2.
As a result, the obtained interpolation signals 1 ', 2', ..., 5 'are completely the same as the original signals 1, 2, ..., 5; 3' is a level 100% signal, and the others are level 0% signals. No degradation of the vertical resolution has occurred.

Next, in the field (n-1), the correlation between the scanning line 263 and the scanning line 2, the scanning line 266 and the scanning line 5, and the scanning line 267 are found from the correlation between the previous field and the field (n-2). And the scanning line 6 have a correlation, the interpolation signal output from the selector 10 is a signal from the line memory 2, but the scanning line 264 and the scanning line 3 and the scanning line 265 and the scanning line 4
Since there is no correlation, the interpolation signal output from the selector 10 is a signal from the adder 6.

In this case, the obtained interpolation signal 263 '
And 267 ′ are exactly the same as the original signals 263 and 267, and become a 0% level signal.
4 'and 265' become signals from the adder 6, and 264 '
Is (2/3) × scanning line 264+ (1/3) × scanning line 265 and is a 33% signal, and 265 ′ is (1/3) × scanning line 2
65+ (2/3) × scanning lines 266, which is a level 33% signal.

As described above, in the odd field, the correlation between the input video signal and the one-field delay signal is calculated, and in the even field, the input video signal is correlated with (1 field + 1 line).
The correlation with the delay signal is determined, and if there is a correlation, the output signal of the line memory 2 is selected. If there is no correlation, the output signal of the adder 6 is selected. Also, FIG.
As shown in the figure, the vertical resolution of the interpolation signals 2 'and 3' is improved as compared with the conventional example. Further, the circuit of the present invention has a simple configuration in which a field memory 8, a comparison / determination unit 9, and a selector 10 are added to the conventional example shown in FIG. 3, and all of them can be configured by digital circuits.
LSI implementation is also easy.

[0015]

According to the video signal processing circuit of the present invention, the deterioration of the vertical resolution at the time of the vertical interpolation of the interlace signal is reduced, and the video signal processing circuit can be constituted by a digital circuit.
There is an extremely excellent effect that the conversion is easy.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating an interpolation process according to the present invention.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a diagram for explaining an interpolation process in a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal 2 Line memory 3 Coefficient control circuit 4 Multiplier (first multiplier) 5 Multiplier (second multiplier) 6 Selector 7 Output terminal 8 Field memory 9 Comparison judging device 10 Selector

Continued on front page F-term (reference) 5C021 PA52 PA62 PA66 PA79 PA89 RA15 RB06 SA22 SA23 XB07 ZA04 5C063 AC01 BA01 BA09 CA01 CA05 CA36 5C082 AA01 AA02 BA12 BA27 BB15 BC07 CA21 CA34 CA55 CA81 DA53 MM10

Claims (1)

[Claims] A video signal processing circuit for performing a vertical interpolation process on an interlaced video signal, comprising: a line memory for outputting a one-line delay signal obtained by delaying an input video signal by one line; A field memory that outputs a delayed one-field delay signal, a coefficient control circuit that outputs a coefficient a and a coefficient (1-a), a first multiplier that multiplies the input video signal by the coefficient a, A second multiplier for multiplying the output signal of the line memory by the coefficient (1-a); an adder for adding an output signal of the first multiplier and an output signal of the second multiplier; A selector for inputting two signals of an output signal of a line memory and an output signal of the adder and selecting and outputting one of the signals; and in an odd field, the input video signal and the one feed signal. In the even field, the correlation between the input video signal and the (1 field + 1 line) delay signal is determined. If there is a correlation, the output signal of the line memory is selected. A video signal processing circuit, comprising: a comparison / determination unit that controls the selector so as to select an output signal of the adder.