JPH1197670A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To set the characteristics from being affected by fluctuations of the thickness of a gate contact layer by setting a thickness thereof to the thickness of stabilized region where the changes in substrate sheet resistance for change of thickness is reduced. SOLUTION: Since a region exceeding in a thickness of 15 nm of a gate contact layer becomes the stabilized region, where the substrate sheet resistance Ro has becomes hardly changing and therefore the gate contact layer 16 is formed of In0.52 Al0.48 As in the thickness of 15 mm. Thereby, in the case of forming a high electron mobility transistor(HEMT)19, even if the film thickness of the gate contact layer 16 fluctuates, a threshold Vt of the HEMT 19 will not fluctuate because the amount of change of the substrate sheet resistance R square is in the stabilized region. Therefore, characteristics of each element can be stabilized, good value for mutual conductance gm can also be obtained and optimum matching of lattice constant between the gate contact layer 16 and substrate 11 can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a film structure used for a field effect transistor of a heterojunction type.

[0002]

2. Description of the Related Art High electron mobility transistors (High Electron Mobility Transistors), which are one of heterojunction type field effect transistors.
Mobility Transistor (hereinafter referred to as HEMT) forms a heterojunction by forming a channel layer having a large electron affinity and forming a semiconductor layer having a small electron affinity as an n-type doped layer as compared with the channel layer. It has a film structure.

[0005] Then, the gate,
The HEMT is completed by forming three electrodes, a source and a drain. Of these three electrodes, the gate electrode that makes Schottky contact can obtain good Schottky characteristics by being formed in contact with a semiconductor layer (gate contact layer) having a high energy barrier. On the other hand, the source and drain electrodes making ohmic contact are
It is formed in contact with an n-type semiconductor layer (cap layer) having a low energy barrier.

Of these, the gate contact layer that contacts the gate electrode is formed under the cap layer that contacts the source and drain electrodes. Therefore, in order to form the gate electrode, only the region where the electrode is to be formed is formed. The cap layer must be removed to expose the gate contact layer on the surface. The processing of exposing the gate contact layer is performed by removing the cap layer on the surface side by etching using a solution or gas.

[0005] HEMT produced by such a process
May be formed, for example, as an MMIC (Monolithic Microwave IC). Since the MMIC is an IC mainly used in a high frequency region such as a millimeter wave band, variations in characteristics of individual elements greatly affect overall characteristics.
For example, if there is a variation in the threshold voltage Vt of each HEMT constituting the MMIC,
In order to cause a deviation of the MIC matching condition, it is necessary to perform adjustment.

The inventors of the present invention have studied the causes of fluctuations in the threshold voltage Vt of the HEMT and have found that variations in the thickness of the gate contact layer greatly affect the threshold voltage Vt. Since the gate contact layer is formed through the etching process as described above, the thickness of the gate contact layer after the HEMT is formed is determined by the etching accuracy. Therefore, in order to suppress the fluctuation of the threshold voltage Vt, it is important to improve the etching accuracy.

For example, JP-A-6-216160 discloses a Schottky contact layer (gate contact layer).
A technique is disclosed in which an etching stopper layer made of InP is inserted between a carrier supply layer (doped layer) and the carrier supply layer (doped layer) to improve the etching accuracy of the carrier supply layer.

Assuming that this conventional technique is applied to improve the etching accuracy of the gate contact layer, for example, a film structure as shown in FIG. 9 may be used. That is, the buffer layer 2 and the
A channel layer 3, a spacer layer 4, a doped layer 5, and a gate contact layer 6 are sequentially formed, and a gate contact layer 6 of InAlAs and a cap layer 7 of InGaAs are formed.
The etching stopper layer 8 made of InP is inserted between the two.

When recess etching is performed on this film structure, the etching rate of InP can be sufficiently reduced with respect to the etching rates of InAlAs and InGaAs by appropriately selecting an etching solution. Therefore, it is expected that the etching accuracy for the gate contact layer can be improved.

[0010]

However, in this prior art, in order to form the etching stopper layer 8 using the InP layer, it is necessary to introduce a P (phosphorus) material into the film growth chamber. However, P is, for example, As of the same V group.
Since the vapor pressure is higher by one digit or more than that of (arsenic), the control is difficult, and a special device is required.

In addition, P remains inevitably left in the film growth chamber due to the high vapor pressure. Therefore, during the subsequent growth of the InGaAs channel layer 3 in the same device, the remaining P is mixed and actually becomes In.
GaAsP will be formed. Generally, in a P-based compound semiconductor, the effective mass of electrons is larger than that in an As-based compound semiconductor, which means that electron mobility is reduced. That is, it is considered that the possibility that the film quality of the channel layer 3 is deteriorated is increased.

Therefore, the inventors of the present invention disclosed in Japanese Unexamined Patent Publication No.
When the technique disclosed in Japanese Patent No. 216160 is applied, it is effective in reducing the film thickness variation itself in the etching of the gate contact layer.
As a result, it was not possible to satisfy the high-speed operation and the high output, and it was concluded that the actual effectiveness was low.

According to the studies by the inventors of the present invention, it has been found that variations in the thickness of the gate contact layer etched are inevitable to some extent. Therefore, in order to produce a HEMT with small characteristic variations, H
It is necessary to have a film structure in which the threshold voltage Vt of the EMT is not affected by the variation in the thickness of the gate contact layer, and a technique for providing such a film structure has not been proposed so far.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device having a film structure in which characteristics such as a threshold voltage are not affected by variations in the thickness of a gate contact layer. To provide.

[0015]

According to the semiconductor device of the present invention, all or part of a semiconductor layer forming a heterojunction and having a small electron affinity is formed as an n-type doped layer, and the doped layer is formed as an n-type doped layer. The thickness of the gate contact layer having a smaller electron affinity than the channel layer formed in the upper layer is set to a thickness included in the stable region where the amount of change in the substrate sheet resistance with respect to the change in the film thickness is small. Therefore, for example, even if the thickness of the gate contact layer varies when the HEMT is formed, the threshold voltage Vt of the HEMT does not vary because the thickness is included in the stable region. Characteristics can be stabilized.

According to the semiconductor device of the second aspect, the gate contact layer is made of non-doped In _x Al _1-x As.
(0 ≦ X ≦ 1) and the film thickness is set to 15 nm or more. For example, when a HEMT is formed,
With suppress the variation in the threshold voltage Vt, also the value of the transconductance g _m can be improved.

According to the third aspect of the present invention, the gate contact layer is made of non-doped In _x Al _1-x As.
(0 ≦ X ≦ 1) and the film thickness is set to less than 20 nm. Therefore, even if the etching accuracy is not good and the gate contact layer is over-etched, the characteristics of each element can be stabilized. it can.

According to the semiconductor device of the fourth aspect, the composition ratio X of In _X Al _{1 -X} As forming the gate contact layer
Is set to 0.52, the lattice constant between the gate contact layer and the substrate can be well matched.

According to the semiconductor device according to claim 5, the doped layer, since it is configured with the n-type _{In Y Al 1-Y As (} 0 ≦ Y ≦ 1), matching the lattice constants of the doped layer and the substrate Can be adjusted to be good.

According to the semiconductor device of the sixth or seventh aspect, the doped layer is constituted as a planar doped layer in which a single atom interface is n-type doped (claim 6). Since it is 10 ¹² cm ⁻² (Claim 7), the doped layer can be formed extremely thin, and the impurity doping concentration can be optimized.

According to the semiconductor device according to claim 8 or 9, wherein the channel _{layer, In Z Ga 1- Z As (} 0 ≦ Z ≦
1) (claim 8). Specifically, the non-doped I
n _{0. Since} the first channel layer is composed of a 16 nm thick first channel layer made of ₈ Ga _0.2 As and a 4 nm thick second channel layer made of In _0.53 Ga _0.47 As (claim 9). _in, in _{Z Ga 1-Z} As
Is controlled so that a lattice mismatch with the substrate or the doped layer does not occur, and the second channel layer controls the electron density distribution to be located substantially at the center of the channel layer. The mobility can be further increased.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
This will be described with reference to FIGS. FIG. 1 shows the HEM of the present invention.
3 schematically shows a cross section of a film structure when applied to T. FIG. In FIG. 1, a non-doped In _0.52 Al film having a thickness of 100 nm is formed on a semi-insulating InP substrate 11.
_The buffer layer 12 made of _0.48 As is arranged. On the buffer layer 12, a first channel layer 13a made of non-doped In _0.8 Ga _0.2 As having a thickness of 16 nm and In _0.53 Ga _{0 . 47}
A second channel layer 13b made of As is provided.

The second channel layer 13b has a thickness of 5n.
m non-doped In _0.52 Al _{0 . A} spacer layer 14 made of ₄₈ As is disposed on the spacer layer 14.
^The Si planar dope layer 15 which is set as extremely high as ¹² cm ⁻² is arranged. On the Si planar doped layer 15, a non-doped In _0.52 Al having a thickness of 15 nm is formed.
_A gate contact layer 16 made of _0.48 As is provided. On the gate contact layer 16, In _0.53 Ga _0.47 As with a thickness of 20 nm and doped with Si so as to have an impurity concentration of 1 × 10 ¹⁹ cm ^−3.
A cap layer 17 is provided.

The channel layer 13 composed of the first and second channel layers 13a and 13b is a region where electrons as carriers travel (move) during the operation of the HEMT, and the buffer layer 12 and the spacer layer 14 as other layers. Due to the band gap formed between the region and the Si planar doped layer 15, the deeper the potential well formed in this region (the lower the energy order), the lower the concentration of electrons.

For this reason, the first channel layer 13 a
The value of Z giving the composition ratio of _Z Ga _1-Z As was
It is sufficient to increase the composition ratio of InAs so as not to cause lattice mismatch with the Si planar doped layer 15,
As the best composition ratio, Z = 0.8, that is, In _0.8 G
a _0.2 As has been selected.

Further, the second channel layer 13b is formed of In
By being composed of _0.53 Ga _0.47 As, the distribution of electrons in the channel layer 13 is kept away from the hetero interface of the spacer layer 14 so that the peak of the electron density distribution is located substantially at the center of the channel layer 13. It acts to increase the mobility of electrons by controlling. In this case, by adding the second channel layer 13b, the film thickness at which the effect of increasing the electron mobility can be obtained without substantially being affected by a slight increase in the energy level of the channel layer 13 is 4 nm. For example, Japanese Patent Laid-Open No. 6-1
No. 40435.

The Si planar doped layer 15 induces a two-dimensional electron gas in the channel layer 13, so that the In _0.52 Al _{0 having an} electron affinity smaller than the In _0.53 Ga _0.47 As of the second channel layer 13 b. _.48 As was planar-doped with n-type impurity Si.

FIG. 2 is a schematic cross-sectional view showing a case where the HEMT (semiconductor device) 19 is formed as an element using the HEMT substrate 18 having the above-described film structure. The source electrode 20 and the drain electrode 21 by ohmic contact are:
The gate electrode 22 formed on the cap layer 17 and formed by Schottky contact is formed in the gate contact layer 16 in the recess region 23 where the cap layer 17 is removed by selective etching.
Is formed on. A 100 nm-thickness SiN _X film 24 is formed so as to cover the entire exposed surface of the source electrode 20, the drain electrode 21 and the gate electrode 22.

Next, the thickness of the gate contact layer 16 is set to 1
The reason for setting the thickness to 5 nm will be described with reference to FIGS. FIG. 3 shows a HEMT having the film structure of FIG.
2 shows the measured value (vertical axis) of the substrate sheet resistance R _□ (unit: Ω / □) when the thickness of the gate contact layer was changed (horizontal axis). The thicknesses of the layers other than the gate contact layer were set in the same manner as shown in FIG. 1, and the substrate sheet resistance R _□ was measured using a non-contact sheet resistance measuring instrument (for example, Model 1320 manufactured by Rehighton Corporation). .

As shown in FIG. 3, the region where the thickness of the gate contact layer exceeds 15 nm is a stable region where the substrate sheet resistance R _□ hardly changes. For example,
Substrate sheet resistance R _{□ at} film thickness of 15 nm and 20 nm
Was 230 Ω / □ and 228 Ω / □. Since the measurement accuracy of the sheet resistance measuring instrument is ± 1%, the significance of the difference between the two measured values is considered to be small. Therefore, if the thickness of the gate contact layer is set so as to be 15 nm or more,
It is considered that the HEMT characteristics do not vary even if the film thickness varies somewhat in the gate contact layer etching process.

FIG. 4 shows a simulation of the reciprocal n _S ^-1 of the sheet carrier concentration of the substrate with respect to the thickness of the gate contact layer under the same conditions as the measurement shown in FIG. n
_S ⁻¹ is proportional to the substrate sheet resistance R _□ . For the boundary conditions and the like in the simulation, numerical values of a database accumulated by experiments and the like performed by the inventors of the present invention so far were used. In the simulation result shown in FIG.
From the vicinity of nm, the reciprocal n _S ⁻¹ is saturated and converges,
Supports the actual measurement results.

FIG. 5 shows a simulation result of the intrinsic transconductance g _m0 (vertical axis), which is a kind of figure of merit of the HEMT, with respect to the thickness D of the gate contact layer. The horizontal axis is the gate voltage VG (V).
It is. Referring to FIG. 5, it can be seen that the thinner the gate contact layer, the higher the intrinsic transconductance g _m0 .

However, the HEMT actually created
In transconductance _{g m} to be measured, the parasitic resistance _{R S}
(= Recess peripheral resistance + Cap resistance + Contact resistance)
And the value of the parasitic resistance _RS decreases as the thickness of the gate contact layer increases.

The above conditions (the threshold value Vt does not vary,
High transconductance g _m, the parasitic resistance R _S is small) comprehensively a result of considering that to optimize the characteristics of the HEMT, when the film thickness of the gate contact layer is 15nm is the best, and the The conclusion has been reached.

As described above, according to the present embodiment, the gate contact layer 16 is made of In _0.52 Al _0.48 As and the film thickness is set to 15 nm. even 16 thickness of varies, the threshold voltage V of HEMT19 by variation of substrate sheet resistance R _□ is in the less stable area
t no longer varies. Therefore, the characteristics of each element can be stabilized. Further, it is also possible to improve the value of the transconductance g _m. Further, the matching of the lattice constant between the gate contact layer 16 and the substrate 11 can be optimized.

Further, according to the present embodiment, n
The doping concentration of the planar doped layer 15 is 8 ×
Since it is 10 ¹² cm ⁻² , the doped layer can be formed extremely thin, and the impurity doping concentration can be optimized.

The channel layer 13 is made of non-doped In.
_0.8 Ga _0.2 since it is configured in the first channel layer 13a and the second channel layer 13b made of _In 0.53 _{Ga 0.47} As consists As, in the first channel layer _13a, In _{Z Ga 1-Z} The value of Z giving the composition ratio of As is
The electron density distribution can be increased as much as possible without causing lattice mismatch with the substrate 11, the doped layer 15, and the like. Further, by controlling the second channel layer 13b so that the peak of the electron density distribution is located substantially at the center of the channel layer 13, the mobility of electrons can be further increased.

(Second Embodiment) FIG. 6 shows a second embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted. explain. HEMT (semiconductor device) 2 in the second embodiment
In the film structure of No. 5, instead of the Si planar doped layer 15 in the first embodiment, a Si-doped I-doped layer having a 10-nm-thick film has an impurity concentration of 1 × 10 ¹⁹ cm ^−3.
A doped layer 26 made of n _0.52 Al _0.48 As is provided. Such a composition of the doped layer 26 is selected in order to obtain a good lattice constant matching with the substrate 11 made of InP. Other configurations are the same as in the first embodiment.

As described above, the Si planar doped layer 15
Instead, even when placing the doped layer 26 having a thickness of 10 nm, by setting the thickness of the gate contact layer 16 to 15 nm, not fluctuated threshold Vt, high transconductance g _m is the parasitic resistance the HEMT25 good property that R _S is small, can be obtained as in the first embodiment.

(Third Embodiment) FIG. 7 shows a third embodiment of the present invention. The same parts as those of the second embodiment are denoted by the same reference numerals, and description thereof will be omitted. explain. HEMT (semiconductor device) 2 in the third embodiment
7 is composed of a buffer layer 12 and a gate contact layer 1.
The order of formation of the respective layers is opposite to that of the second embodiment shown in FIG. 6 of the second embodiment.

That is, the doped layer 26, the spacer layer 14, the second channel layer 13b, and the first channel layer 13a are formed in the order from the buffer layer 12 to the gate contact layer 16 in this order. HEMT "structure.

[0042] As described above, even when the reverse HEMT structure, by setting the thickness of the gate contact layer 16 to 15 nm, not fluctuated threshold Vt, high transconductance _{g m} is the parasitic resistance R The HEMT 27 having a good characteristic that _S is small can be obtained as in the first embodiment.

(Fourth Embodiment) FIG. 8 shows a fourth embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted. explain. HEMT (semiconductor device) 2 in the fourth embodiment
8 is different from the gate contact layer 16 in the first embodiment in that the gate contact layer 2 having a thickness of 20 nm is used.
9 is different from that of the first embodiment.

The grounds for setting the thickness of the gate contact layer 29 to 20 nm in the fourth embodiment will be described. In order to form the recess region 23 in the cap layer 17 to form the gate electrode 22 in the HEMT, wet etching using a solution or dry etching using a gas is generally performed. In this etching step, the In
Only _0.53 Ga _0.47 As can be etched, and In _0.52 Al constituting the gate contact layer 16 can be etched.
Ideally, _0.48 As should not be etched.

However, In _0.53 Ga _0.47
Both As and In _0.52 Al _0.48 As are In
Is more than 50%, and it is practically difficult to establish a method of etching only one of the two. Therefore, in fabricating the HEMT, an etching method is used in which the etching rate of In _0.53 Ga _0.47 As is relatively high and the etching rate of In _0.52 Al _0.48 As is as low as possible. .

The inventors of the present invention have employed the above-mentioned etching technique by etching using a mixed solution of citric acid and hydrogen peroxide solution to _obtain In _0.53 Ga.
_0. The etching rate ratio of ₄₇ As: In _0.52 Al _0.48 As was set to 16: 1.

However, even with this 16: 1 speed ratio, the etching amount of In _0.52 Al _0.48 As cannot be reduced to zero, and in some cases, it may actually be 5 nm.
In some cases, over-etching of In _0.52 Al _0.48 As occurred. Therefore, In _0.52 Al
_{Even if 0.48} As is over-etched, H
The thickness of the gate contact layer 29 was set to 20 nm in consideration of a margin so as to reduce the variation in the characteristics of the EMT.

As described above, according to the fourth embodiment, even when the gate contact layer 29 is over-etched to some extent, the threshold value Vt does not vary, the transconductance g _m is high, and the parasitic resistance R _S is increased. HEMT 28 having a small characteristic is obtained.

The present invention is not limited to the embodiment described above and shown in the drawings, and the following modifications or extensions are possible. HEMT transconductance gm
The thickness of the gate contact layer may be set to be larger than 15 nm if the reduction of
m or more. Composition ratio of _In X _{Al 1-X} As for the gate contact layer is not limited to X = 0.52, it may be appropriately changed in a range of 0 ≦ X ≦ 1.
Composition ratio of _In Y _{Al 1-Y} As constituting the doped layer is also not limited to Y = 0.52, it may be appropriately changed in a range of 0 ≦ Y ≦ 1.

The second channel layer 13b may be provided as needed, and the channel layer 13 may be made of non-doped In _0.8 Ga _0.2 As with a thickness of 20 nm. Also,
Composition ratio of _In Z _{Ga 1-Z} As constituting the channel layer is not limited to Z = 0.8 or Z = 0.53, 0
It may be changed appropriately within the range of ≦ Z ≦ 1. The doping concentration of the Si planar doping layer 15 may be appropriately changed without being limited to 8 × 10 ¹² cm ⁻² .

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing a cross section of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram schematically showing a cross section when an HEMT element is formed by forming an electrode on a semiconductor device.

FIG. 3 is a diagram showing a result of actually measuring a change in a substrate sheet resistance R _□ when a thickness of a gate contact layer is changed.

FIG. 4 is a diagram showing a result of simulating a reciprocal of a sheet carrier concentration of a substrate when a thickness of a gate contact layer is changed.

FIG. 5 is a diagram showing a simulation result of an intrinsic transconductance g _m0 with respect to a film thickness D of a gate contact layer.

FIG. 6 is a view corresponding to FIG. 2, showing a second embodiment of the present invention;

FIG. 7 is a view corresponding to FIG. 2, showing a third embodiment of the present invention;

FIG. 8 is a view corresponding to FIG. 2, showing a fourth embodiment of the present invention.

FIG. 9 is a diagram corresponding to FIG. 1 showing a conventional technique.

[Explanation of symbols]

13 is a channel layer, 13a is a first channel layer, 13b is a second channel layer, 15 is a Si planar doped layer, 16 is a gate contact layer, 19 and 23 are HEMTs (semiconductor devices), 26 is a doped layer, 27 and 28 Denotes a HEMT (semiconductor device), and 29 denotes a gate contact layer.

Claims (9)

[Claims] A heterojunction formed of a channel layer and a semiconductor layer having a lower electron affinity than the channel layer, wherein all or a part of the semiconductor layer having a lower electron affinity is an n-type doped layer. And a semiconductor device in which a gate electrode forms a Schottky contact with a semiconductor layer having a smaller electron affinity than the channel layer on the doped layer, A semiconductor device, wherein the film thickness is set to a thickness included in a stable region where the amount of change in the substrate sheet resistance with respect to the change in the film thickness is small. 2. The gate contact layer according to claim 1, wherein the gate contact layer is made of non-doped In _X Al _1-X As (0 ≦ X ≦ 1) and has a thickness of 15 nm or more. Semiconductor device. Wherein the gate contact layer, according to claim 1 or 2 together composed of non-doped _{In X Al 1-X As (} 0 ≦ X ≦ 1), film thickness and less than 20nm 13. The semiconductor device according to claim 1. 4. The gate contact layer is composed of In and Al.
4. The semiconductor device according to claim 2, wherein a value of X representing a composition ratio of the semiconductor device is set to 0.52. 5. The semiconductor device according to claim 1, wherein the doped layer is an n-type In _Y Al
5. The semiconductor device according to claim _{1, wherein 1-Y} As (0≤Y≤1). 6. The semiconductor device according to claim 1, wherein the doped layer is configured as a planar doped layer in which a single atom interface is n-type doped. Wherein said planar doped layer dopant concentration 8 × 10 ¹² cm ^- claim, characterized in that a ² 6
13. The semiconductor device according to claim 1. Wherein said channel _layer, In _{Z Ga 1-Z} A
The semiconductor device according to claim 1, wherein s (0 ≦ Z ≦ 1). 9. The method according to claim 1, wherein the channel layer is made of non-doped In.
10. A semiconductor device comprising: a first channel layer made of _0.8 Ga _0.2 As and having a thickness of 16 nm; and a second channel layer made of In _0.53 Ga _0.47 As and having a thickness of 4 nm. 9. The semiconductor device according to 8.