JPH1197283A - Method of manufacturing multiple multilayer ceramic capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely expose inner electrode ends at the side faces to accelerate well alloying inner and outer electrodes, without forming hollows at the inner and outer electrodes faces by cutting grooves into the inner electrodes so as to intersect all the inner electrodes. SOLUTION: Grooves 14 are cut into inner electrode 12 faces exposed at the side faces 13 of a sintered capacitor array body 11 so as to intersect all the electrodes 12 of each of multilayer capacitors. The groove 14 is narrower than the width of the electrode 12 and shallower than 1/2 the length of the electrode 12. The bottom of the groove is curved at the corners 16 and formed like an outward arcuate bottom face 17, thereby perfectly exposing the ends of every electrode 12, increasing the surface area of the end of the electrode 12 and ensuring an insulation distance between opposed outer electrodes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic capacitor (hereinafter, referred to as a multilayer capacitor) in which a plurality of multilayer ceramic capacitors (hereinafter referred to as multilayer capacitors) are connected and integrated.
A capacitor array).

[0002]

2. Description of the Related Art A conventional method for manufacturing a capacitor array will be described with reference to the drawings.

FIG. 5 shows a conventional sintered body 2 of a capacitor array.
1 and 6 are views showing a conventional capacitor array.

According to a known multilayer capacitor manufacturing method, a green laminate in which a plurality of dielectric layers and internal electrode layers are alternately laminated is cut into a predetermined capacitor array shape.
After firing, barrel polishing of the obtained sintered body 21 is performed, and the group of internal electrodes 22 formed inside the sintered body 21 is
3 and a method of forming the external electrode 24 so as to cover the exposed internal electrode 22 is generally known.

[0005]

However, in the conventional capacitor array, barrel polishing of the sintered body 21 is performed to expose the internal electrodes 22 to the side surfaces 23. However, in order to completely expose the lead-out portions of the internal electrodes 22, When the barrel polishing is required for a long time and the polishing is not sufficient, when the paste for the external electrode 24 is applied to the exposed surface of the internal electrode 22 and baked, the alloy between the lead-out portion of the internal electrode 22 and the external electrode 24 is formed. When the electrode paste for the external electrode 24 is applied to the uneven surface generated by the insufficient reaction or the uneven surface generated on the side surface of the capacitor array by barrel polishing, bubbles remain on the exposed concave surface of the internal electrode 22, There is a problem in that the bubbling after the application causes voids to form in the air bubbles, resulting in a so-called poor capacity loss.

An object of the present invention is to solve the above-mentioned conventional problems and to provide a method of manufacturing a highly reliable capacitor array.

[0007]

In order to achieve the above object, the present invention provides a method of manufacturing a capacitor array, comprising:
A notch groove is provided in the internal electrode part so as to intersect with all the internal electrodes constituting the multilayer capacitor for each unit, and the internal electrode which cannot be sufficiently exposed only by barrel polishing the side surface of the capacitor array sintered body Exposed the extreme part to the side without fail, and promotes good alloying of the internal electrode and the external electrode without forming a cavity between the internal electrode exposed surface and the external electrode by applying and baking the paste for the external electrode. is there.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention according to claim 1 of the present invention is directed to a capacitor array in which a plurality of multilayer capacitors are built in parallel with a green laminate in which a plurality of internal electrodes and dielectric layers are alternately laminated. After cutting so that the internal electrodes are exposed to the side surfaces facing each other, a cut groove is provided for each internal electrode group surface exposed at the end face of the capacitor array sintered body obtained by firing, and the cut groove is provided. A method for manufacturing a capacitor array in which a plurality of multilayer capacitors are connected in parallel by forming independent external electrodes for each internal electrode group including: a notch groove in the internal electrode portion exposed on the side surface. By forming, the internal electrode end faces are concavely shaped inward and are formed inside the capacitor array sintered body. It can be exposed to the surface. Accordingly, when an independent multilayer capacitor external electrode paste is applied and baked on the internal electrode exposed surface, a favorable alloying reaction is promoted and the occurrence of a capacity loss defect is eliminated, and
The bonding area of the external electrode is increased, and the bonding strength can be increased.

According to a second aspect of the present invention, there is provided a capacitor array according to the first aspect, wherein a cut groove is provided so as to intersect with all internal electrodes of each multilayer capacitor unit, which are exposed on the side surface of the capacitor array sintered body. This is a manufacturing method, whereby all the internal electrode ends of each multilayer capacitor unit formed inside the capacitor array sintered body can be reliably exposed to the side surfaces.

[0010] According to a third aspect of the present invention, the cut groove is formed by:
3. The method for manufacturing a capacitor array according to claim 1, wherein the width of each of the internal electrodes exposed on the side surface of the sintered body of the multilayer ceramic capacitor is smaller than a width of each of the internal electrodes. 4.
This formed inside the capacitor array sintered body,
All the internal electrode ends of each multilayer capacitor unit can be reliably exposed on the side surfaces, and when mounting the external electrodes on the printed circuit board after forming the internal electrode portions, the adjacent multilayer capacitor A short circuit between the external electrodes due to a solder bridge or the like can be prevented.

According to a fourth aspect of the present invention, there is provided the multiple type according to any one of the first to third aspects, wherein the corner portion of the bottom portion of the cut groove is formed into a cut surface in a curved shape. A method of manufacturing a multilayer ceramic capacitor,
This makes it easier to reliably apply the external electrode paste to the corners at the bottoms of the cut grooves and to remove air bubbles that are easily left behind at the corners of the cut grooves.

According to a fifth aspect of the present invention, in the capacitor according to any one of the first to fourth aspects, the cut-out groove bottom face is formed with a cut-out groove in an arc shape outward. This is a method for manufacturing an array, whereby the paste for the external electrode can be easily applied to the corners of the bottoms of the cut grooves, and bubbles that are easily left behind at the corners of the cut grooves can be removed.

According to a sixth aspect of the present invention, the cut depth of the cut groove is formed to be shallower than half the length of the internal electrode formed in the capacitor array sintered body. 6. The method of manufacturing a capacitor array according to claim 1, wherein the exposed surface area of the internal electrode end is increased, the bonding strength of the external electrode is increased, and the capacitor array is manufactured. The insulation distance between the opposing external electrodes of each unit multilayer capacitor formed inside can be ensured.

(Embodiment 1) Hereinafter, a method of manufacturing a quadruple capacitor array according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a perspective view of a sintered body in this embodiment, FIG. 2 is a perspective view of a capacitor array formed using the sintered body of FIG. 1, and FIGS. It is a perspective view of a body.

According to a known multilayer capacitor manufacturing method, a green laminate in which a plurality of dielectric layers and internal electrode layers are alternately laminated is cut into a quadruple capacitor array shape.
The firing was performed. Next, the obtained capacitor array sintered body 1
1, as shown in FIG. 1, a cut groove 14 was provided on the surface of the internal electrode 12 exposed on the side surface 13. The cut groove 14 is smaller than the width of the internal electrode 12 formed inside the capacitor array sintered body 11, and the depth of the cut groove 14 is smaller than the internal electrode 1 formed in the capacitor array sintered body 11.
2 shallower than one half of the longitudinal dimension, and intersect with all the internal electrodes 12 of each multilayer capacitor. Further, the shape of the cut groove 14 is such that the corner part 16 at the bottom of the cut groove 14 is formed into a curved surface. Further, the cut groove 14 was machined so that the bottom face was directed outward to form an arc-shaped machined portion 17. Accordingly, the end portions of all the internal electrodes 12 are completely exposed, and the surface area of the end portions of the internal electrodes 12 is increased.
Also, the insulation distance between the opposing external electrodes 15 was ensured. Next, an electrode paste for the external electrode 15 was applied to the cut grooves 14 and the exposed side surfaces of the internal electrodes 12 and baked to produce the capacitor array shown in FIG. The capacitance of the obtained capacitor array and the capacitance of each of the 100 capacitor arrays in which the external electrodes 15 were formed in the portions where the internal electrodes 12 were exposed without performing the processing for forming the conventional cut grooves, the capacitance of the internal electrodes 12 and the external electrodes 15 The connection status and the adhesive tensile strength of the external electrode were investigated, and the results are shown in (Table 1) and (Table 2).

[0017]

[Table 1]

[0018]

[Table 2]

As can be seen from (Table 1), in the capacitor array according to the manufacturing method of the present invention, although no capacitor array outside the allowable range of the capacitance is generated, the conventional product in which the cut groove 14 is not processed. Are generated out of the allowable range of 13 capacitances. This is because the lead-out portion of the internal electrode 12 is not completely exposed on the side surface 13 of the sintered body 11 and a part of the internal electrode 12 is insufficiently alloyed with the external electrode 15 or the internal electrode 12 A cavity was formed between the side surface of the first electrode and the external electrode 15 and an electrical connection between the internal electrode 12 and the external electrode 15 was insufficient, so that the capacitance was considered to be smaller than an allowable range. . In order to confirm this, the part of the cut groove 14 was polished by polishing 30 pieces of the present invention and the conventional product which were within the allowable range of capacitance and 13 pieces whose capacitance was smaller than the allowable range. As a result of examining the connection state between the electrode 12 and the external electrode 15, any one having an allowable capacitance is completely alloyed between the internal electrode 12 and the external electrode 15, and the existence of the cavity is On the other hand, all of the electrodes outside the permissible range were not recognized, but a part of the internal electrode 12 was insufficiently alloyed with the external electrode 15, and the presence of a cavity on the surface on which the external electrode 15 was formed was confirmed. An unconnected part was found.

As can be seen from (Table 2), the external electrode adhesive strength of the product of the present invention is all clear of the standard value, while that of the product having no cut groove is 42.
Some of them are less than the specified value. From the above results, it is clear that the process of providing the cut groove 14 in the internal electrode 12 portion of the sintered body 11 is an essential condition for obtaining a highly reliable capacitor array.

It has been confirmed that a similar result can be obtained even if the shape of the cut groove 14 as shown in FIGS. 3 and 4 is changed. That is, it can be understood that a capacitor array with high reliability can be obtained by increasing the exposed area of the internal electrode 12 exposed on the side surface 13 of the sintered body 11.

[0022]

As described above, according to the present invention, by providing a cut groove in the internal electrode portion exposed on the side surface of the sintered body,
While reliably exposing the internal electrode formed in the sintered body layer, the surface area of the exposed internal electrode lead-out portion is increased,
A good alloy layer is formed without the presence of a cavity or the like between the external electrodes formed so as to cover the surface thereof, and it is possible to secure electrical connection. In addition to securing the insulation distance, the bonding strength of the external electrode can be increased.

[Brief description of the drawings]

FIG. 1 is a perspective view of a sintered body of a quadruple-type multilayer ceramic capacitor according to an embodiment of the present invention.

FIG. 2 is a perspective view of a capacitor array according to an embodiment of the present invention.

FIG. 3 is a perspective view of a sintered body of a capacitor array according to another embodiment of the present invention.

FIG. 4 is a perspective view of a sintered body of a capacitor array according to another embodiment of the present invention.

FIG. 5 is a perspective view of a sintered body of a conventional quadruple-type multilayer ceramic capacitor array.

FIG. 6 is a perspective view of a conventional quadruple-type multilayer ceramic capacitor array.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Sintered body 12 Internal electrode 13 Side surface 14 Cut groove 15 External electrode 16 Corner part 17 Processing part

Claims (6)

[Claims] 1. A green laminated body in which a plurality of internal electrodes and dielectric layers are alternately laminated in the form of a multi-layer laminated ceramic capacitor in which a plurality of laminated ceramic capacitors are built in parallel, and the internal electrodes are opposed to each other. After being cut so as to be exposed on the side surface to be cut, a cut groove is provided for each internal electrode group surface exposed at the end face of the multiple-layered multilayer ceramic capacitor sintered body obtained by firing, and the internal electrode group including the cut groove is provided. A method of manufacturing a multi-layer monolithic ceramic capacitor in which independent external electrodes are formed for each surface. 2. The multilayer ceramic capacitor according to claim 1, wherein a cut groove is provided so as to intersect all internal electrodes of each multilayer ceramic capacitor unit exposed on the side surface of the multilayer ceramic capacitor sintered body. Manufacturing method. 3. The multiple laminated ceramic capacitor according to claim 1, wherein the cut groove is provided to be narrower than the width of each internal electrode exposed on the side face of the multiple multilayer ceramic capacitor sintered body. Production method. 4. The multi-layer type multilayer ceramic capacitor according to claim 1, wherein the cut groove is formed so that a corner portion of the cut groove bottom is curved. Production method. 5. The multi-layer laminated ceramic according to claim 1, wherein the cut groove is formed so that the cut groove bottom portion is formed in an arc shape outward. Manufacturing method of capacitor. 6. The method according to claim 1, wherein the cut depth of the cut groove is formed to be shallower than one half of a lengthwise dimension of an internal electrode formed in the multiple-layer ceramic capacitor sintered body. A method for manufacturing a multiple-layer ceramic capacitor according to claim 5.