JPH1196680A - Circuit and method for synchronous control - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronous control circuit capable of always correcting synchronism shift between decoded data caused by asynchronously reading and decoding a plurality of compressed data from a buffer memory. SOLUTION: This synchronous control circuit is provided with an audio buffer 30 for storing demultiplexed audio data, a buffer control section 50 for controlling the reading timing or the like of the audio buffer 30, an interruption control section 60 for detecting the deviation of the remaining storage amount of the audio buffer 30 from a range where a video reproducing output is synchronized with an audio reproducing output and informing a CPU 10 of it, and a sampling clock correction section 70 for correcting the decoding sampling clock of the audio data based on the control of the CPU 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for demultiplexing (multiplexing) multiplexed data obtained by encoding and compressing video data and audio data, decoding video data and audio data, and decoding video data and audio data. The present invention relates to a technique for synchronously reproducing data.

[0002]

2. Description of the Related Art Hitherto, multiplexed data including variable length compressed video data (hereinafter, compressed video data) and fixed length compressed audio data (hereinafter, compressed audio data) has been used by using data decoding means. A data reproducing system for decoding and reproducing data is known (Japanese Patent Laid-Open No. 6-76).
471 etc.). In such a data reproduction system, when video data and audio data before compression are mutually related information, for example, when video data and audio data obtained by recording the same location, It is necessary to synchronize data to be decoded and reproduced based on the data. For this reason, conventionally, in order to compensate for a difference in processing time required for decoding compressed video data and compressed audio data, and to synchronize, one of the data decoded by the data decoding means, for example, audio data is stored in a buffer memory. In addition, the timing of reading from the buffer memory is adjusted according to the processing time required for decoding video data.

[0003]

The above-described conventional data synchronization method can be an effective method when the processing time required for decoding compressed video data and compressed audio data is fixed. Also, if within a certain range,
It is also possible to make an adjustment so that one data after decoding is output in synchronization with the other data. However, the time required for decoding the compressed video data and compressed audio data, that is, the decoding speed varies depending on the type of data or the amount of data, and the compression rate is not always constant. Therefore, in the conventional synchronization method, it may not be possible to correctly synchronize with the video data even if the timing of reading the audio data from the buffer memory is adjusted. Such a problem is caused not only by the relationship between the video data and the audio data, but also by temporarily storing n (n is 1, 2,...) Kinds of compressed data in a buffer memory and storing each compressed data. This occurs commonly in systems provided with data decoding means for reading out from the corresponding buffer memory, asynchronously decoding the data, and synchronously outputting n types of decoded data.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a synchronization control circuit that can always correctly correct a synchronization shift between decoded data due to asynchronous reading and decoding from a buffer memory. Another object of the present invention is to provide an improved synchronization control method for synchronously decoding compressed video data and compressed audio data.

[0005]

A synchronization control circuit according to the present invention for solving the above-mentioned problems is to temporarily store n (n is 1, 2,...) Kinds of compressed data in a buffer memory, A circuit applied in a system having data decoding means for reading out compressed data from a corresponding buffer memory and asynchronously decoding the same, and synchronously outputting n kinds of decoded data, wherein each of the n kinds of compressed data is Monitoring the remaining storage amount of any of the compressed data, and when the storage remaining amount of any of the compressed data deviates from a predetermined synchronizable range, dynamically changes the decoding speed of the data decoding means based on the compressed data to thereby store the compressed data. It is characterized by comprising control means for controlling the remaining amount to go to the synchronizable range.

When the n types of compressed data include compressed video data and compressed audio data, the control means causes the decoded data of the compressed video data and the compressed audio data to be synchronously output from the data decoding means. Be composed.

Preferably, the control means is configured to change a decoding speed of the data decoding means through a predetermined interrupt means. The interrupting means includes, for example, a counting means for counting the number of times of writing and reading to and from the buffer memory for each compressed data, and an accumulation means for calculating the remaining amount of storage for each compressed data based on the counting result by the counting means. An amount calculating means, a register for storing an upper limit value and a lower limit value of the synchronizable range, and when the remaining amount of the individual compressed data reaches the upper limit value or the lower limit value in the register, the data decoding is performed. And an output circuit for outputting an interrupt signal for interrupting processing to the means together with a signal indicating the state of the remaining storage amount.

A synchronous control method for solving the above-mentioned other problem is to demultiplex the compressed and multiplexed multiplexed data into decompressed video data and compressed audio data, each of which has a predetermined buffer memory. In a system for temporarily reading and decoding after temporarily storing the compressed audio data, the remaining storage amount of the compressed audio data is monitored,
When the remaining storage amount is larger than a predetermined amount, the decoding speed of the audio data is increased. When the storage remaining amount is smaller than the predetermined amount, the decoding speed of the audio data is reduced, and the decoded video data and The output timing of audio data is synchronized.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of a compression-multiplexed data decoding / reproduction system to which a synchronization control circuit according to the present invention is applied.

In this compression multiplexed data decoding / reproducing system, the multiplexed data obtained by multiplexing the compressed video data and the compressed audio data is input to a demultiplexer 20. The demultiplexer 20 separates the multiplexed data into compressed video data and compressed audio data, and stores them in the video buffer 40 and the audio buffer 30, respectively. The compressed video data stored in the video buffer 40 is reproduced by the video decoder 90, and is externally output as video reproduction data. The compressed audio data stored in the audio buffer 30 is reproduced by the audio decoder 80, and is externally output as audio reproduction data.

The processing timing of the video decoder 90 and the audio decoder 80 is regulated by a sampling clock supplied directly from the CPU 10 or through a sampling clock correction unit 70. The demultiplexer 20 and the video buffer 40
The audio buffer 30 is controlled by the buffer control unit 50. The buffer control unit 50 is controlled by the CPU 10 and can instruct a predetermined interrupt to the interrupt control unit 70. That is, the synchronous control circuit of the present invention, in particular, the control means includes the CPU 10, the buffer control unit 50, the interrupt control unit 6
0, constituted by a sampling clock correction unit 70. The contents of control by this control means are as follows.

When data transfer requests from the video decoder 90 and the audio decoder 80 are sent to the buffer control unit 50, the buffer control unit 50
To the video decoder 90, and from the audio buffer 30 to the audio decoder 80. The video decoder 90 decodes and D / A converts the transferred encoded video data and outputs video reproduction data. The audio decoder 80 decodes and D / A converts the transferred encoded audio data, and outputs audio reproduction data.

The buffer controller 50 constantly monitors the remaining capacity of the audio buffer 30. When it detects that the remaining capacity of the audio buffer 30 has reached the upper limit for synchronizing the video reproduction data and the audio reproduction data, the buffer control unit 50 executes the splitting. Control unit 6
An interrupt is issued to the CPU 10 via the "0". CPU
The control unit 10 regards the interruption as a “delay” in decoding the audio data, controls the sampling clock correction unit 70 as interrupt processing, and optimizes the decoding rate of the audio data by increasing the sampling clock speed.

On the other hand, when it is detected that the storage remaining amount of the audio buffer 30 has reached the lower limit for synchronizing the video reproduction data and the audio reproduction data, the buffer control unit 50 also controls the interruption control unit. CPU 10 via 60
Interrupts The CPU 10 regards the interruption as “advance” of the decoding of the audio data, and executes the sampling clock correction unit 7 as interruption processing.
0 is controlled, and the decoding rate of audio data is optimized by reducing the sampling clock speed. The upper limit and the lower limit will be described later.

FIG. 2 shows an example of the configuration of the buffer control unit 50. As described above, the demultiplexer 20
Write video data to the video buffer 40 from
Reading of video data from the video buffer 40 to the video decoder 90 is performed according to a data transfer request from the video decoder 90. Demultiplexer 20
Before transferring the video data to the video buffer 40, the CPU 10 confirms that the video buffer 40 has a sufficient free space, and sets the initial value of the write address in the write address counter 52 via the timing controller 51. Thereafter, the write address is selected by the address selector 54. The writing (transfer) of the video data is performed by a data transfer request to the demultiplexer 20 under the control of the timing controller 51.

The CPU 10 reads the video data from the video buffer 40 by the timing controller 51.
After setting the initial value of the read address in the read address counter 53 via the address selector and selecting the read address by the address selector 54, the read address is controlled by the timing controller 51. The writing of audio data from the demultiplexer 20 to the audio buffer 30 and the reading of audio data from the audio buffer 30 to the audio decoder 80 are performed in the same manner as in the case of the video buffer.

FIG. 3 shows an example of the configuration of the interrupt control unit 60. Hereinafter, the operation of the interrupt control unit 60 will be described with reference to FIG. In FIG. 4, in order for the video reproduction output and the audio reproduction output to be synchronized, an upper limit value (see FIG.
(Point U in FIG. 4) and a lower limit (point L in FIG. 4). That is, the fact that more data is stored in the audio buffer 30 than necessary means that the decoding of the audio data is delayed, and conversely, if the data amount of the audio buffer 30 is too small, This means that decoding has progressed too much. The upper limit value and the lower limit value correspond to the data transfer speed from the video buffer 40 to the video decoder 90 and the audio buffer 30 respectively.
It is appropriately determined according to the data transfer speed from the video decoder 90 to the audio decoder 80, the sampling clock speed of the video decoder 90, and the sampling clock speed of the audio decoder 80. The determined upper limit is set in advance in the upper limit register 64 of FIG. 3, and the lower limit is set in advance in the lower limit register 65 of FIG.

Referring back to FIG. 3, the interrupt controller 60 counts the read signal and the write signal output from the buffer controller 50 to the audio buffer 30 by the read pulse counter 61 and the write pulse counter 62, respectively.
The remaining storage amount in the audio buffer 30 is obtained by subtracting the read pulse counter 61 from the value of the write pulse counter 62.
Is calculated by

The storage remaining amount in the audio buffer 30 obtained by the data storage amount calculating section 63 is equal to the upper limit value register 6
4 is constantly compared with the upper limit value set in advance in the comparator 66. If the data accumulation amount exceeds the upper limit value, a bit indicating that the data accumulation amount exceeds the upper limit value is set in the interrupt status register 69. At the same time as setting, an interrupt is requested to the CPU 10 via the OR circuit 68. Further, the data accumulation amount is constantly compared with the lower limit value preset in the lower limit value register 65 by the comparator 67. At the same time as setting the indicated bit, an interrupt is requested to the CPU 10 via the OR circuit 68.

When receiving an interrupt request from the interrupt control unit 60, the CPU 10 checks the interrupt status register 69 of the interrupt control unit 60 and determines whether the data stored in the audio data buffer has reached the upper limit or has reached the lower limit. It is determined whether it has been done.

FIG. 5 shows a sampling clock correction unit 70.
FIG. 3 is a block diagram showing a specific example of the configuration. If the data storage amount has reached the upper limit, the CPU 10 determines that the decoding process of the audio data is delayed, and increases the sampling clock speed of the audio decoder 80 to increase the decoding rate in order to increase the decoding rate. Set an appropriate value for. On the other hand, if the accumulated data amount has reached the lower limit, the CPU 10 determines that the audio data decoding process is in progress, and reduces the sampling clock speed of the audio decoder 80 to reduce the decoding rate in order to reduce the decoding rate. An appropriate value is set in converter 71.

An appropriate value set by the CPU 10 is converted into an analog quantity by a D / A converter 71 and input to a voltage-controlled crystal oscillator (VCXO, 72). VC receiving input from D / A converter 71
The XO 72 supplies a sampling clock having a frequency corresponding to the input signal to the audio decoder 80.

As described above, the synchronization control circuit according to the present embodiment provides a sampling clock and audio data for decoding video data in a system for decoding and reproducing compressed and multiplexed audio data and video data. Video reproduction output and audio generated when there is a deviation from the sampling clock for decoding video, or when the sampling clock for decoding video data and the sampling clock for decoding audio data are asynchronous. It is understood that it is possible to correct the synchronization deviation of the reproduction output.

Although the present invention has been described with reference to one embodiment, the present invention is not limited to this embodiment, and achieves the same object by similar circuits / means regardless of the difference in name. Needless to say, if possible, they are included in the scope of the present invention. For example, in the above embodiment, the buffer control unit 50 and the interrupt control unit 60 are represented as hardware, but these can be implemented as software in the CPU 10 to realize similar functions.

Further, in this embodiment, the speed of the sampling clock of the audio decoder is controlled to realize the synchronization of the video / audio reproduction output. However, the speed of the sampling clock of the video decoder may be controlled.
In this case, what is necessary is to change the speed of the sampling clock according to the amount of data stored in the video buffer.
It is obvious to a person skilled in the art. Further, it is also possible to change both the speed of the sampling clock of the audio decoder and the speed of the sampling clock of the video decoder.

[0026]

As is apparent from the above description, according to the present invention, it is possible to always correctly correct a synchronization shift between decoded data caused by asynchronously reading and decoding a plurality of compressed data from a buffer memory. There is a unique effect that can be done.

[Brief description of the drawings]

FIG. 1 is a block diagram of an example of a compression-multiplexed data decoding / reproduction system according to an embodiment of the present invention.

FIG. 2 is a block diagram of an example of a buffer control unit suitable for the present invention.

FIG. 3 is a block diagram illustrating an example of an interrupt control unit suitable for the present invention;

FIG. 4 is a diagram showing a data storage amount in an audio buffer according to the present invention.

FIG. 5 is a block diagram of an example of a sampling clock correction unit suitable for the present invention.

[Explanation of symbols]

 Reference Signs List 10 CPU 20 Demultiplexer 30 Audio buffer 40 Video buffer 50 Buffer control unit 60 Interrupt control unit 70 Sampling clock correction unit 80 Audio decoder 90 Video decoder

Claims (5)

[Claims] 1. While temporarily storing n (n is 1, 2,...) Kinds of compressed data in a buffer memory, reading out each compressed data from a corresponding buffer memory and asynchronously decoding the compressed data, A circuit used in a system having data decoding means for synchronously outputting the decoded data of the n types of compressed data, wherein the remaining amount of each of the n types of compressed data is monitored and the remaining amount of any of the compressed data is monitored. A control means for dynamically changing a decoding speed of the data decoding means based on the compressed data and controlling the remaining amount of storage toward the synchronizable range when the value deviates from a predetermined synchronizable range. A synchronization control circuit. 2. When the n types of compressed data include compressed video data and compressed audio data, the control means synchronously outputs at least decoded data of the compressed video data and compressed audio data from the data decoding means. 2. The synchronization control circuit according to claim 1, wherein 3. The synchronization control circuit according to claim 1, wherein said control means is configured to change a decoding speed of said data decoding means through a predetermined interrupt means. 4. The counting means for counting the number of times of writing and reading of data into and from the buffer memory for each compressed data, and the storage remaining amount for each piece of compressed data based on the result of counting by the counting means. A storage amount calculating means for calculating, a register for storing an upper limit value and a lower limit value of the synchronizable range, and a storage remaining amount of each compressed data reaches an upper limit value or a lower limit value in the register. 4. The synchronization control according to claim 3, further comprising: an output circuit that outputs an interrupt signal for interrupting processing to the data decoding unit together with a signal indicating the state of the remaining storage amount. circuit. 5. A system for demultiplexing compressed and multiplexed multiplexed data to separate it into compressed video data and compressed audio data, temporarily storing them in predetermined buffer memories, and then reading and decoding them. Monitoring the remaining storage amount of the compressed audio data, if the remaining storage amount is larger than a predetermined amount, increase the decoding speed of the audio data; if the remaining storage amount is smaller than the predetermined amount, A synchronization control method characterized in that the decoding speed of audio data is slowed to synchronize the output timings of decoded video data and audio data.