TW454421B - Decoding system - Google Patents

Abstract

The present invention is a decoding system for transferring a system stream multiplexing the video stream obtained by compressing and coding the video signal, a presentation time stamp, and a program clock reference for recovering the system time clock of the decoding system, to the CPU through a bus and processing it on the CPU. The entered system stream is stored in first buffer means, and is transferred to second buffer means through the bus. The system stream stored in the second buffer means is read out by the CPU and decoded. The capacity of the second buffer means is set so as to exceed the quantity of the system stream entered in a time necessary for arbitration of transfer requests in the bus. Moreover, the PCR input to the STC recovery means is delayed by the delay time from the output of a packet from a demodulator until arrival at the CPU.

Description

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5 4421 A7 __B7 _ 7. Description of the invention (1) 1. Scope of the invention: The invention relates to a decoding system for receiving compressed and packetized video and The audio stream is multiplexed by wireless or wired devices by MPEG or other encoding methods, or read and output video signals and audio signals from a storage medium. More specifically, it has techniques for synchronizing the output of the connotation of images and sounds. 2. Explanation of early techniques: A traditional decoding system is designed to receive at least one system stream from a video stream that is multiplexed, and this video stream uses MPEG2 or other video compression methods to indicate the time stamp (hereinafter PTS), and the program clock data (PCR) used to restore the system clock (STC) of the decoding system, obtained by compressing the video. According to the MPEG system standard, for such a multiplexed system stream, two streams are defined, that is, a transport stream and a program stream. As a representative example of the two, this transport stream is explained as follows: In the transport stream, in addition to the video stream pTs and PCR mentioned above, an audio stream obtained from compressed sound, a program specifies Information (PS!), Such as program information, business information (SI), and other additional information can be multiplexed. Since then, the stream is streamed to distribute them to the PCRs obtained. This stc is restored. Based on an STC, a decoding system for displaying a video obtained by decoding this multi-distributed video stream at a presentation time designated by PTS is disclosed, for example, in Japanese Patent Publication No. 9_ 七 纸Class applies to China's national sample; (CNS) Α4 · _ (210X297 male 褒 J-—------- installation ------ order -------- BU Λ (. '·--T ( Please read the precautions on the back before filling out this page) 4 5. The invention description printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (No. 2 307865). The device disclosed in this bulletin was intentionally implemented from This transport stream, the shoulder of STC, and the necessary data such as the video and audio on the hardware must be separated, and the software is used to process 1) 81 and 31 on this processor. This bulletin also discloses this device The structure in which the audio is decoded on the processor by the use of software. An example of a decoding system that implements this bulletin with a device installed on a personal computer is shown in FIG. 18 < * on page 18 'One input terminal 1, first-class demodulator 2, one packet demultiplexer 15, ST C restoration device 16 'The first bus interface device 3, the third buffer device 4, the video decoder 5, and an output terminal 6 are parts requiring high-speed processing, and are therefore implemented in hardware, and therefore connected A peripheral bus 7 to a personal computer serves as an add-on to the machine (so-called digital TV receiver). This peripheral bus 7, bridge 8, arbitration programmer 9, main bus 10, memory 11, fourth buffer The device 12 and the processor 13 form part of this personal computer. The second bus interface device 14, an audio provider 7, and an output terminal 18 are connected to the peripheral bus 7 of the personal computer as other internal additions (so-called Second card). The third bus interface device 25 is connected to the peripheral bus 7 and a hard disk drive (HDD) 26 on the personal computer. An operating system (0s) and a patent application software system are stored in the HDD 26, and This OS is read into this memory ^ The internal one has been passed from the HDD 26 through the third bus interface device 25 to the local paper standard (CNS > A4 specification < 21〇X 29 *) 7 mm) (please First read the notes on the back and then fill out this page), installed · -ordered-today 4 5 44 2: 1

Printed by the Intellectual Property Bureau's Consumer Cooperatives of the Ministry of Economic Affairs A7 B7 V. Description of the Invention (3) Machine 13 to operate 'and this patent application software such as psi / SI processing and audio decoding software operates on the OS. This operation is explained as follows: In FIG. 18, “a signal with error correction coding or modulation added to this transport stream is fed into the stream demodulator 2 through this input terminal 1”. The transport stream obtained by the demodulation or error correction of the router 2 is fed into the packet demultiplexer 15. The packet demultiplexer 15 separates pcR from the transport stream, and outputs the PCR to the STC reduction device 16. At the same time, an elementary stream (video PES) in which a PTS is multiplexed on a video data packet is separated, and it sends the video PES to the third buffer device 4. Other data are transferred from the first bus interface device 3 to the fourth buffer device 12 in the memory 11 by the path of the peripheral bus 7, the bridge 8, and the main bus 10. Here 'this fourth buffer device 12 is a packet receiving buffer having a size of 512 XN bytes, assuming that the number of units used to constitute this program is N' as described in the cited publication . The STC reduction device 16 restores the STC from the incoming PCR and outputs it to the video decoder 5. At the same time, it also outputs the peripheral bus 7, bridge 8 and main temperature bus 10 from the first bus interface device 3 to this process. Machine 13. This video decoder 5 decodes the video PES stored in the third buffer device 4 'regenerates this video data, transforms and processes it into a signal format suitable for rotation' and enters the STC from the STC restoration device 16 Based on this, the video signal is output to the output terminal 6 according to the time presented by the PTS separated from the video PES. The size of this paper is suitable. Use Chinese National Standard (CNS) Α4 size (210X297 male thin) ----------------- ~ tr ~ ------ `` '... (Please read the note on the back before filling in this page}

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 0 44 2 ^ A7 ___B7 V. Description of the invention (4) This processor 13 processes the PSI / SI stored in the fourth buffer device 12 and controls this according to these data The entire device. This processor 13 also decodes the audio PES stored in the fourth buffer device 12 and reproduced reproduced audio data, and based on the STC transferred from the STC restoration device 16 through the bus, according to the audio from this j > es The time presented by the separated PIS is transferred to the audio provider 17 by the path of the bridge 8, the peripheral bus 7 and the second bus interface device 14 ^ This audio provider i7 changes and processes the transfer The audio data becomes a signal format suitable for output, and the audio signal is output from this output terminal. The arbiter 9 is hardware for judging the transfer request among the bridge 8, the first bus interface device 3, the second bus interface device 14, and the third bus interface device 25. The peripheral bus 7, the bridge 8, the first bus interface device 3, the arbitration programmer 9, the second bus interface device 14, and the third bus interface device 25 may interconnect the PCI The building is thus composed (for example, "; details of the PCI bus and steps for supply", Public Design No. 7, CQ Publishing, 1995). In this conventional decoding system, although the packet demultiplexer 15 is implemented in hardware, the number of internal circuits added for this purpose is increased in number and it will cause high costs. Recently, the production volume of the microprocessor has been significantly enhanced, and it is fully possible for us to let this processor 13 use software for processing of the packet demultiplexer 15. However, to save costs, if the self-stream demodulator 2 transfers the transport stream to the processor 13 and try to use it as the program of the packet demultiplexer 15, the paper size is appropriate. Use Chinese National Standard (CNS) Α4 specifications (210X297 mm) (Please read the note on the back before filling in this page) l. Order 1 ^. 454421 A7 B7 V. Description of the invention (5) When it is on the processor 13, it is transmitted through the peripheral bus 7 Therefore, the time when the data packet of each transmission method reaches the processor 13 is unclear. It further causes the problem of instability of STC reduction due to fluctuations in the arrival time of the PCR. Due to the recurrence of video and audio on the basis of STC, if the value of STC becomes discontinuous due to the instability of STC restoration, the video or audio may not be continuously reproduced. It can also cause problems with the asynchronous presentation of video and audio content. In this peripheral bus, the transfer requests of several bus interface devices or bridges with a main bus function (hereinafter referred to as the main device) may overlap, and these requests are judged by the arbiter, but While one master device is being transferred, the other master devices must wait for the transfer. It therefore creates an irregular wait for the transfer of the transport stream to the processor. The personal computer may include, in addition to the construction mentioned above, a number of additional bus interfaces installed on other additives in the machine, such as the SCSI main socket and LAN card in this peripheral bus, and it further adds The ups and downs of the arrival time of PCR "Summary of the present invention: Therefore, the purpose of the present invention is to present a decoding system that has the ability to stably restore the STC by implementing decoding of the transport stream on the processor. To solve this problem, the present invention provides a decoding system for receiving at least one set of compressed and encoded video signals, a time stamp, and a program clock for restoring the system timing clock of the decoding system. One of the video streams and one system stream obtained from the data includes a first buffer device to store and output the incoming system stream. A bus has a paper size that applies the Chinese National Standard (CNS) A4 specification (210X297 mm) ) (Please read the notes on the back before filling this page) l. Order printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -8-b 44 2 1 A7 B7 V. Description of the invention (6) (Please read the notes on the back first Please fill in this page again) to transfer data and a control signal, an arbiter to determine the transfer request from the device connected to this bus, and a second buffer device to receive through this bus The output from the first buffer device is stored and a processor is used to decode the system stream stored in the second buffer device and output the necessary video stream and time scale , Extract the program clock data, and restore and output the system timing clock, and a video decoder to receive the video stream, time stamp and system timing clock output from this processor, based on the system timing clock Decode the video stream and output the decoded video at the time represented by the time stamp, where the energy of the second buffer device is set to be less than the time used for the judgment of the transfer request in the bus The energy of the incoming system flow is greater. More suitably, the arbiter is designed to cut off the transfer when one of a plurality of devices is transferred for a specific maximum transfer time, and the energy of the second buffer device is set Becomes greater than the number of devices that can be connected to this bus multiplied by the product of the longest transfer time and the data flow rate of the system stream. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The energy of the second buffer device can be variably set by this processor. This processor detects the device that requires the judgment of the transfer request in the bus, and the second The energy of the buffer device is set to be greater than the number of devices requesting the transfer request multiplied by the product of the maximum transfer time of each device and the data flow rate of the system stream. More appropriately, the arbitration procedure is designed to output to the processor the data of the device in the bus that requests the determination of the transfer request. This paper size applies to China National Standard (CNS) 8-4 specifications (2 丨 0X297 mm) -0-b 44 2 A7 B7 V. Description of the invention (7)

The present invention also provides a decoding system for receiving at least one group of compressed and encoded video signals from a multiplex transmission, a time stamp, and program clock data used to restore the system clock of the decoding system. A system streamer of a video stream includes a first buffer device to store and output the incoming system stream, a bus to transfer data and a control signal, and an arbiter to determine whether it is connected to the bus. The transfer request of the row device, the second buffer device is used to receive and store the output of the first buffer device through this bus, and a processor is used to decode the system stream stored in the first buffer device. , Output the necessary video stream and time stamp 'extract program clock data, and restore and output this system timing clock' and a video decoder to receive the video stream 'time stamp and system timing clock output from this processor Decode this video stream based on the system timing clock and output this decoded video at the time represented by the time stamp ' The processor detects the remaining data of the second buffer device and controls the arbiter, so that the transfer of the system flow from the first buffer device to the second buffer device can make a transfer request on the bus Judgment is given first over the rest of the data into a more specific amount for the hour. The present invention also provides a decoding system for receiving at least one set of boring and partial code_video signals, a time stamp, and program clock data used to restore the system clock of the decoding system. A video stream and a system stream, including a first buffer device for storing and outputting the incoming system stream, a bus for transferring data and a control signal, and an arbiter for determining the The transfer request of the device connected to this bus, the second buffer device 'through this bus is used to connect the paper size to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back first (Fill in this page again.) Order Printed by the Intellectual Property Bureau Employee Consumer Cooperatives of the Ministry of Economic Affairs 10 4 5 44 2

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ______________ B7 V. Invention Description (8) The output of the first buffer device is received and stored, a first clock generator is used to generate a clock of a specific frequency, a first A counter for generating a master clock, as the system timing clock of the first clock generator has changed in the same period since then, and fed into a processor, and a processor for decoding and storing in a second buffer device System stream, output the necessary video stream and time stamp, extract the program clock data and restore and rotate the system timing clock, and a video decoder to receive the video stream 'time stamp output from this processor And the system timing clock, decode the video stream based on the system timing clock, and output the decoded video at the time represented by the time stamp, where the processor restores this by storing the difference between the program clock data and the main clock The system timing clock β is more appropriate, the processor detects whether the second buffer device is vacated or not, and Stop clock difference update data and the master clock to a specific time of the fruit vacated. More appropriately, this processor controls the arbiter, so that the output of the first-buffer device is transferred to the second buffer setting, either immediately after the start of decoding or immediately after the change of the stream to be decoded. Give priority to the transfer request of the bus. More appropriately, the processor restores the system timing clock by using the average of the difference between the program clock data and the master clock for a specific number of times. The present invention also provides a decoding system for receiving at least one video signal derived from compression and partial code borrowing, a time stamp, and program clock data used to restore the system clock of the decoding system. A system stream of a video stream 'includes a first buffer device to store the paper size applicable to China National Standards (CNS > Α4 size (210X297 mm) (谙 Please read the precautions on the back before filling this page) Ή Installation-order _ 11 A7 ______B7_ 5. Description of the invention (9) and output the incoming system flow, a program clock data multiplexer, used to separate the program clock data from the incoming system flow, and output to the delay device The delay device is used to delay the program clock data from the program clock data multiplexer and output it to the system timing clock restoration device. The system clock restoration device 'uses the program clock data of the self-delay device to restore the system. Timing clock, a bus, used to transfer data and a control signal 'an arbiter' is used to connect to the bus itself The device judges the transfer request, and the second buffer device is used to receive the output of the first buffer device and store it through the bus, a first clock generator for generating a clock with a specific frequency, and a first counter. Is used to generate a master clock, as the system timing clock of the first clock generator has changed in the same period since then, and fed into a processor, a processor is used to decode the data stored in the second buffer device. System stream, output the necessary video stream and time stamp §, extract the program clock data, and calculate the difference between the first master clock as a differential system timing clock and a video decoder to receive from this processor The output video stream and time stamp, and the system time clock output from the system clock restoration device, decode this video stream based on the system time clock, and output this decoded time at the time represented by this time stamp The frequency β is more appropriate. The processor detects when the second buffer device becomes empty, and sets the delay time of the delay device. The system timing clock restoration function of the system timing clock restoration device is started. The present invention also provides a decoding system for receiving at least one group of multiplexed and encoded video signals, a time stamp, and the paper U Applicable to the Chinese standard rate (阙) (plus 7 male sauce) (Please read the precautions on the back before filling out this page)-Order printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economy 12 4544 2 ^ A7 _______B7_ V. Description of the invention ( 10) A system stream of a video stream obtained by restoring the program clock data of the system timing clock of the decoding system includes a first buffer device for storing and outputting the incoming system stream. Way distributor, used to separate the program clock data from the incoming system stream and output it to the clock restoration device 'clock restoration device, using the program clock data from the program clock data multiplexer' to restore the clock, a bus, Used to transfer data and a control signal 'An arbiter is used to judge the transfer of the device connected to the culvert. A second buffer device is used to receive the output of the first buffer device through the bus and store it. A first clock generator is used to generate a clock with a specific frequency. A first counter is used to generate A first master clock 'is the same as the system timing clock from the first clock generator, and is fed into a processor in this same period. The processor is used to decode the system stored in the second buffer device. Stream, output the necessary video stream and time stamp, extract the program clock data, and restore and output the system timing clock, and a video decoder that operates on the clock of the self-clock recovery device 'is received by the processor through the bus The output of this video stream 'time stamp and system timing clock, decode this video stream based on the system timing clock' and output this decoded video at the time represented by the time stamp. More appropriately, the processor transfers the system timing clock to the video decoder after the system timing clock output stops all transfer command output to other devices, and cancels other transfer commands after the system timing clock transfer is terminated. stop. The present invention also provides a decoding system * for receiving multiple transmissions of at least one piece of paper, so it will be transferred from Long Jin Guan Jia (CNS) 彳 4 inspections (21GX297 mm) (Please read the precautions on the back before filling this page)-Order 4 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 13 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ____B7__ V. Description of the Invention (U) Compressed and coded a video signal, a time stamp, and used for restoration A system stream of a video stream obtained from the program clock data of the system timing clock of the decoding system includes a first buffer device for storing and outputting the incoming system stream, a bus for transferring data and a A control signal, an arbiter, for judging a transfer request from a device connected to the bus; a second buffer device for receiving the output of the first buffer device through the bus and storing it; The first clock generator is used to generate a clock with a specific frequency, and a first counter is used to generate a first master clock, as is the case from the first clock generator. The timing clock changes during the same period. A processor is used to decode the system stream stored in the second buffer device, 'output the necessary video stream and time stamp, extract the program clock data', and calculate the difference from the first master clock. As a differential system timing clock, it is output to an adder through the bus, and a second counter is used to generate a second master clock. In this way, the system timing clock is changed in the same period and fed to an adder. An adder for obtaining the sum of the differential system timing clock from the second main clock output of the second counter and the output from the processor, and feeding it as a system timing clock to a video decoder and a video Decoder for receiving the video stream and time stamp output from the processor and the system timing clock output from this adder based on the system timing clock to decode this video stream and the time represented by the time stamp Output this decoded video. More appropriately, the first main clock from the first counter is immediately after the power is connected, or immediately after setting the processor, and after stopping all data transfer through this bus, it is transferred to the second counter. This paper is in compliance with Chinese national standards (called eight 4 threats (210 fathers, 297 public envy) * (please read the precautions on the back before filling out this page). Binding-Ί4 A7 B7 Staff Consumption of Intellectual Property, Ministry of Economic Affairs Printed by the cooperative ^ 54421 V. Description of the invention (12) ^ --- 俾 This second master clock may be so that the first master clock is almost the same value. More suitably, this processor controls the arbiter, 俾The transfer of the first master clock from the first-counter to the second counter can be assigned the first priority in the judgment of the transfer request of the bus, and the master clock of the first counter has been transferred to the second counter since then. Make the second master clock almost the same value as the first master clock. More appropriately, the reset signal of this bus is immediately after the power is connected, or immediately after the bus is reset. Into the first counter and the second counter, and by using it, the first master clock and the second master clock are set to almost equal values. More suitably, it also includes a second clock generator for Generate a clock of the same frequency as the frequency of the first clock generator and output it to the second counter. More suitably, the bus uses the clock output from the first clock generator as the transfer clock of the bus, and this The second counter receives the transfer clock of the bus and generates a second master clock. More suitably, it further includes a selector to store a differential system timing clock output from this processor between a specific number and select storage One of the minimum values of the differential system timing clock is output to the adder. More appropriately, this processor controls the arbiter, so that the transfer of the differential system timing clock to the adder can be performed on the transfer request of the bus. The first priority is given to judgment. The present invention also provides a decoding system for receiving at least one of the multiplexed transmission, but by borrowing compression and encoding a video No, a presentation time stamp, paper scales applicable to this Chinese National Standard (CNS) A4 existing grid (210X297 mm > (Please read the Notes on the back to fill out this page)

15 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (13) and a system stream of a video stream obtained from the program clock data of the system clock, which includes the first. Buffer device to store and output the incoming system stream, a bus to transfer data and a control signal, an arbiter to determine the transfer request of the device connected to this bus, second A buffer device for receiving and storing the output of the first buffer through the bus, a first clock generator for generating a clock of a specific frequency, a first counter for generating a first The master clock, as changed from the same period of the system timing clock of the first clock generator, and fed into a processor, a processor to decode the system stream stored in the second buffer device, the output must be Video stream and time stamp, extract the program clock data, calculate the difference from the first master clock to obtain a differential system timing clock, and calculate the decoding time Record the difference between the timing clock of the differential system and obtain the corrected time stamp, and output the corrected time stamp together with the necessary video stream to the third buffer device, the third buffer device. To receive and store the video stream and the corrected time stamp output from the processor through this bus, a second counter is used to generate a second master clock, so that the system timing clock changes in the same period and feeds To—video decoder 'and a video decoder for receiving the second master clock rotated from the second counter, decoding the video stream stored in the third buffer device' and marking the time stamp at the time corrected thereby. This decoded video is output at the time of presentation. In this structure, according to the present invention, since the energy of the second buffer | depends on the devices connected to the bus itself, each device itself applies the Chinese National Standard (CNS) A4 specification (210X297) %) -------------------- ^ *; \ (Please read the note on the back before filling in this page} 5 442 ^ A7 B7 V. Description of the invention (14) Depending on the number of master devices that control the bus for transfer, and this time until the arbiter program forcibly cuts off the transfer by urging the master device to transfer (known as stopping operation). When transferring this incoming system flow to the second buffer device, we may avoid the phenomenon of unstable restoration of STC due to the effect of the judgment of the bus. This processor controls the delay device to change the delay time and control this The STC restoration device is used to set the STC restoration function, so that the video and audio can be stably synchronized. By transferring the STC value restored by this processor to the video decoder, the delay device can be omitted, and we do not need to calculate Delay time in the delay device, This setting is set by the processor, and the video and audio can be synchronized by this small hardening. If an underflow occurs in the second buffer device, by combining one of the methods to reduce the impact on STC restoration, This STC can be restored stably even if it is in the constitution of reducing the energy of the second buffer device. By installing a second counter, a master clock system is also generated on the side of the additions in the machine, and uses between the master clock and the STC The difference of the DSTC is transferred from the processor. This video decoder has the STC restored by the adder, and further chooses to use one of the minimum delays due to the judgment in the middle of the value sent by DSTC. The influence of the judgment of the bus on the transfer of the STC can be reduced. In addition, the processor controls the arbiter when the DSTC is transferred, and by improving the priority of the temporary transfer of the DSTC, the STC transfer is on the bus. The impact of the judgment can be further reduced. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling in this )

Printed by tT of the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives -17-4 5 44 2 1 A7 ____B7__ V. Description of Invention (15) In this constitution, 'where this master clock is directly placed in the video decoder', instead of separately Send this DSTC to the video decoder to send the PTS range of the original video PES, in the format replaced by the corrected PTS (PTS-DSTC), through this third buffer device to the video decoder, from the bus The effect of the judged DSTC can be absorbed in the third buffer device, and the decoding operation based on the shared STC can be accurately performed between the processor and the video decoder. In addition, 'by using the output clock of the first clock generator in the main clock used to drive the bus, and using this clock in the input to the second counter, the frequency of the main clock output from the first counter and the The frequency of the main clock output by the second counter can be correctly matched, and the synchronization of the processor and the video decoder can be stably completed by STC. Borrowing the reset signal of the bus to the first counter and the second counter 'This bus is reset, and this second counter and the first counter are reset' and the reset of the bus is clear, and counts It starts at the same time 'and therefore I don't have to come to transfer the value of the first counter to the second counter' and ';! The influence of the judgment of the flow can be completely avoided. As a result, the decoder of this system stream can be replaced by a processor on a personal computer ', which will produce a significant effect of reducing the cost of internal additives for the decoding of digital video. Brief description of the drawings: Fig. 1 is a block diagram showing the structure of a decoding system in the first embodiment of the present invention. The second line is the size of the paper transmitted on a processor 13 in the first embodiment of the present invention. The size of the paper applies to the Chinese National Standard (CNS) M specification (210X297 mm) -1J? --------- Ί — ---(Read the notes on the back to read the first page and fill in this page) Order-Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Α7 Β7 V. Description of the invention () Schematic flow chart of the software. Figure 3 is a concept circle 'used to explain the cycle-first ordering algorithm. (Please read the precautions on the back before filling this page) Figure 4 is a block diagram showing the structure of a decoding system in the second embodiment of the present invention * Figure 5 is a conceptual diagram for explaining the STC restoration value Break. Fig. 6 is a schematic flowchart showing an example of transmitting decoder software on the internal processor 13 of the second embodiment of the present invention. Figure 7 is a conceptual diagram explaining the improvement in the interruption of the STC restore value. FIG. 8 is a flowchart of a DSTC calculation procedure in the case of reduction of STC by using the average of the seven largest PCR inputs. Order

Fig. 9 is a conceptual diagram showing the STC obtained by averaging this DSTC. Fig. 10 is a block diagram showing the structure of a decoding system in the third embodiment of the present invention. Fig. 11 is a schematic diagram showing an example of the boot sequence of the decoding system in the third embodiment of the present invention. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Figure 12 is a schematic flowchart of transmitting decoder software on a processor 13 in the third embodiment of the present invention. Fig. 13 is a block diagram showing the structure of a decoding system in a fourth embodiment of the present invention. Fig. 14 is a schematic flow chart of software for a decoder of a wheel on a processor 13 in a fourth embodiment of the present invention. Figure 15 is a conceptual diagram explaining the video decoder 5 and the 19th 4 5 44 2 A7 B7 of the present invention. Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (1?) Possibility of STC synchronization decoding operation. Fig. 16 is a block diagram showing the structure of a decoding system in the fifth embodiment of the delivery month. Fig. 17 is a block diagram showing the structure of a decoding system in the sixth embodiment of the present month. Fig. 18 is a block diagram showing a description of a preferred embodiment of a conventional decoding system: The decoding systems of the first to sixth embodiments of the present invention are described below, while referring to Figs. < First Embodiment > The first embodiment of the present invention will be described below with reference to the first embodiment. The common parts with those of the earlier technique in Figure 18 are identified by the same reference code. Fig. 1 is a block diagram showing the construction of a decoding system in the first embodiment of the present invention. In the first figure, a round-in terminal, a first-stage demodulator 2, a first bus interface device 3, a second buffer device 4, a video decoder 5, an output terminal 6, a first buffer device 27, A pCR demultiplexer, delay device 37, and STC reduction device 38 are the parts that need high-speed processing, and are therefore implemented on the hardware, and therefore connected to a peripheral bus connected to a personal computer as an add-in board ( (The so-called digital TV receiver board). Peripheral bus 7, bridge 8, arbitrator 9, main bus, memory 11, processor 13, first counter 22, first clock generator 23, and second buffer device 24 form a personal computer Part of it. This paper uses the Chinese National Standard (CNS) A4 (21 × 297 mm) (please read the precautions on the back before filling this page)

20 45442 ^ A7 B7 V. Description of the invention (18) The second bus interface device 14, an audio provider 17, and an output terminal 18 are connected to the peripheral bus of the personal computer as other add-in boards (so-called sound cards) . The third bus interface device 25 connects the peripheral bus 7 and an HDD 26. An OS and an application software system are stored in the HDD 26, and the OS is read into the memory 11 and is operated by the processor 13 from the HDD 26 through the third bus interface device 25, and the application software such as transmission Decoder software, operate on this 0S "This operation is explained as follows: In Figure 1, there is an error correction bias code or modulation added to the multiplexed signal of at least one set of transport streams from a video stream, by compressing this The video is fed into the stream demodulator 2 through the input terminal 1 by using MPEG2 or other video compression methods, PTS > and PCR to restore STC. The transport stream obtained by processing the input signal by the demodulator 2 with demodulation, error correction, or similar operations is stored in the first buffer device 27 once, and is passed through the first bus interface device 3, The peripheral bus 7, the bridge 8, and the main bus 10 are transferred to the second buffer device 24 in the memory 11. The first buffer means 27 is to accumulate the transport stream when it is caused to wait for the transfer of the transport stream commanded by the arbiter 9. The arbiter 9 is used to adjust the transfer requester from the peripheral bus 7. The transport stream stored in the second buffer device 24 is separated by the processor 13 into video PES and audio PES to be reproduced. PSI / SI, and PCR. Here, the processing of the audio PES and PSI / SI is the same as the earlier paper standard that applies the Chinese solid standard (CNS) A4 specification (210X 297 mm) --------- y installation-(please first Read the notes on the back and fill in this page) Order printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -71-4 5 442 ^ A7 B7 V. Description of Invention (19) The method in the technique is the same, and its explanation is omitted, And the processing of video PES and PCR are described in detail below. (Please read the precautions on the back before filling this page.) Using the clock generated by the first clock generator 23, this first counter 22 generates a master clock, which is the same as the time reference used for the operation of this decoding system. Here, this master clock is the time reference value as if the PCR and STC were in some bits and during the update period. Incidentally, the update period of the master clock and the period of the clock generated by the first clock generator 23 are not always required to overlap each other. The processor 13 returns the STC by using the separated PCR and master clock. Here, the restored STC is used inside the processor 13 to decode audio PES, or to control the entire device on the basis of PSI / ST. The processor 13 decodes the transport stream and transfers the separated video PES to the third buffer device 4 via the path of the main bus 10, the bridge 8, the peripheral bus 7, and the first bus interface device 3. Referring now to Fig. 2, the decoding process of the transport stream of the processor 13 is explained as follows: Fig. 2 shows an example of a schematic flow of transmitting and decoding software on the processor 13. Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs at step 201, the decoding process of the transport stream is started, and the transport stream stored in the second buffer device 24 is from the start of one data packet to another. It is read into the processor 13 (step 202). The processor 13 analyzes the header of the read data packet, determines the content of the data packet (step 203), and executes a series of processing (steps 204 to 208) according to the data determined by the judgment result, and reads the next The data packet is one packet after step 209. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -22-4 6 4421 A7 B7 V. The processing of part (20) of the invention description has passed (step 202 ). When the content of the read data packet is the PCR to be decoded (step 203), the difference between the master clock and the PCR value output from the first counter 22 is retained in a specific address on the memory 11 as this DSTC value (step 204). Thereafter, in this MPEG transport stream, since PCR and video data may be contained in the same packet, we judge whether this video data is included in the payload of the PSI packet and the header of the packet (step 205), and when the video data is presented, this operation is transferred to the processing of the video data (step 206), and if not present, the processing of this packet is terminated to move to step 209, if it is being read When the content of the incoming data packet is the decoder of the video PES (step 203), the video PES in this data packet is transferred to the third buffer device 4 (step 206). If the content of the data packet being read is SPI / SI or audio data to be decoded (step 203), it is reserved in a specific area on the memory 11 (step 207), and it is not required In the case of other data packets, no action is taken and the operation proceeds to step 209. When the processing of each data packet is terminated, the DSTC retained in the memory 11 is read out, and at the same time it is added to the value of the first counter 22 to obtain the STC value, which is software for decoding audio PES or Similar. Returning to FIG. 1, the PCR splitter / distributor 36 receives the transport stream output from the stream demodulator 2, separates the PCR, and outputs it to the delay device 37. When the output self-stream demodulator 2 of the self-packet has entered the processor 13, until it passes through the first buffer device 27, the first bus interface device, the paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 (Mm) (Please read the notes on the back before filling out this page) / Binding. Order-Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-23-4 5 44 21 A7 B7 V. Description of Invention (21) 3, Peripheral When the bus 7, the bridge 8, and the second buffer device 24 are fed with the delay time until the STC reduction device 38, the delay device 37 delays the separated PCR at the same time. Here, this delay time is the delay time to be set in the delay device 37, that is, the total number of transport streams stored in the first buffer device 37 and the second buffer device 24 divided by the data speed. That is the amount of data transmitted per unit time of the transport stream when the self-stream demodulator 2 outputs it. Our industry is designed to absorb the fluctuation of the transfer time from the first bus interface device 3 to the first buffer device 27 and the second buffer device 24 to transmit through the bridge 8 and stored in the first buffer The total amount of transmission streams of the device 27 and the second buffer device 24 (that is, from the input into the first buffer device 27 to the output from the second buffer device 24) is always the same value. When the energy system of the second buffer device 24 has been determined and designed, this value is automatically determined, and it can be set as a fixed value in the delay setting 37. The STC restoration device 38 restores the B clock and STC value from the incoming PCR, and feeds them to the video decoder 5. This video decoder 5 is a decoder that complies with the MPEG 2 standard capability of decoding video PES. On the inside, the decoder incorporates the function of displaying images together with time, and uses the STC counter and PTS extracted from the video PES to form the video PES. In this STC counter, the STC value transferred from the outside is set, and thereafter it is counted at 90KHz. This video decoder 5 decodes the video PES stored in the third buffer device 4 and then generates moving image data, transforms and processes it into the paper size applicable to the output. The applicable Chinese National Standard (CNS) A4 specification (210X297 mm) ) (Please read the notes on the back before filling this page)-Order d Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics-24-4 5 44 2 1 Α7 Β7 V. Description of the invention (22) A signal format, and On the basis of the STC entered from the STC restoration device 38, this recurring moving image signal is output to the output terminal 6 according to the time presented by the PTS separated from the video PES. »According to the structure described herein, we may borrow The processor 13 decodes the transport stream. The PCK demultiplexer 36 only analyzes the transmission header and sends this PCR only to the delay block 37. At the same time, when compared with the packet demultiplexer 15 in FIG. 18, it is in the simpler hardware Medium to achieve. The following is an explanation, that is, if the transfer of the PCR from the demodulator 2 to the second buffer device 24 is delayed due to the judgment of the peripheral bus, the influence on the STC restored by the processor 13 is prevented. The arbiter 9 operates in a loop-first ordering operation with obsolescence. The conceptual diagram of the loop prioritization operation is shown in Figure 3. Here, the main device is connected to the peripheral bus 7 (all integrated circuits on the add-in board and the motherboard, and the bridge circuit). There is a function to control the peripheral bus 7 to be transferred by itself. One of Pei Zhi. If multiple master devices are presented on the same bus, and they individually request the transfer to control this peripheral bus 7, we need to judge the transfer among all the devices requesting transfer. The first bus interface device 3 is assumed to be the master device a. When a transmission stream is output from the stream demodulator 2, the host device 8 requests it to be transferred to the second buffer device 24 to the arbiter programmer 9. According to the instruction from the processor 13, this master device A also requested to transfer the video pES stored in the memory to the third buffer device 4 to the arbiter 9 9 This bridge 8 is assumed to be the master device B . When it is necessary to issue a control paper, the paper size is applicable to the Chinese National Standard (CNS) Α4 specification (210X297 public epidemic) ---------- Λ. * I (Please read the precautions on the back before filling in this Page), τ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 75 454421 A7 B7 V. Description of the invention (23) When the processor 13 is used to control other words, the main device B outputs a transfer request of a control command To the arbitration procedure 9. The second bus interface device 14 is assumed to be the master device c. According to the instruction from the processor 13, the master device C outputs the transfer request of the audio data stored in the memory u into the audio provider 17 to the arbiter. Programmer 9: This third bus interface device 25 is assumed to be the master device. When a file approaches HDD 26, the master device d outputs a transfer request to the memory. U to the arbiter programmer 9 . Among these four master devices, if multiple master devices including the master device A issue a transfer request at the same time, the arbiter 9 first receives the transfer request from the autonomous device A, assuming that the master device a has the highest When priority is given, the master device B has the second priority, the master device c has the third priority, and the master device D has the lowest priority. The arbiter 9 performs the transfer operation of the master device A to a specific time Ta 'and is forced to terminate the transfer. This forced action to terminate this transfer is called latent time, and the duration from the beginning of the transfer until the occurrence of the latent action is called the latent period (herein Ta). At this moment, when the arbiter programmer 9 loops this priority order, and when the host device A is assumed to have the lowest priority, the host device b is the highest priority, and the host device C is the second priority, and the host device A is the second priority. Device D has the third priority. Therefore, multiple master devices including to device B request a transfer at the same time. At this moment, the main device B is assumed to have the highest priority and its paper size applies the Chinese National Standard (CNS) A4 specification (210X297 cm) --------- 3 packs-" π ' · '·' (Please read the note on the back before filling this page) Order printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 26 454421 A7 B7 V. Description of the invention (24) The transfer request is accepted, and when the transfer action After a specified time Tb, the transfer is postponed. (Please read the notes on the back before filling this page.) After that, similarly, the main device C is assumed to have the highest priority, and the transfer is operated to a specific time Tc, and the transfer is terminated. Then, similarly, the master device D is assumed to have the highest priority, and the transfer is operated to a specific time Td, and the transfer is forced to terminate. By using this arbiter programmer 9 it operates in this way, the transfer of the stream demodulator 2 to the second buffer device 24 is caused to wait for a transfer request of the longest time (Tb + Tc + Td) until The migration of the main device B, the main device C, and the main device D has passed. This holding period (Tb + Tc + Td) is the time required to judge the transfer request of the bus. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Assuming that the data speed or the amount of data transferred per unit time of the transport stream output by the stream demodulator 2 is R bytes per second, the second buffer is defined by The energy of the device 24 is greater than (Tb + Tc + Td) xR bytes than the energy of the fourth buffer device 12 in FIG. 18. The energy of the second buffer device 24 can be set to be more than that used for the peripheral bus 7. The energy of the incoming transport stream during the time necessary for the judgment of the internal transfer request is large. Therefore, this transport stream can be continuously read into the processor 13 at this data speed R, so that the restoration operation of the STC is stable. At this time, because we need to start in the state energy waiting to be transferred by Tb + Tc + Td Therefore, the processor 13 must start after the detection data is stored in the second buffer device 24 with (Tb + Tc + Td) XR bytes. This paper size applies the Chinese national standard (CNS > A4 specification (210X297) -97. 4 5 44 2 1 A7 B7 V. Explanation of the invention (25) Decoding (Please read the notes on the back before filling out this page) Actually, as one of the methods of constructing this decoding system, it is assumed that the arbitration The longest time in program 9 until the latent time is Tmax, the total number of devices connected to the peripheral bus 7 (slots for adding cards, integrated circuits on the board connected to this bus, and bridges That is, the maximum number of main devices) is Na, the data speed of the transport stream output from the stream demodulator 2 is R bytes / second, and the maximum number of processing elements of the program constituting the transport stream to be entered is Nmax, Setting the second buffer device 2 The method of energy of 4 becomes greater than

The Tmax X Nax X R + 5 12 X Nmax bytes are explained as follows: Immediately after starting the flowchart of transmitting the decoding software shown in Figure 2, the remaining stream data in the second buffer 24 is detected. Tmax X Na XR bytes are inserted by this program to proceed to the next step. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs At this moment, it is unknown whether a master device is connected to a slot for adding a board, or a target device does not have such functions such as controlling peripheral buses by itself The 7 is connected (or it may be changed in the future), and therefore at the moment when this decoding system is constructed, a sufficient amount of energy can be used to set the second buffer by using the total number of devices Nc that can be connected to this bus Alternatively, it may be designed to set the energy of the second buffer device 24 from the processor 13. When the OS detects hardware data, the number of master devices that need to be judged by the transfer request is detected in the middle of the devices that are actually connected to the peripheral bus 7, and the processor 13 is actually used to measure the masters. The number of devices is set according to the calculation result. Since the paper size of the main device presented uses the Chinese National Standard (CNS) M specification (210X297 mm) 4 5 44 2 1 A7 B7 V. Description of the invention (26) The number is limited, so the second buffer prize is a small scale The energy of the device 24 can be substantially reduced. Incidentally, the structure for setting the energy of the second buffer device 24 from the processing machine 13 can also be realized as follows. For example, a register showing the energy of the first coin-buffer device 24 is installed in the first bus interface device. c Odd 'stolen value is set by processor 13. The write indicator value used to write in the second buffer device% is controlled by the bus interface device based on the value of this register. The reading indicator value for reading from the second buffer device 24 is directly controlled by the processor 13. At this time, the indicator value is written to the register display by providing the first bus interface device to The second buffer device 24, and the remaining transport stream data in the second buffer device 24 can be measured by the processor 3. By using this structure for detecting the rest of the transport stream, several functions can be realized, and the details are described later in this embodiment. The Consumer Cooperatives of the Intellectual Property Office of the Ministry of Economic Affairs printed as described in this article, according to the browning system of the first embodiment, set the number The energy of the second buffer device 24 may prevent the unstable instability of the STC caused by the influence of the judgment of the peripheral bus 7 when transferring the auto demodulator 2 to the second buffer device 24. In this structure t, the input to the processor 13 is continuously completed, and therefore the data packet of the auto demodulator 2 needs to reach the processor 13 normally, and according to this time, the delay device 17 The delay time can be set. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 00 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 454421 A7 ______B7 V. Description of the invention (27) Self-processing machine 13 detects the second buffer device 24 The method of the remaining transport stream data has been explained above, and in addition, in a similar method, by detecting the remaining transport stream data in the first buffer device 27, we can also calculate the delay to be processed by the processor 13 The delay time set in the device 37. Here, as a detection method for the remaining data, the processor 3 directly controls the value of the read indicator of the second buffer device 24, and the first bus interface device 3 is provided with a register to display the The write-out indicator value of the second buffer device 24, and therefore, the processor 13 reads the indicator value and the write-out indicator value from this to detect the remaining transport stream data in the second buffer device 24. The first buffer device 27 is also equipped with a register to display the read indicator and the write indicator value, and to make the processor 13 readable by the first bus interface device 3, the processor 13 That is, the remaining transport stream data in the first buffer device 27 can be confirmed. In the second buffer device 24, when the remaining data in the buffer becomes zero, the arrival time of the next PCR to the processor 13 is delayed, and therefore, the PCR is at a different timing from the STC restoration enter. At this moment, the zero residual of data means that the amount of data stored in the second buffer device 24 in the traditional buffer control is small, and we must change the second buffer by the processor 13 The reading control of the data of the buffer device 24 allows the average remaining of the second buffer device 24 to be larger, and therefore the required delay time in the delay device 37 is changed.

Accordingly, the processor 13 controls the delay device 37 to change the delay time, and controls the STC restoration device 38 to set the STC restoration action again. This has been repeatedly set, this STC reduction action has been terminated, but this is because the PCR entered the STC The paper size is appropriate. Use Chinese National Standard (CNS) A4 specifications (210X297 mm) ~ -_ (Please read the back Note #Fill in this page)

454421 A7 ____B7 V. Description of the invention (28) The input time in the reduction device 38 is changed due to the change in the delay time ', and this repeated setting is intended to terminate the current STC restoration operation once and start again from the beginning. With this operation, the video and audio can be optimally synchronized according to the STC restoration action when the delay is changed. "In the calculation of the arbiter 9, the first bus interface device 3 (that is, the main Device A) can often give the highest priority. In this method, the arbiter programmer 9 can be composed in a simple circuit, but only by referring to this method, the transfer amount of other master devices is reduced and the output video or audio may be disturbed or other inconveniences may occur. . In this embodiment, the use of a circular prioritization operation with latent time, and the determination of the buffer energy according to this, will not cause such an inconvenient decoding system to be presented. < Second Embodiment > Fig. 4 is a block diagram showing the structure of a decoding system in the second embodiment of the present invention. In Fig. 4, the same parts as those in the first embodiment of Fig. 1 are denoted by the same reference numerals, and repeated explanations are omitted. The difference between the second embodiment and the first embodiment is that the STC value restored by the processor 13 is transferred to the video decoder 5, and the delay device is thus cleared. By transferring the STC value restored by the processor 13 to the video decoder 5, the STC restoration device 38 requires only the function of feeding only the words into the video decoder 5, and it does not require the restoration of an accurate stc value. Therefore, 'this delay device 37 cannot be removed. At the same time, the processor 13 does not need to calculate and set the delay time in the delay device 37 here. On the other hand, when transferring 37 (restored by the processor 13 to the video's paper size) (CWS 2] GX297 public meal) --- -_ {Please read the precautions on the back before reading (Fill in this page)-Install-'Order printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 45 44 2 1 A7 ___B7 V. Description of the invention (29) When the decoder 5 is transferred through this peripheral bus 7, and therefore The input time of the STC value in the video decoder 5 is affected by the judgment of the peripheral bus 7. Therefore, in the decoding system of the second embodiment, the processor 13 transfers the STC value to the video decoder 5 after stopping sending other transfer commands through the peripheral bus, and therefore, we may reduce the impact of judgment on transferring STC When the value reaches the video decoder 5, β means that when transferring through the peripheral bus 7, except the transfer of the STC value to the video decoder 5, the same transfer as shown in FIG. 3 may also occur. If such a transfer occurs at the same time as the transfer of the STC to the video decoder 5, then the actual turn of the STC value into the video decoder 5 is subject to the influence of judgment. The transfer of the STC value to the video decoder 5 is a small amount each time, and the amount transferred per unit time is smaller than the amount shown in Figure 3. Therefore, if this STC value is transferred to the video decoder 5 with the highest priority, its influence on other transfers is extremely small. Therefore, in these transfers, the command concerning the transfer is output by the processor. Before the transfer of the STC value to the video decoder 5, the processor U temporarily stops sending the transfer command, and therefore the transfer of the STC value to The influence of the judgment on the video decoder 5 can be reduced. For this type of processing, 'it may be used in the middle of the program executed by the processor 13', that is, the transfer through the peripheral bus 7 is a request for the transfer service of this OS from each application software on the processor 13 Output, and this 0S receives this request, and outputs a transfer command through the processor's hardware) M specifications (210X297 mm) -------- install-i- (锖 先 读读Note on the back, please fill out this page again) Order 454421 A7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs _____B7 V. Description of the invention (30) Each device to the surrounding busbar 7. Therefore, the processor 13 is used to temporarily install other transfer service request processing by implementing the request of the transfer service that detects the STC value to the video decoder 5 whether it is output from the application software or not. In the decoding system 10 of the second embodiment, if an underflow occurs in the second buffer device 24, we may also combine with the method of reducing the impact on the STC restoration as explained below. In this case, we may also set the energy of the second buffer device 24 to be smaller than that explained in the first embodiment. Examples of this method are explained with reference to Figures 5, 6 and 7. Figure 5 is a conceptual diagram to explain the situation of STC restoration in the case of temporary underflow due to the influence of the judgment in the transmission decoder software generated according to the flowchart in Figure 2. In Figure 5, the horizontal axis indicates time, and the vertical axis indicates the main clock, and the values of STC and PCR. The discontinuous line 140 indicates that the counter 22 is generated by the counter printed by the Consumer Cooperative of the Intellectual Property Bureau of the First Ministry of Economy The main clock, a single-point chain-like straight line 14ι displays the STC value (two main clocks + DSTC), and the empty circle points 132 to 137 are equivalent to pcR values. These values are incremented over time 'and are therefore shifted to the right in Fig. 5. In Figure 5, at the beginning, the DSTC value is restored within the value indicated by the length of the line 138 in the figure. It is assumed that this second buffer 24 is emptied from time 130 to time 131. The transport stream received in the stream demodulator 2 is stored in the first buffer device 27 during this period. Subsequently, at the moment of the first input of PCR135, the paper size of the transport stream is applicable to the Chinese National Standard (CNS) A4 (210X297 mm) 4 5 44 21 A7 B7 printed by the Anti-Poverty Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Fifth, the description of the invention (31) After the resumption of the continued transfer, the value of DSTC is expanded to the value indicated by 139 in the figure, and thereafter, this value is used in the STC restoration. Therefore, the video PES is used in video decoding The subsequent decoding in the processor 5 and the decoding of the audio PES in the processor π are synchronized with the new STC, and a recurring time interruption occurs, which leads to the video skip due to the discontinuous decoding of the video PES and due to Audio skipping of discontinuous decoding of audio PTS. At this moment, from the third buffer device 4, this stream is consumed at a speed equal to the data speed of the original video PES, and at this equivalent speed, the transmission stream of this second buffer device is consumed, Therefore, from time 130 to time 131, the same amount of this transport stream is stored in the first buffer device 27 or the second buffer device 24 as if it were stored in the first buffer 27. This data summer is divided by the data speed of the transport stream, and the time it is generated is the amount of the non-recurring part of the reproductive time. This time is the time of the delay time newly added to the delay device 37 in the case of the first embodiment. To reduce this, an example of the flow chart of the decoder software is shown in Figure 6. The flow chart is different from the flow chart in Figure 2 in that a variable space count is provided (steps 602, 607), just before the start of reading the data packet and in the part that calculates the DSTC value (in Figure 6). Wave line 200) Use this value to add control. At step 601, the decoding process of the transport stream has started, and when the execution of the program has started, 0 is placed in the empty count (step 602), just before each packet read, we have detected This second buffer 24 (Please read the precautions on the back before filling this page); Binding and ordering Ί 4 5 4 4 2 1 A7 __B7 _._ V. Description of the invention (32) (Please read the precautions on the back first Fill out this page again) whether it is vacated or not (step 603), and if vacated, a specific number M is placed in the space count (step 604). This number M is used to control the number of PCRs of the M pieces entered immediately after the second buffer 24 recovers from the emptied state, and this number is not used for the restorer of DSTC. In the case where the data packet being read is a PCR to be decoded, we first check whether the space count is 0 or not (step 607). If the space count is 0, the second buffer 24 is not emptied, and the PCR is provided, and therefore the same procedure is performed as in the flowchart in Fig. 2 (step 608). If the space count is not 0, the PCR is used and the DSTC value is uncalculated (therefore, the STC value is restored. The DSTC value calculated and stored in memory in the previous guide is used), and a space is used. After the count is decremented, this operation proceeds to the next step (step 609). Fig. 7 is a conceptual diagram for explaining the situation of STC restoration in the case of the invention of temporary underflow due to the influence of the judgment in the software of the round decoder generated according to the flow in Fig. 6. In Figure 7, the horizontal axis represents time, and the vertical axis represents the values of the master clock, STC, and PCR. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. At the initial restoration in Figure 7, DSTC is the value indicated by 138 in the figure. Here, it is assumed that the second buffer device 24 is vacated from time 130 to time 131. When the first PCR 135 is entered after the continuous transfer of PCR restarts, since M is placed in the space count, this DSTC value Continuing is the same value as indicated by 157 in the figure.

In this case, the video PES that has been transferred to the third buffer device 4 applies the Chinese national standard (CNS) A4 specification (210X297 mm) 454421 A7 ___ B7 V. The description of the invention (33) is due to the The second buffer device 24 is vacated from time 130 to time i3i and no data packet is supplied to the processor 13 and is also stopped, and at this moment, this part is included in the third buffer device 4 The arrival of video PES in the payload of subsequent packets is delayed. However, since STC is restored without this delay time, the waiting time of video decoder 5 for image output is shortened, or this image has been skipped until the pTS of the image to be reproduced changes It is the same time as STC, and therefore, the consumption of video PES within video decoder 5 is continued onward in any one operation. As this consumption of video PES continues, the processing of the transport stream stored in the second buffer device 24 is accelerated by this processor 13. According to this, between time 130 and 131, the stream stored in the first buffer device 27 is released to the second buffer device 24 as it continues to move forward. Therefore, the PCR system is processed by the processor η at time 136 in FIG. 5 and is processed at time 151 in FIG. 7. In this way, when all the transmission streams stored in the first buffer device 27 are released between time 130 and 131, they are stored in the first buffer device 27 and the second buffer device 24. The sum of the transport streams is the same as when the STC is restored before time 130, and the delay time caused by the first buffer device 27 and the second buffer device 24 is returned to the state before time Π0, so that this PCR It is placed in the processor I3 at the same time as the original STC, just like the PCR after time 153. As a result, the influence of the undercurrent STC 150 value in the second buffer device 24 can be avoided. This paper size applies to the national standard of China (CNS > A4 specification (210X297). (Please read the precautions on the back before filling out this page); Sang. Order. Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs d 5 4 4 2 1 A7 B7 V. Description of the invention (34) By using the method explained in Figure 5, Figure 6, and Figure 7, we may be the time of PCR output of the M piece of the auto demodulator 2. Avoid the influence of the underflow of the second buffer device 24. Therefore, by multiplying the amount of time obtained by multiplying the portion of the PCR for the M pieces at the output data speed of the stream demodulator 2, we are It is possible to reduce the energy of the second buffer device 24 as compared with the first embodiment. In addition, when calculating DSTC from PCR, by using the average value of several PCR inputs, the stability of STC reduction may be enhanced. One method is based on Figure 8. Explanation. Figure 8 is a flowchart of the DSTC calculation procedure in the case of using the average of seven PCR inputs for STC reduction. This method replaces the flow in Figure 6. The part 200 is surrounded by a dotted line in the figure. For ease of explanation In Figure 8, the average value of seven PCR inputs is used, but that is not limited to seven. When the number of this PCR is large, the judgment of the bus is suddenly and significantly delayed The impact may be reduced, but the hardware load is increased inversely, and in actual devices, therefore, several PCRs can be set to a larger value within the range allowed by the hardware scale. In Figure 8, in order to Calculate the average of up to seven PCR and master clock differences. The variable DSTC (i) is used. Here, (i) is an integer ranging from 0 to 6. To count from the beginning of the average The number of PCR inputs, a variable DSTC count is used. When the space count is different from 0 (step 801), that is, when the second buffer device 24 is undercurrent, the space count is decremented. The paper size in (step 807) applies the Chinese National Standard (CNS) A4 specification (210X297 mm) n · nni-tt-n-! \ Iy 7 1 I (Please read the precautions on the back before filling this page ) Order Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 454421 A7 _B7 __ 5 Description of the invention Immediately after (35), the changeable DSTC count and DSTC system are cleared to 0 (steps 808, 809). ---------- install-^.-(Please read the back first For the matters needing attention, fill in this I.) Therefore, after passing the processing after step 610 in FIG. 6, the processing in step 801 in FIG. 8 starts again, and when the space count becomes 0, also That is, when the STC reduction system from the input PCR is started, the difference between the PCR and the master clock (the value of the first counter 22) is stored in the variable column DSTC (i) (steps 802, 803), and some stored differences The system counts up from DSTC to 60 and increments the DSTC count. However, when the DSTC count is not six, the DSTC count is incremented (steps 804, 805), and when the DSTC count is not six, this procedure Proceed to the next step (step 806) without incrementing. By constituting the transmission decoder software in this way, the STC can be restored by using the average value of the seven PCR inputs, and if the second buffer device 24 is undercurrent, set the averaging procedure once again, If the value of this DSTC has changed since the recovery from the underflow, we may immediately track it. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has printed another alternative method, which is to reset the average procedure, that is, from the part enclosed by the dashed line 201 in the flowchart in Figure 8, if the underflow occurs in the second When inside the buffer device 24, it can be designed to use this average continuously. This method is effective when underflow occurs frequently in a short period of time, as a result of slightly reducing the energy of the second buffer device 24 (and the first buffer device 27). As explained in this article, in the decoding system of the second embodiment, the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) 454421 A7 B7 5. Explanation of the invention (%) By omitting the delay device With the smaller hardware of 37, video and audio can be synchronized, and even in a structure that reduces the energy of the second buffer device 24, this STC can still be restored steadily. In the second embodiment, the purpose of stably restoring this STC has been achieved, and by using such a stably restored ST, the structure for more accurate synchronization of video and audio is shown in the third embodiment below Explanation: < Third Embodiment > Fig. 10 is a block diagram showing the structure of a decoding system in the third embodiment of the present invention. In FIG. 10, those parts that are common to the second embodiment in FIG. 4 are denoted by the same reference numerals, and repeated explanations are omitted. A The difference between the third embodiment and the second embodiment is The second clock generator 20 and the second counter 21 are provided so that a master clock can be added here, and the DSTC value fed by the processor 13 through the first bus interface device 3 to A selector 34, using an adder to obtain the sum of the output of the selector 34 and the master clock from the second counter 21 to restore the STC 'and feed the restored STC into the video decoder 5, and at the same time the arbitration The programmer 30 is connected to the peripheral bus 7 to send information about the judgment of the shoulder bus 7 to the processor 13 and to use the control of the processor 13 to change the operation of the judgment. By installing the second clock generator 20 and the second counter 21 to generate the master clock, the processor 13 and the video decoder 5 can also talk about the master clock so that the left STC shifts to the upper periphery. The influence of the judgment of the bus bar 7 can be reduced. However, for this purpose, at the same time, I must apply the national standard of the T country (CNS) rule 8 (2) OX297 mm at the same time (please read the precautions on the back before filling this page). -Ordered by the Consumer Cooperative of the Intellectual Property Office of the Ministry of Economic Affairs 19 454421 A7 B7 V. Description of the invention (37) The master clock generated by the first counter 22 and the master clock generated by the second counter 21 are the same value. --------- 7 =. 装-..-广 ../ (Please read note f on the back before filling this page) In the third embodiment, therefore, the first clock generator 20 and the second clock generator 23 are formed by using a quartz oscillator of the same frequency. By using a quartz oscillator of the same frequency, the frequency difference between the two quartz oscillators can be suppressed to a level where one stone affects the synchronization of video and audio. Referring now to FIG. 11, one of the values of matching the master clock generated by the first counter 22 and the master clock generated by the second counter 21 is explained as follows. Figure Π shows an example of the boot sequence in the decoding system from the supply of power to the start of transmitting the decoding software. At step 1101, the electric power system is supplied, and this os system is activated. Alpha. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. When the power system of this decoding system has been connected, first this OA system is as normal. The same procedure as the start procedure of the OS is implemented. That is, it includes self-test (step 1102), reading from the master boot record of HDD 24 (step Π 03) 'OS load loader enters memory 11 (step π 04)' and checking hardware data ( After the execution of the procedure of step 1105), before the load of the OS points enters the memory 11 (step 1107), that is, a stage before the access to the peripheral bus (not HDD 26) begins, the HDD Access to 26 has stopped (step 1106). In this state, within the peripheral bus, the transfer request is not formed by any bridge or interface device. Now, in this state, the value of the first counter 22 is transferred to the paper. It is appropriate to use the Chinese National Standard (CNS) from the secret (21 ();) < 297 public works) ~ — — -4Π 4 5 44 2 1 A7 _B7_ V. Description of the invention (38) Second counter 21 (step 1106) »Therefore, we may transfer without causing a delay in the judgment of the transfer request by the bus, so that the first counter The values of the generated master clock and the master clock generated by the second counter can match. In the future, the OS points of this decoding system are loaded into the memory 11 (step 1107), the os system has begun (step 1108), and the transmission decoder software system starts in the started OS (step 1109) . On the other hand, 'the processor 13 and the video decoder 5 can both refer to the master clock' and restore this STC individually, and therefore the DSTC is transferred from the processor 13 to the frequency decoder 5 to replace the value of the STC itself . In the configuration in FIG. 10, a schematic flowchart of one of the transmission decoder software to be executed by the processor 13 is shown in FIG. FIG. 12 is similar to the flowchart in the second embodiment in FIG. 6, that is, when the data packet is processed and transferred to the frequency decoder 5 (step 614), the procedure for restoring the STC is changed to check The procedure of space counting (step 1214), and transfer the DSTC value directly to video decoder 5 (step 1215). After the processing of a tandem data packet is terminated, we first check whether the space counting is 0 or not (step 1214). , And if it is not 0, that is, if the DSTC value is not updated, the next data packet is processed (return to step 1203). If the space count is 0, that is, if the DSTC value is updated, the DSTC is transferred by the main bus 10, the bridge 8, the peripheral bus 7, and the first bus interface device 33. To adder 35 »When this processor 13 is performed as shown in this flowchart, if this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 meal) —--41-(Please read first Note on the back, please fill in this page again) Order printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives 4 5 44 21 A7 ________B7 V. Description of the invention (39) When the DSTC value has been updated, this DSTC / £ fc is transmitted through this neighborhood The stream 7 is sent to the selector 34. In the structure of FIG. 10, 'this selector 34 stores the latest DSTC value from a specific number of the entered DSTc values, and outputs the minimum value of them to the adder 35 «This adder 35 is stored from the first bus The DSTC value entered by the interface device $ is added to the master clock output from the second counter 21, and the sum of the STC value itself (ie, the STC value itself) is output to the video decoder 5. In this configuration, 'we' entered in video decoder 5 is used to restore one of the STCs using the minimum value of the specified number of entered DSTC values. It means one of the effects of the smallest judgment among a certain number of DSTC values. In this embodiment, in order to reduce the influence of judgment on the STC, the arbiter 30 is connected to the peripheral bus 7, And the algorithm designed by us to send information about the judgment of the peripheral bus 7 to the processor 3, and to change the control of the processor 13 from this. That is to say, in this configuration, when the processor 3 transfers the DSTC value to the selector 34 through the peripheral bus 7, the arbiter is controlled, and the priority of the bridge 8 is temporarily changed. Is higher. As a result, the request to transfer the dSTC value from the processor 13 to the selector 34 through the bridge 8 and the surrounding bus 7 is given higher priority than other transfer requests, and the time until the transfer request is accepted is relatively high. short. Therefore, because the time from the output of the total processor 13 of the DSTC value to the time when it reaches the selector 34 is reduced, the original selected by the adder 35 and the use of this DSTC value are entered as the paper size applies to the country. Rate (CNS) 8 sides ^ plus 7 mm) (Please read the precautions on the back before filling out this page)-Order printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 42 4 5 44 2,1 A7 _____B7______ 5. Description of the Invention (4) This STC in the frequency decoder 5 further reduces the influence of the judgment of the peripheral bus 7. In addition, in this structure, we may also avoid the underflow of the second buffer device 24 due to the influence of the judgment of the surrounding busbars. That is to say, this processor 13 detects and stores in a specific period of time. When the remaining transport stream in the second buffer device 24 and the remaining data become less than a specific value, the arbiter 30 is controlled, and the priority of the first bus interface device 3 is temporarily raised. By increasing the priority of the first bus interface device 3, the underflow of the second buffer device 24 can be avoided. Assume that the remaining data system is completely 0. If the priority is raised in this state, the undercurrent state will remain as it is until the next data system has entered. Based on this, “by temporarily increasing the priority of the first bus interface device 3”, the underflow of the second buffer device 24 has been avoided. To be clear, when the remaining data becomes smaller than the specified amount, it is equivalent to The specific value of this value is as follows «* [(average output speed of the second buffer device 24)-(average output speed before increasing the priority of the second buffer device 24) x (until the priority is increased first The data is the time until the second buffer 24 has entered. Accordingly, the auto demodulator 2 'and the second buffer 2 7 are stored in the first bus interface device 3 * the peripheral bus 7, the bridge 8, And the transfer request of the main pass stream 10 output to the second buffer device 24 is given a higher priority than other transfer requests, and therefore the input speed of the transmission stream entering the second buffer device 24 is relatively higher. Fast, so that the underflow of the second buffer device 24 can be avoided. The paper size is appropriate. Use the Chinese National Standard (CNS) A4 specification (21 〇χ 297 mm) — ---- -41. ^ 1.1 III -I -I an uM111 I in _, tT.1 II— —I— ( Read the notes on the back before filling this page) 4 5 4421 A7 B7 V. Description of the invention (41) At this time, the remaining data can be checked, for example, by comparing the address of the read indicator and The address of the write-out indicator of the stream to the second buffer device 24. The standard used to change the priority order of the first bus interface device 3 can be implemented by the following standards. For example, when from the first buffer device 27 to The transfer request of the second buffer 24 stream is output by the command from the processor 13 by the first bus interface device, assuming that it is accepted in the arbiter 30 and the transfer has started Is Tsta, and the data speed used by the processor 13 to read the stream from the second buffer device 24 is Rstd. The time when the remaining stream stored in the second buffer device 24 becomes smaller than TstaxRstd On the basis (actually, the threshold is set to be somewhat larger in consideration of a tolerance) 'This processor 13 has a higher priority in setting the first bus interface device 3. Therefore, the processor 13 reads from second Before all the stream data of the buffer device 24, 'the input speed of the transport stream entering the second buffer device 24 has been enhanced' and the underflow system of the second buffer device 24 has been avoided. By this one operation 'and always given Compared with the method of giving the highest priority to the first bus interface device 3, the influence on other main devices is smaller, and the underflow of the second buffer device 24 can be avoided at the same time. Moreover, as shown in FIG. 6 When the processor 13 applies this algorithm to maintain the original STC to a specific time after the underflow of the second buffer device 24, the stability of the STC restoration can be enhanced by this composition. Operation is as follows. Private paper scales are in accordance with China's national standard (CNS > A4 specification (21〇χ 297) ----------- hi. Packing-►― 广 '、 · (Please read the note on the back first (Fill in this page again) ί1τ

A Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 44 454421 A7 __B7 _'_ V. Description of the Invention (42) (Please read the precautions on the back before filling this page) That is to say, when you start decoding or changing the stream (change channels ), The processor 13 controls a specific number M to be set at a space count of 0 or near 0, and shortens the time for retaining the original STC. By controlling the arbiter program 30, the priority of the first remote streamer interface device 3 is temporarily raised, and the underflow in the second buffer device 24 is avoided, so that the STC can be stabilized. reduction. With this operation, after the STC is definitely restored, the specific number M set in the space count is set to a larger value within a range. Within this range, do not update this STC while retaining the original STC here The actual system is in almost all underflows. Accordingly, when the stream is started to be decoded or converted, the STC is surely restored by controlling the arbiter 30, and since then it has been kept almost unchanged, so that the stability of the STC restoration can be enhanced. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy The time delay of the master clock of 22 reaches the second counter 21 can be suppressed to be smaller. As a result, the amount of delay of the value of the master clock output by the second counter 21 is reduced when compared with the value of the master clock output by the first counter 22, and the values of the two master clocks can be surely synchronized. In addition, when the energy of the second buffer device 24 is set, the processor 13 directly reads the number of main devices from the arbiter 30 and sets the energy calculated at this value to make the second buffer 24 The energy can be set with a sufficient value. That is to say, as explained in the first embodiment, when the paper wave scale is set to the Chinese National Standard (CNS) A4 specification (210X297 mm) -45-Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economy 454421 A7 __________ B7_ V. Description of the invention (43) When the energy of the second buffer device 24 is set to TmaxXNaXR + 512 = Nmax or more, in the first embodiment, Na is set to the maximum number of main devices', but in this case In fact, there are slots in which the card is inserted, and the energy of the second buffer device 24 is set to a value larger than the actual energy required. The substitute 'can read the energy of the Na' second buffer device 24 directly from the arbiter 30 and can set it accurately by the number of master devices actually operating on the bus. As explained in Section A of this article, in the decoding system of the third embodiment, the master clock is also generated on the board by installing a second clock generator 20 and a second counter 21, and the video decoder 5 The impact of the judgment of the peripheral bus 7 on the STC restored by the adder 35 by using the DSTC transferred from the processor 13 and further by selecting and using one of the smallest delays due to the judgment of the transferred DSTC It can be reduced in the transfer of STC. There are still entrants, so that the processor 13 controls the arbitration program 30 and temporarily increases the priority of DATC transfer. When this DSTC is transferred, the impact of the judgment of the surrounding warm current can be further transferred on the STC transfer. Decrease. < Fourth embodiment > Fig. 13 is a block diagram showing the construction of a decoding system in a fourth embodiment of the present invention. In Fig. 13, those parts which are common to the third embodiment in Fig. 10 are designated by the same reference numerals, and repeated explanations are omitted. The difference between the fourth embodiment and the third embodiment is that the selector 34 and the adder 35 are eliminated, so that the master clock can be fed directly from the second counter 21 into the video decoder 5. This paper & size is suitable for towels (CNS) A4 size (2 丨 0X297mm) '--- (Please read the notes on the back before filling this page)

46 4 5 4421 A7 __B7_ V. Description of the Invention (44) (Please read the notes on the back before filling out this page) In this example, this DSTC is not transferred separately, but it is transferred before being included in the processing One of the PTS of the video PES transferred by the cameras 13 to the third buffer device 4 is in one of the formats. This processor 13 extracts PTS from the multi-distributed video PES, calculates PTS-DSTC, and uses it as a corrected PTS (hereinafter, this video PES replaces this PTS range with this corrected PTS is called a corrected video PES ), And transfer to the third buffer device 4 by the way of the main bus 10, the bridge 8, the peripheral bus 7, and the first bus interface device 3. FIG. 14 shows an example of a schematic flow of the transport decoder software used on processor 13 to form such a process. What is different from the flow chart in Figure 12 is that the transfer process of DSTC is omitted, and the process of replacing this PTS with a corrected PTS (PTS-DS-D) is added by <2 in the video data package. Processing. "\ When the content of the data packet being read is the video PES to be decoded, we will determine whether PTS is included in the video PES, and if PTS is included, then PTS-DSTC is calculated, and It is used as a corrected PTS to replace the original PTS range. Thereafter, the video PES is transferred from this packet to the first buffer device, and the processing of this packet is terminated. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 15 is a conceptual diagram to explain the synchronization of the decoding operation with STC. The above operations may be in the video decoder 5. In Fig. 15, the horizontal axis indicates time, and the vertical axis indicates the values of the master clock, STC, and PTS. The dashed line 123 shows the master clock generated by the first counter 22, the solid line 120 is the master clock generated by the second counter 21, and the single-point chain lines 121 and 122 indicate the STC value (equal to the master clock plus DSTC), and all The paper size of the X-point paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 cm) -47-454421 A7 _____ B7 5. Description of the invention (45) Including 110 and 13 series of 3 values. Since these values increase over time, they all move up and to the right in the figure. When the power system is connected at time 100, the guidance sequence in FIG. I is executed, and the master clock value of the first counter 22 is transferred to the master clock of the second counter 21 at time 101. The first PCR was performed at time 103 from the incoming transport stream, and the STC reduction system started. When this processor detects pTS j 10 at the time, the value of DSTC is expressed by the length of the straight line indicated by 111. At this moment, the value of the corrected PTS (equal to PTS-DSTC) calculated by the processor 13 is equivalent to the value indicated by 112 in the figure. The video decoder 5 reads the corrected PTS 112 value from the incoming corrected video PES and when the value of the master clock 120 reaches this corrected PTS value 112, the corrected ptS is output at time 104. Adding the image inside this time 104 is equivalent to the time when STC121 reaches the same value as the original PTS 110, and it is well known that the video decoder 5 has operated to issue synchronization with this STC by using this PTS Its output. Subsequently, at time 105, the receiving channel system changes, and the restoration of other streams is known. In this case, the restored STC is a value smaller than the master clock, but the operation is still the same as described above. That is, a first PCR is changed at time 105 from the detection of the transport stream in the receiving channel, and the restoration of a new STC has begun. When this processor 13 detects PTS 113, the value of DSTC is represented by the straight line length indicated by I14 (however, this value is negative). The size of this paper is suitable. Use Chinese National Standard (CMS) A4 specification (2 丨 0X297mm) (Please read the notes on the back before filling in this page)-Order 4 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 48 4 5 44 21 A7 B7 V. Description of the invention (46) At this moment, the value of the corrected PTS (equal to PTS-DSTC) calculated by the processor 13 is equivalent to the value indicated by 1.15 in the figure. (Please read the precautions on the back before filling this page) This video decoder 5 reads the corrected PTS 115 from the incoming corrected video PES, and outputs the PTS image that has been added to it as the master at time 106 The value of the clock 120 reaches this corrected PTS value of 115 hours. This time 106 is equivalent to the time when the new STC 122 reaches the same value as the original PTS 113. It is also a known one, that is, this output is related to STC synchronization by using PTS. In this operation, the time when the corrected PTS reaches the third buffer device 4 may be delayed due to the influence of the judgment in the peripheral bus 7. However, this delay effect is absorbed by the first buffer device. That is to say, immediately after the time 107 when the processor 13 detects the PTS 113, the corrected PTS has been transferred to the third buffer device 4, but as far as this transfer is terminated before time 104, this There is no problem for a period of time, and the delay in judgment during this period is allowable. In the decoding of video and audio, by adding a same delay amount to both master clocks, and increasing the energy of the third buffer device 4 by a portion equivalent to this delay amount, the delay time of this allowable judgment can be Stretch further. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

Therefore, in the fourth embodiment, since the master clock system is directly placed in the video decoder 5, the DSTC system is not transferred to the video decoder 5 separately, but it is included in the correction PTS (PTS-DSTC). One alternative format of the PTS range of the original video PES is sent to the video decoder 5 through the third buffer device 4, so that the influence of DSTC due to the judgment of the peripheral bus is absorbed by the third buffer device 4, And therefore, in the total STC paper scale, China National Standards (CNS) A4 specifications (2 丨 0X297 mm) -49-454421 A 7 B7 V. Description of the invention (47) (Please read the precautions on the back before reading (Fill in this page) based on the decoding operation can be performed more accurately between the processor 13 and the video decoder 5. As a result, we may borrow the video decoder 5 and this decoded audio data to synchronize accurately between the decoded video output and the output from the processor 13. &lt; Fifth Embodiment &gt; A fifth embodiment of the present invention is described with reference to FIG. 16 at the same time. Fig. 16 is a block diagram showing the construction of a decoding system in the fifth embodiment of the present invention. In Fig. 16, those parts which are common to the fourth embodiment in Fig. 13 are denoted by the same reference numerals, and repeated explanations are omitted. All the differences between the fifth embodiment and the fourth embodiment are that the output clock of the first clock generator 23 is used as a clock for driving the peripheral bus 7 and that this clock is used for the second counter 21 Input. According to the fifth embodiment, according to the fifth embodiment, the frequency of the main clock output from the first counter 22 and the frequency of the main clock output from the second counter 21 can be accurately matched, so that the processor 13 and the video The decoder 5 can be synchronized on the spot by STC. &lt; Sixth embodiment &gt; Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The sixth embodiment of the present invention is explained while referring to FIG. Fig. 17 is a field diagram showing the construction of a decoding system in the sixth embodiment of the present invention. In Fig. Π, those parts which are common to the fourth embodiment in Fig. 13 are given the same reference numerals, and repeated explanations are omitted. All the differences between the sixth embodiment and the fifth embodiment are the reset signals of the peripheral bus 7 are fed into the first s ten digits 3 ^ 21 through the first bus interface device 3, such as by ^ Break the line 36, and pass the bridge 8 The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 50

Claims (1)

4 5 44 21 A8 B8 C8 D8 _ VI. Patent Application Scope 1. A decoding system for receiving at least one set of compression and encoding video signals, a time stamp, and restoration of the decoding system. A system streamer of a video stream obtained from the program clock data of the system timing clock includes: a first buffer device, which also stores and outputs the incoming system 涑, a bus, which is used to transfer data and a control signal, An arbiter, for determining a transfer request from a device connected to the bus, a second buffer device, through which the bus receives the output of the first buffer device and stores it, a processor, It is used to decode the video stream and time stamp necessary for the output of the system stream stored in the second buffer device, extract the program clock data, restore and output the system timing clock, and a video decoder for Receives the video stream 'time, time mark and system timing clock output from this processor, and resolves on the basis of the system timing clock The video stream, and output this decoded video at the time presented by this time stamp. The clothing of the Intellectual Property Bureau of the Ministry of Economic Affairs's consumer co-operative prints clothing. 'The energy of the second buffer device is set to be higher than that of the bus. The internal transfer request is judged by the energy of the system stream that is entered in the required time. "2. For example, the decoding system of the first scope of the patent application, wherein the arbitration programmer is designed to One when transferring for a specific longest transfer time, 'to cut off this transfer, and the paper size of the second buffer is applicable to China National Standard (CNS) A4 specifications (21G X 297 public love) 53 4 5 442 A8 B8 C8 D8 6. The energy set in the patent application range is set to be larger than the product of the number of devices that can be connected to this bus multiplied by the longest transfer time and the data flow rate of the system stream. 3. For the decoding system in the first item of the patent application scope, the energy of the second buffer device can be variably set by the processor, and the processor does not measure the device that judges the transfer request in the bus. , And the energy of the second buffer device is set to be larger than the product of the number of devices that require a transfer request multiplied by the maximum transfer time of each device and the data flow rate of the system stream. 4. If the decoding system of the third item of the patent application is applied, the arbitration program is sent to the processor via ka &quot;} * to send the information of the device in the Pan Liupai to request the transfer request. 5. —A decoding system for receiving at least one video from the multiplexed compression and encoding of a video signal 'a representation time stamp, and a video obtained by restoring the program clock data of the system timing clock of the decoding system One of the system streams includes: a first buffer device for storing and outputting the incoming system stream, a bus for transferring data and a control signal, and an arbiter programmer for judging its own connection So far the transfer request of the bus device, the second buffer device, through which the bus receives the output of the first buffer device and stores it, and a processor for decoding the data stored in the second buffer device. System stream, output the necessary video stream and time stamp, and extract the process. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297). (Please read the notes on the back *. ,, fill in, write (This page) Printed line of employee cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs · 54 4 5 44 2 1 A8 B8 C8 D8, patent application sequence clock data ', and restoration and output Output the system timing clock, and a video decoder 'for receiving the video stream output from the processor' time stamp and the system timing clock, decode the video stream based on the system timing clock, and The video of this solution is output at the time of presentation, where the processor detects the remaining data in the second buffer and controls the arbiter, so that the system flow from the first buffer device is transferred to the first Two buffer devices, when the remaining data becomes smaller than a certain amount, it can be designated as the first priority in the judgment of the transfer request of the bus "6. A decoding system 'used to receive multiple transmissions at least A group of system streams from a video stream obtained by compressing and editing a video signal, a time stamp, and program clock data used to restore the system clock of the decoding system, including: a first buffer The device is used to store and output the incoming system stream, a bus is used to transfer data and a control signal, and an arbiter is used to judge itself A transfer request from a device connected to the bus, a second buffer device, through which the bus is used to receive the output of the first buffer device and store it, a first clock generator for generating a specific frequency The clock, a first counter, is used to generate a master clock. Since then, the timing clock of the first clock generator system has changed in the same period, and the paper size applies the Chinese National Standard (CNS) A4 specification (21〇X 297 public hair) ------------- i .. &lt; · -N (Please read the notes on the back before filling this page) Order ---_------ line Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 55 464421 A8 B8 C8 D8 Printed by the Consumers ’Cooperative of the Ministry of Economic Affairs. Produced by the Consumers’ Cooperative of the Production Bureau 6. The scope of patent application is given to a processor, a processor to decode and store in the second The system stream in the buffer device outputs the necessary video stream and time stamp, extracts the program clock data, restores and rotates the system timing clock, and a video decoder to receive the video output from the processor Stream, time stamp The system timing clock decodes the video stream based on the system timing clock and outputs the decoded video at the time represented by the time stamp. The processor stores the difference between the program clock data and the main clock and Restore this system timing clock. 7. If the decoding system of claim 6 is applied, the processor detects whether the second buffer device is vacated or not vacated, and if it is vacated, the difference between the program clock data and the master clock is updated to one of the following Specific time. 8. If the decoding system of claim 7 is applied, the processor controls the arbiter, so that the output of the first buffer device is transferred to the second buffer device, just after the start of decoding. , Or just after the change of the stream to be decoded, the first priority can be assigned to the judgment of the transfer request of the bus. 9. If the decoding system of the patent application No. 6 is used, the processor uses the average value of the difference between the program clock data and the master clock for a fixed number of times to restore the system clock. 10. A decoding system 'for receiving multiplexed at least one set of compressed and encoded video signals, a time stamp, and a Chinese paper standard (CNS) A4 (21〇X 297) (Gongchu)-nn ^^ 1 ^^ 1 ^^ 1 ^^ 1 cal ft ^^ 1 ^^ 1x, ^^ 1 ^^ 1 ^^ 1 ^^ 1 I ^^ 1 ^^ 1 ^^ 1 '- Γ. Ν ·-: (Please read the precautions on the back before filling in this page) Line U. 56 4 5 44 21 A8 B8 C8 D8 VI. Application scope of patent The system clock of the system timing clock of the inscription relief system A system streamer who obtains a video stream includes: a first buffer device for storing and rotating the incoming system stream, a program clock data multiplexer for separating the program clock data from the incoming system stream And output to the delay device, the delay device is used to delay the program clock data from the program clock data splitter and output to the system timing clock restoration device 9 system timing clock restoration device, by using the program from the delay device The clock data is used to restore the system timing clock. The bank is used to transfer data and control signals. An arbiter is used to judge a transfer request from a device connected to the bus. The second buffer device is used to receive the first buffer through the bus. The output of the device is stored. The first clock generator is used to generate a clock of a specific frequency, and the first thirty digitizer is used to generate a master clock, as is the system timing clock of the first clock generator. Changed in the same period and fed into a processor, a processor 'used to detect the system stored in the second buffer device, output the necessary video stream and time stamp, extract the program clock data' and calculate from This first master clock is used as the difference between the timing clock of a differential system, and this paper size applies the Yin National Standard (CNS) A4 specification (210 X 297 mm) (read the precautions on the back before writing this page) Order --------- Line 4 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 57 4 5 44-2 鲔 充 AS B8 C8 D8 六 、 Applicable patent scope 16. If you apply for the solution of item 15 of the patent scope The code system, in which the first master clock of the first counter is connected to the power just after the power is connected, or just after setting the processor again, after stopping all data transfer through the bus The second counter, so that the second master clock can be almost the same value as the first master clock. 17. The decoding system according to item 15 of the patent application scope, wherein the processor controls the arbitration program to 'make a transfer from the first master clock of the first counter to the second counter' a transfer request at the confluence Judgment can be given to the first priority 'and the first master clock from the first counter is transferred to the second counter, so that the second master clock can be close to the same value as the first master clock 6 18 For example, the decoding system of the patent application No. 15 wherein the reset signal of the bus is input into the first counter and the second counter immediately after the power is turned on or after the bus is reset. 'This first master clock and the second master clock are set to almost the same value 19. For example, the decoding system of the 15th patent application scope further includes a second clock generator for generating the same as the first clock generator. A clock of the same frequency is output to the second counter. 20. The decoding system according to item 15 of the patent application park, wherein the bus uses the clock output from the first clock generator as the transfer clock of the bus, and the first counter receives the transfer clock of the bus and generates a first Two master clocks. 21 · If the decoding system for the item in the scope of the patent application includes a selector, this paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page } W -------- tr-- !! Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -61, 454421 A8 B8 C8 DS 6. The scope of patent application, a designated number is used to store the output from the processor The differential system timing clock selects one of the minimum values of the stored differential system timing clock 'and outputs it to the adder. U For example, the decoding system of the patent application No. 15 wherein the processor controls the arbiter,俾 The transfer of the timing clock of the differential system to the adder can be given the first priority in the determination of the transfer request of the bus. 23. A decoding system for receiving multiple transmissions of at least one set of borrow compression and encoding Video signal, a system streamer that represents a time stamp and a program clock data used to restore the system clock of the decoding system, including: Please read first Note that the surface of the item IIIII Unified buffer device, used to store and output the entered consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs, print a bus, used to transfer data and a control signal, and an arbiter, to judge itself The transfer request of the device connected to the bus, the second buffer device, through which the bus receives the output of the first buffer device and stores it, 'a first clock generator for generating a specific frequency Clock J is a first counter for generating a first master clock. If the system timing clock of the first clock generator is changed in the same period and fed into a processor, a processor is used to decode and store In this second buffer device, the paper size of this paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 Gongchu) line 62 4 5 442 Ί A8 BS C8 D8, the system stream for patent application 'output the necessary video stream and Time stamp, extract the program clock data, calculate the difference from the first master clock to obtain a differential system timing clock, and calculate the decoding time Record the difference between the timing clock of the differential system and obtain a corrected time mark. And output the corrected time mark, together with the necessary video stream, to the third buffer device and the third buffer through the bus. A device for receiving the video stream and the corrected time stamp output from the processor through the bus and storing it, and a second counter for generating a second master clock, just as the system timing clock is in the same period Change and feed to a video decoder and a video decoder to receive the second master clock output from the second counter, decode the video stream stored in the third buffer, and correct it by This decoded video is output at the time represented by the time stamp. ---- --- 1! ---- atM .---------- yes --- Γ .----- line ^ ; (Please read the notes on the back before filling out this page) Printed on the paper by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, China Paper Standard Applies to Chinese National Standard (CNS) A4 (210 X 297 mm) 63