JPH1195450A - Resist pattern forming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a resist pattern forming method which may be simply and easily executed and is capable of making the distribution of the line width within the plane of a process substrate uniform in the lithography technique of a process for producing semiconductor integrated circuit devices. SOLUTION: This resist pattern forming method is constituted so as to include a stage for applying a chemically amplified resist on the process substrate, a stage for prebaking the chemically amplified resist, a stage for irradiating the chemically amplified resist with ionization radiations, a post-exposure baking processing stage for the chemically amplified resist irradiated with the ionization radiation and a developing stage for the chemically amplified resist. In such a case, the post-exposure baking processing stage includes at least twice of the post-exposure baking processing and is executed by rotating the process substrate by the angle obtd. by dividing 360 deg. by the number of the post-exposure baking processing times at every post-exposure baking processing of the second and succeeding times.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to an improvement in lithography technology.

2. Description of the Related Art In recent years, high integration is required for semiconductor integrated circuit devices, and it is necessary to miniaturize circuit patterns. For this reason, it has been promoted to increase the resolution of the exposure apparatus and shorten the wavelength of the light beam to be used, and a higher resolution and a more stable line width have been demanded for the resist. .

With respect to resists, recently, chemically amplified resists containing a photoacid generator have been spotlighted, and are being actively developed. Under the circumstances described above, there is a demand for a method of forming a resist pattern by a lithography technique using a chemically amplified resist containing a photoacid generator capable of miniaturizing a circuit pattern.

[0004]

2. Description of the Related Art Hereinafter, a conventional resist pattern forming method using a negative type chemically amplified resist will be described in detail.

[0005] A conventional resist pattern forming method is performed as follows. First, using a resist coating and developing device SK-80BW manufactured by Dainippon Screen Co., Ltd., a negative chemically amplified resist TDUR manufactured by Tokyo Ohka Kogyo Co., Ltd. was applied to the surface of a silicon wafer subjected to hexamethyl disilazane processing (HMDS processing). -N908 film thickness of 0.50 μm
After the resist film was formed, a pre-bake treatment was performed at 90 ° C. for 90 seconds using a hot plate mounted on the resist coating and developing apparatus SK-80BW.

Next, a reduction projection exposure apparatus NS manufactured by Nikon Corporation
Using R-2005EX8A, wavelength = 248 nm, NA = 0.50
Exposure was performed on a pattern having a line of 0.27 μm width and a space of 0.27 μm width.

When the exposure apparatus irradiates the exposure apparatus with ionizing radiation through the reticle, an acid is generated only in the region of the chemically amplified resist film irradiated with the ionizing radiation according to the reticle pattern.

After this exposure treatment, a post-exposure bake treatment (PEB treatment) at 100 ° C. for 90 seconds was performed. This PEB
When processing is performed, in the case of a negative resist, the acid generated in the resist film renders the properties of the base resin insoluble in a developing solution, and a resist pattern is formed by the developing process. Since the acid acts as a catalyst and renders the properties of many base resins insoluble, high sensitivity of the resist film can be realized.

After the PEB treatment, the film was once cooled to 23 ° C. and then developed. Thereafter, the line width distribution in the silicon wafer surface was examined using a length measuring SEM (Hitachi S-8600). As a result, the line width distribution in the silicon wafer surface was determined as shown in FIG. 16nm at 3σ variation
3 (a), AA 'traverse line, BB' traverse line, C-C '
The line width distribution on the traverse line and the DD ′ traverse line were as shown in FIG. 3 (b), and the line width distribution was clearly varied in the silicon wafer plane.

[0010]

In the conventional method of forming a resist pattern using such a chemically amplified resist, all the resist pattern formation reactions are performed by a single PEB treatment after exposure, and therefore, a hot plate is not used. However, high controllability is required for temperature controllability, uniformity of in-plane temperature distribution, temporal controllability, and the like.

In particular, the in-plane temperature distribution of the hot plate directly affects the distribution of the line width in the plane of the processing substrate, and the distribution of the line width in the plane of the processing substrate directly changes the in-plane temperature distribution of the hot plate. It is a distribution that reflects.

In the above-described conventional method of forming a resist pattern using a chemically amplified resist, since all of the resist pattern formation reactions are performed by one PEB treatment after exposure, the method is expensive with respect to a hot plate. There was a problem that controllability was required.

The present invention has been made in view of the above circumstances, and has as its object to provide a method of forming a resist pattern which can be easily and easily carried out, and which can make the distribution of line width in the plane of a processing substrate uniform. It is what it was.

[0014]

According to the present invention, there is provided a method for forming a resist pattern, comprising the steps of: applying a chemically amplified resist on a processing substrate; prebaking the chemically amplified resist;
Irradiating the chemically amplified resist with ionizing radiation,
In a method of forming a resist pattern including a post-exposure bake process of the chemically amplified resist irradiated with the ionizing radiation and a development process of the chemically amplified resist, the post-exposure bake process includes at least two post-exposure bake processes. And for each subsequent post-exposure bake
Rotating the processing substrate by an angle obtained by dividing 60 degrees by the number of times of the post-exposure bake, and cooling the chemically amplified resist during at least two times of the post-exposure bake To have.

That is, according to the resist pattern forming method of the present invention, the post-exposure bake process includes at least two post-exposure bake processes, and the bake process is performed by 360 degrees every second and subsequent post-exposure bake processes. Since the processing substrate is rotated by an angle divided by the number of post-exposure bake processes, the processing is not affected by variations in the in-plane temperature distribution of the hot plate, and a good line width distribution in the processing substrate is obtained. It becomes possible.

Therefore, when manufacturing a highly integrated and highly integrated semiconductor integrated circuit device, a resist pattern having a good line width distribution can be formed by the resist pattern forming method of the present invention.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, first to fourth embodiments of the present invention using a negative type chemically amplified resist will be described in detail.

The method of forming a resist pattern according to the first embodiment of the present invention comprises the following steps. (1) Resist coating and developing equipment SK manufactured by Dainippon Screen
Using -80BW, a 0.50 μm thick resist film made of a negative chemically amplified resist TDUR-N908 manufactured by Tokyo Ohka Kogyo Co., Ltd. is formed on the surface of the HMDS-treated silicon wafer. (2) Then, the resist coating and developing apparatus SK-80BW
Pre-bake at 90 ° C for 90 seconds using a hot plate mounted on the (3) Next, a reduction projection exposure apparatus NSR-20 manufactured by Nikon Corporation
Using 05EX8A, wavelength = 248nm, NA = 0.50, 0.27μ
Exposure is performed for a pattern with a width of m and a space of width 0.27 μm. (4) Perform PEB treatment at 100 ° C for 45 seconds. (5) Once cooled to 23 ° C, the silicon wafer is rotated by 180 ° C by the coating cup of the resist coating and developing device, and heated again at 100 ° C for 45 seconds using the same hot plate. After the cooling, the development is performed.

Thereafter, a length measuring SEM (S-860 manufactured by Hitachi, Ltd.)
As a result of examining the line width distribution in the silicon wafer plane using (0), the line width distribution in the silicon wafer plane was 8 nm at 3σ, as shown in FIG. (a) on AA 'traverse line, B-B' traverse line, C-C 'traverse line,
The line width distribution on the D-D 'traverse line is as shown in Fig. 1 (b).
Very good results were obtained.

The PEB processing after the above-described exposure processing was performed twice by rotating 180 degrees, but three times by rotating 120 degrees, four times by rotating 90 degrees, and six times by rotating 60 degrees. For example, the heat treatment may be performed by rotating 360 degrees by an angle obtained by dividing 360 degrees by the number of heat treatments.

The heating time was set to 45 seconds because the heat treatment was performed twice, but was set to 30 seconds if the heat treatment was performed three times, to 22.5 seconds if the heat treatment was performed four times, and to six times. If the heat treatment is performed, the heat treatment may be performed for a time obtained by dividing 90 seconds by the number of heat treatments, such as 15 seconds.

The method for forming a resist pattern according to the second embodiment of the present invention comprises the following steps. (1)-(4)
The steps up to this are the same as the resist pattern forming method of the first embodiment. However, in the resist pattern forming method of the second embodiment, the cooling process is not performed during the PEB step (5). The silicon wafer is rotated 180 ° C. by the coating cup of the developing device, heat-treated again at 100 ° C. for 45 seconds using the same hot plate, and once cooled to 23 ° C., development is performed.

Thereafter, a length measuring SEM (Hitachi S-860)
As a result of examining the line width distribution in the silicon wafer plane using (0), very good results similar to those in FIG. 1 were obtained. The method for forming a resist pattern according to the third embodiment of the present invention comprises the following steps.

The steps (1) to (4) are the same as the resist pattern forming method of the first embodiment. However, in the resist pattern forming method of the third embodiment, (5) once cooling to 23 ° C. After that, the silicon wafer is rotated by 180 ° C. by the coating cup of the resist coating and developing apparatus, and is again heated at 100 ° C. for 45 seconds using another different hot plate mounted on the resist coating and developing apparatus SK-80BW. Alms,
Development is performed after cooling to 23 ° C once.

Thereafter, a length measuring SEM (S-860 manufactured by Hitachi, Ltd.)
As a result of examining the line width distribution in the silicon wafer plane using (0), the line width distribution in the silicon wafer plane was 9 nm at 3σ as shown in FIG. (a) on AA 'traverse line, B-B' traverse line, C-C 'traverse line,
The line width distribution on the D-D 'crossing line is as shown in Fig. 2 (b).
Very good results were obtained.

The method of forming a resist pattern according to the fourth embodiment of the present invention comprises the following steps. (1)-(4)
The steps up to this are the same as the resist pattern forming method of the first embodiment. However, in the resist pattern forming method of the fourth embodiment, the cooling process is not performed during the PEB step (5), and the resist coating is performed. The silicon wafer is rotated 180 degrees by the coating cup of the developing device, and the resist coating and developing device S
Using another different hot plate mounted on the K-80BW, heat treatment was performed again at 100 ° C. for 45 seconds.
Development is carried out after cooling to ° C.

Thereafter, a length measuring SEM (S-860 manufactured by Hitachi, Ltd.)
As a result of examining the line width distribution in the plane of the silicon wafer by using (0), very good results similar to those in FIG. 2 were obtained. In the above embodiment, the case where a negative type chemically amplified resist is used has been described. However, the chemically amplified resist to be used is not limited to the negative type, and the present invention can be applied to a case where a positive type chemically amplified resist is used. It is.

[0028]

As is apparent from the above description, according to the present invention, there is an advantage that the distribution of the line width in the plane of the processing substrate can be made extremely simple, and it is extremely economical and economical. In addition, it is possible to provide a method of forming a resist pattern that can be expected to improve the reliability.

[Brief description of the drawings]

FIG. 1 is a diagram showing a line width distribution in a processing substrate according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a line width distribution in a processing substrate according to a third embodiment of the present invention.

FIG. 3 is a diagram showing a line width distribution in a processing substrate by a conventional resist pattern forming method.

Claims (3)

[Claims] A step of applying a chemically amplified resist on a processing substrate, a step of pre-baking the chemically amplified resist, a step of irradiating the chemically amplified resist with ionizing radiation, and a step of irradiating the chemically amplified resist with the ionized radiation. A resist pattern forming method including a post-exposure bake treatment step of a resist and a development step of the chemically amplified resist, wherein the post-exposure bake processing step includes at least two post-exposure bake treatments, and after the second and subsequent exposures A method for forming a resist pattern, comprising: rotating the processing substrate by an angle obtained by dividing 360 degrees by the number of post-exposure baking processes for each baking process. 2. The method according to claim 1, further comprising a step of cooling the chemically amplified resist between at least two of the post-exposure bake processing steps. 3. The method according to claim 1, wherein each of the at least two post-exposure bake treatment steps is performed using a different heating device.