JPH1188254A - Device for reducing power consumption of radio communication component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption remarkably by reducing power consumption in the transmission state, in the reception state and in the standby state respectively. SOLUTION: An internal multiple number of a digital signal processing component 11 incorporating a PLL being a component of a radio communication equipment is autonomously varied, a speed of an operating clock being an externally oscillated input CPUIN to a central arithmetic processing component 12 from an operating clock supply component 14 is controlled variable depending on a processing load, any of pluralities of operating clocks is selected according to the processing load of the component 12, and in the case that no other arithmetic processing is required than transmission and reception slots, the digital signal processing component 11, the central arithmetic processing component 12 and a voice coding decoding component 13 are subject to sleep control.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for reducing the power consumption of each element constituting a wireless communication device such as a commercial wireless communication device.

[0002]

2. Description of the Related Art FIG. 5 shows a configuration of a conventional business radio communication apparatus. In FIG. 5, a commercial wireless communication device includes a PLL built-in digital signal processing element 51 for modulating and demodulating a signal of a wireless line, and a digital signal processing element 51.
A central processing element 52 for performing call processing control / radio section control, a voice coding / decoding element 53 for coding and decoding voice signals, and a bus connection to the central processing element 52 , Central processing unit 52 and speech encoding
An operation clock supply element 54 that supplies an operation clock to the decoding element 53, an original crystal oscillator 55 of the operation clock supply element 54, and 4.8 to the digital signal processing element 51.
And an RF interface IC 56 for supplying a signal of MHz.

When the wireless communication apparatus is used, the multiplication factor of the internal frequency of the digital signal processing element 51 is fixed to 12 times, and the operation clock supplied from the operation clock supply element 54 to the central processing element 52 is set to 13 times. .824 MHz
, And the operation clock supplied to the voice encoding / decoding element 53 is fixed at 27.648 MHz, and all the elements are held in an active state.

[0004]

However, in the above-mentioned conventional wireless communication apparatus, all elements are active at the time of transmission and reception, and are in the same processing operation state at the time of standby as at the time of reception. There is a problem that power consumption increases.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and reduces the power consumption at the time of transmission, reception, and standby, thereby making it possible to greatly reduce the power consumption. It is an object of the present invention to provide a device for reducing power consumption of a mechanical element.

[0006]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a low power consumption apparatus according to the present invention autonomously variably controls the internal multiplication number of a digital signal processing element with a built-in PLL constituting a wireless communication device. And variably controlling an operation clock speed, which is an external oscillation input to the central processing element, according to a processing load, and selectively switching a plurality of input operation clocks according to the processing load of the element; The sleep control is performed on the digital signal processing element, the central processing element, and the speech encoding / decoding element which constitute the above.

According to the present invention, it is possible to reduce power consumption during transmission, reception, and standby.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a modulation / demodulation digital signal processing element having a built-in PLL constituting a radio communication device, and a central processing unit for performing call processing control, radio unit control, and man-machine control. An arithmetic processing element, and an audio encoding / decoding element that performs encoding and decoding of the audio signal, and performs transmission, reception, and selective switching to a transmission / reception mode by a mode control signal from the central processing element, An operation clock supply element for supplying an operation clock to the central processing element and the voice encoding / decoding element, and a multiplication factor of an internal frequency of the digital signal processing element is autonomously determined according to transmission and reception. It performs variable control and has the effect of optimizing the power consumption of the digital signal processing element.

According to a second aspect of the present invention, the operation clock supply element is controlled by the central processing element so that the operation clock supplied to the central processing element is variably controlled in accordance with the processing load of the central processing element. This has the effect of optimizing the power consumption of the central processing element.

According to a third aspect of the present invention, a frequency of an operation clock supplied to a voice encoding / decoding element selectively switched to a transmission, reception, or transmission / reception mode by a mode control signal from a central processing unit is set. It selectively switches between transmission, reception, and transmission / reception, and has the effect of reducing power consumption.

According to a fourth aspect of the present invention, when arithmetic processing other than transmission and reception slots does not occur, the multiplication factor of the digital signal processing element is minimized, and the frequency of the operating clock to the central processing element is minimized. In addition, the operation clock to the audio encoding / decoding element supply element is stopped, and the digital signal processing element, the central processing element, and the audio encoding / decoding element are subjected to sleep control. It has the effect of being able to reduce.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

(Embodiment 1) FIG. 1 is a functional block diagram showing a configuration in a case where Embodiment 1 according to the present invention is applied to a business wireless communication apparatus.

In FIG. 1, a radio communication apparatus modulates and demodulates a signal of a radio line and an RF interface IC.
A digital signal processing element 11 having a control function of autonomously varying a multiplication number of an internal frequency based on a 4.8 MHz signal supplied from the digital signal processing element 11;
A central processing unit 12 that is connected to a bus and performs call processing control, radio unit control, and man-machine control, and performs transmission and reception according to a mode control signal from the central processing unit 12 that encodes and decodes a voice signal and performs voice signal encoding and decoding. , An audio encoding / decoding element 13 that is selectively switched to a transmission / reception mode, and a bus connected to the central processing element 12, and an external oscillation input CPUIN (0.846 to 1
3.824 MHz operation clock) and 27.648 M for the audio encoding / decoding element 13.
An operation clock supply element 14 that supplies a high-speed operation clock of 1 Hz and a low-speed operation clock of 6.932 MHz, and a crystal oscillator 15 for original vibration of the operation clock supply element 14 are provided.

Next, the operation of the wireless communication apparatus configured as described above will be described with reference to FIGS.
First, the operation clock supply element 14 generates an original vibration from the crystal oscillator 15, and based on the original vibration, the operation clock supply element 14 controls the built-in frequency dividing circuit according to the processing load of the central processing element 12. 0.84 divided by 1/16
A 13.824 MHz external oscillation input CPUIN obtained by dividing the frequency from 6 to 1/1 is supplied to the central processing element 12, whereby the external oscillation input CPUIN to the central processing element 12 is processed from 0.846 to 13.824 MHz. The speed can be varied according to the load.

The 4.8 MHz signal from the RF interface IC 16 is supplied to the digital signal processing element 11, and the internal frequency of the digital signal processing element 11 is multiplied by the built-in PLL based on the 4.8 MHz signal. As shown in FIG. 3, variable control is performed autonomously according to reception demodulation and transmission modulation.

In FIG. 3, at time T0, the PLL incorporated in the digital signal processing element 11 is turned on, and at time T1, the multiplication factor of the internal frequency F of the digital signal processing element 11 is changed to F = F1, which is 12 times. That is, the operation clock frequency F1 of the digital signal processing element 11 is set to F1 =
The frequency is changed to 4.8 MHz × 12 = 57.6 MHz (60 mA).
The reception demodulation process is performed for (15 msec). And
At time T6, the multiplication factor of the internal frequency F of the digital signal processing element 11 is changed to F = F6, which is three times. That is, the operation clock frequency F6 of the digital signal processing element 11
To F6 = 4.8 MHz × 3 = 14.4 MHz (15 m
The frequency is changed to the frequency of A).
The transmission modulation processing is performed during T10 (4 + 15 msec). Next, at time T11, the multiplication factor of the internal frequency F of the digital signal processing element 11 is changed to F = F11, which is 12 times. That is, the operating clock frequency F11 of the digital signal processing element 11 is set to F11 = 4.8 MHz × 12 =
The frequency is changed to 57.6 MHz (60 mA), and the reception clock is subjected to the reception demodulation processing for a period of time T12 to T13 (5 msec) with this operation clock. Further, at time T14, the multiple of the internal frequency F of the digital signal processing element 11 is set to 2
Change to F = F14 which has been doubled. That is, the operating clock frequency F14 of the digital signal processing element 11 is set to F14 =
The frequency is changed to 4.8 MHz × 2 = 9.6 MHz (10 mA).
During (1 msec), handshaking with the central processing element 12 is performed. Then, at time T17, the PLL incorporated in the digital signal processing element 11 is turned off.

As described above, by autonomously changing the multiple of the internal frequency of the digital signal processing element 11 during reception and transmission, and changing the operation clock speed of the digital signal processing element 11, the series shown in FIG. Power consumption when performing the processing of (60 × 15) + (15 × 19)
+ (60 × 5) + (10 × 1) = 1495 (μAsec
/ Frame). On the other hand, in the conventional case without speed control, 60 × 40 = 2400 (μAsec / fl)
ame). As a result, power consumption in the present embodiment can be reduced by about 60% as compared with the conventional case.

On the other hand, the speech encoding / decoding element 13 has
27.648MHz high-speed operation clock and 6.932M
The low-speed operation clock of Hz is selectively switched and supplied according to the encoding and decoding operations of the audio encoding / decoding element 13 during transmission and reception.

For example, as shown in FIG. 2, when there is enough processing capacity at the time of transmission and reception within a frame of 90 ms, a high-speed operation clock of 27.648 MHz is used for encoding during transmission. In order to use a low-speed operation clock of 6.932 MHz for decoding, the operation clock is changed from high speed to low speed to high speed to low speed in accordance with the encoding and decoding operations of the audio encoding / decoding element 13. Selectively switch dynamically. Similarly, the encoding of the audio encoding / decoding element 13 is performed so that the low-speed operation clock of 6.932 MHz is used for encoding during reception and the high-speed operation clock of 27.648 MHz is used for decoding during reception. The operation clock is dynamically selectively switched from low speed to high speed to low speed to high speed in accordance with the encoding and decoding operations. At this time, the power consumption at high speed is 40 mA, and the power consumption at low speed is 1 mA. However, in the transmission / reception mode, it is always operated with a high-speed clock.

Thus, the audio encoding / decoding element 13
By selectively switching between transmission, reception, and transmission / reception modes according to a mode control signal from the central processing unit 12, power consumption of the speech encoding / decoding element 13 during transmission, reception, and transmission / reception can be optimized.

Table 1 shows the power consumption of the conventional digital signal processing element, central processing element, and voice encoding / decoding element without clock control, and the digital signal processing element according to the first embodiment with clock control. The result of comparison with the power consumption of the central processing element and the speech encoding / decoding element is shown.

[0023]

As is apparent from Table 1, it is recognized that power consumption during transmission, reception and standby in Embodiment 1 of the present invention can be significantly reduced.

(Embodiment 2) Next, the operation of sleep control in Embodiment 2 of the present invention will be described with reference to FIG. 1 and FIG.

First, in a state where no arithmetic processing other than the reception and transmission slots occurs (step S1), the digital signal processing element 11 sets the multiplication number of the internal PLL to 1,
The operation clock is reduced to 4.8 MHz, and the digital signal processing element 11 is put into the sleep state (step S2).
Next, after the speech encoding / decoding element 13 is set to the stop mode under the control of the central processing unit 12, the operation clock supply element 14 to the speech encoding / decoding element 13 6.
The supply of the operation clocks of 932 MHz and 27.648 MHz is stopped (step S3). Further, the frequency of the external oscillation input CPUIN to the central processing element 12 is reduced to 0.86 MHz, and the central processing element 12 is put into the sleep state (step S4).

In this state, the digital signal processing element 1
1 is activated every superframe cycle by an internal timer interrupt (superframe interrupt) (step S5). Further, the central processing element 12 is activated by a communication activation interrupt from the digital signal processing element 11 (step S6), and performs a super frame receiving operation (step S7). After the reception is completed, the digital signal processing element 11 and the central processing element 12 enter the sleep state again. The central processing element 12 is activated by an external timer interrupt having a period of 10 ms (step S8).
The frequency of PUIN is set to 13.824 MHz, and the presence or absence of a battery voltage and options is checked (step S9).

In response to a communication start interrupt, a key interrupt, and a press interrupt from the digital signal processing element 11 (step S10), the digital signal processing element 11,
Central processing element 12 and speech encoding / decoding element 13
Is activated (step S11). Then, transmission, reception or transmission / reception operation of the audio signal is performed (step S12),
After the processing is completed, the digital signal processing element 11, the central processing element 12, and the audio encoding / decoding element 13 enter the sleep state again.

According to the second embodiment as described above, the digital signal processing element 11, the central processing element 12, and the voice encoding / decoding element 13 are sleep-controlled to perform arithmetic processing other than the transmission and reception slots. Power consumption can be reduced to the utmost in a state where no noise occurs.

In the above description, a case has been described in which the low power consumption device of the present invention is applied to a commercial radio communication device. However, the present invention is not limited to this, and may be applied to other mobile communication devices. The same can be applied.

[0030]

As described above, according to the present invention, it is possible to autonomously variably control the internal multiplication factor of the digital signal processing element with a built-in PLL constituting the radio communication apparatus, and to control the central processing element. The operation clock speed as an external oscillation input can be variably controlled according to the processing load, and a plurality of input operation clocks can be selectively switched according to the processing load of the element. The sleep control of the digital signal processing element, the central processing element, and the voice encoding / decoding element that constitute the device can be performed. Therefore, there is an effect that power consumption during transmission, reception and standby can be reduced, and power consumption can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing the configuration of a commercial wireless communication device that realizes the device of the present invention;

FIG. 2 is an explanatory diagram of an operation of a speech encoding / decoding element according to Embodiment 1 of the present invention.

FIG. 3 is an operation explanatory diagram of the digital signal processing element according to the first embodiment of the present invention;

FIG. 4 is a flowchart showing an operation of sleep control according to Embodiment 2 of the present invention.

FIG. 5 is a functional block diagram showing a configuration of a conventional business wireless communication device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Digital signal processing element 12 Central processing element 13 Speech encoding / decoding element 14 Operation clock supply element 15 Crystal oscillator for original vibration 16 RF interface IC Document describing chemical formula etc.

[Table 1]

Claims (4)

[Claims] 1. A modulation / demodulation digital signal processing element with a built-in PLL constituting a wireless communication apparatus, a central processing element for performing call processing control, radio section control, and man-machine control, and encoding and decoding of a voice signal. And a speech encoding / decoding element that is selectively controlled to be switched to a transmission, reception, transmission / reception mode by a mode control signal from the central processing element, and the central processing element and the speech encoding / decoding element. And an operation clock supply element for supplying an operation clock to the digital signal processing element, wherein the multiplication factor of the internal frequency of the digital signal processing element is autonomously variably controlled according to transmission and reception. Power consumption device. 2. An operation clock supply element is controlled by a central processing element, whereby an operation clock supplied to the central processing element is variably controlled according to a processing load of the central processing element. Item 2. A device for reducing power consumption of a wireless communication device element according to Item 1. 3. A frequency of an operation clock supplied to an audio encoding / decoding element selectively switched to a transmission, reception, and transmission / reception mode by a mode control signal from a central processing unit according to transmission, reception, and transmission / reception. 2. The device for reducing power consumption of a wireless communication device according to claim 1, wherein the device is selectively switched. 4. In a state in which arithmetic processing other than transmission and reception slots does not occur, the multiplication number of the digital signal processing element is minimized, the frequency of the operation clock to the central processing element is minimized, and voice encoding / coding is performed. 2. The wireless communication device according to claim 1, wherein the operation clock to the decoding device supply device is stopped, and the digital signal processing device, the central processing unit, and the speech coding / decoding device are sleep-controlled. Low power consumption device.