JPH1187917A - Ceramic multilayered wiring board - Google Patents

Ceramic multilayered wiring board

Info

Publication number
JPH1187917A
JPH1187917A JP9238730A JP23873097A JPH1187917A JP H1187917 A JPH1187917 A JP H1187917A JP 9238730 A JP9238730 A JP 9238730A JP 23873097 A JP23873097 A JP 23873097A JP H1187917 A JPH1187917 A JP H1187917A
Authority
JP
Japan
Prior art keywords
layer
ceramic
layers
wiring board
metal plane
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9238730A
Other languages
Japanese (ja)
Other versions
JP3688444B2 (en
Inventor
Kazuya Nozu
一哉 野津
Yoshitoshi Nomura
俊寿 野村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Niterra Co Ltd
Original Assignee
NGK Spark Plug Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Spark Plug Co Ltd filed Critical NGK Spark Plug Co Ltd
Priority to JP23873097A priority Critical patent/JP3688444B2/en
Publication of JPH1187917A publication Critical patent/JPH1187917A/en
Application granted granted Critical
Publication of JP3688444B2 publication Critical patent/JP3688444B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a multilayered wiring board for preventing the short-circuit of a wide area metallization layer or the like electrically connected to a via and the wide area metallization layer adjacent through a relatively thin ceramic layer, even when the built-in via is deformed. SOLUTION: For this ceramic multilayered wiring board 1, metal plane layers 10 and 12 which are the wide area metallization layers and a wiring pattern 14 are provided between ceramic layers 2-8 whose thickness is respectively 50 μm, the upper end of via 18 penetrating through in a thickness direction inside the clearance 16 of the wiring pattern 14 is electrically connected with the metal plane layer 12 and an opening part 11 which is almost concentric with the via 18 is formed around a position crossing with the axial direction of the via 18 on the metal plane layer 10 adjacent to the metal plane layer 12 through the ceramic layer 4. Even when the via 18 is expanded or contracted and deformed along the axis by pressing in the thickens direction before baking and a heat contraction difference after the baking by forming the opening part 11, the short-circuit of the metal plane layers 10 and 12 with each other is prevented.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、複数で比較的薄肉
のセラミック層の間に広域メタライズ層と配線パターン
とが積層して形成されるセラミック多層配線基板に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic multilayer wiring board formed by laminating a wide metallization layer and a wiring pattern between a plurality of relatively thin ceramic layers.

【0002】[0002]

【従来の技術】一般に、セラミック多層配線基板を得る
には、図5(A)に示すように、複数のグリーンシート8
2〜84の間に略平面方向全体に広がる広域メタライズ
層用のメタライズペースト層86,88と、図示しない
配線パターン用のメタライズペースト層とを積層する。
また、グリーンシート84において上記ペースト層88
と図示しないペースト層とを厚さ方向に接続するビア用
のインクメタライズ89を形成する。そして、グリーン
シート82〜84やメタライズペースト層86,88等
を積層し、得られた積層体80をプレスしてから焼成す
る。焼成後において、上記グリーンシート82〜84は
セラミック層92〜94に、上記メタライズペースト層
86,88は例えば電源用のメタルプレーン層等の広域
メタライズ層96,98に、且つ上記インクメタライズ
89はビア99となってセラミック多層配線基板90を
構成する。
2. Description of the Related Art Generally, in order to obtain a ceramic multilayer wiring board, as shown in FIG.
Metallization paste layers 86 and 88 for a wide area metallization layer and a metallization paste layer for a wiring pattern (not shown), which are spread in substantially the entire plane direction between 2 and 84, are laminated.
In the green sheet 84, the paste layer 88
A via ink metallization 89 is formed to connect the paste layer (not shown) with a paste layer (not shown) in the thickness direction. Then, the green sheets 82 to 84, the metallized paste layers 86 and 88, and the like are laminated, and the obtained laminate 80 is pressed and fired. After firing, the green sheets 82 to 84 are formed into ceramic layers 92 to 94, the metallized paste layers 86 and 88 are formed into wide metallized layers 96 and 98 such as a metal plane layer for power supply, and the ink metallized 89 is formed into vias. The reference numeral 99 indicates a ceramic multilayer wiring board 90.

【0003】[0003]

【発明が解決すべき課題】ところで、上記積層体80を
焼成する前に行うプレスによる厚さ方向への圧縮による
相対的な変形差や、焼成後の相対的な熱収縮差により、
以下のような問題点を生じることがある。即ち、図5
(B)に示すように、ビア99がその軸方向に沿って膨張
(伸長)し、広域メタライズ層98の一部を突き上げる。
このため、ビア99の直上の位置において広域メタライ
ズ層98と広域メタライズ層96が接触して短絡するこ
とがある。この際、ビア99の上方の基板90の上面9
1には破線で示す凸部100が形成されることもある。
The relative deformation difference due to compression in the thickness direction by a press performed before firing the laminate 80 and the relative heat shrinkage difference after firing,
The following problems may occur. That is, FIG.
As shown in (B), the via 99 expands along its axial direction.
(Extend) and push up a part of the wide area metallization layer 98.
Therefore, the wide area metallized layer 98 and the wide area metallized layer 96 may be short-circuited at a position immediately above the via 99. At this time, the upper surface 9 of the substrate 90 above the via 99
1 may be formed with a convex portion 100 indicated by a broken line.

【0004】また、図5(C)に示すように、逆にビア9
9が軸方向に沿って縮むため、広域メタライズ層96,
98の一部が下向きに凹む。このため、その位置におい
て広域メタライズ層96と広域メタライズ層98が接触
して短絡することもある。この場合には、配線基板90
の上面91に凹み102が形成されることもある。これ
らの凸部100や凹み102は、セラミック層92,9
3が薄肉になるほど顕著に表れ易い傾向がある。この広
域メタライズ層96,98間の短絡により、配線基板9
0は当初の回路を形成できず、本来の機能を果たせなく
なる。また、該基板90の上面91に上記凸部100や
凹み102が形成されると、その位置にICチップ等の
電子部品が正確に搭載できなくなるという問題もあっ
た。特に、このような問題はセラミック層の厚さが60
μm以下という薄いセラミック層において顕著であっ
た。
[0005] As shown in FIG.
9 shrinks along the axial direction, so that a wide area metallization layer 96,
Part of 98 is recessed downward. For this reason, the wide area metallization layer 96 and the wide area metallization layer 98 may come into contact with each other at that position and cause a short circuit. In this case, the wiring board 90
In some cases, a recess 102 is formed in the upper surface 91 of the substrate. These projections 100 and depressions 102 are formed by the ceramic layers 92, 9.
No. 3 tends to appear remarkably as it becomes thinner. The short circuit between the wide area metallization layers 96 and 98 causes the wiring board 9
0 cannot form the original circuit and cannot perform its original function. Further, when the protrusions 100 and the recesses 102 are formed on the upper surface 91 of the substrate 90, there is a problem that electronic components such as IC chips cannot be accurately mounted at the positions. In particular, such a problem is caused when the thickness of the ceramic layer is 60
This was remarkable in a ceramic layer as thin as μm or less.

【0005】本発明は、以上の従来の技術が有する問題
点を解決し、ビアの軸方向の変形が生じてもメタルプレ
ーン層のような広域メタライズ層同士、又は広域メタラ
イズ層と配線パターンとが短絡しないようにすると共
に、併せて上面に電子部品を正確に搭載でき、且つセラ
ミック層を薄肉化し得るセラミック多層配線基板を提供
することを目的とする。
[0005] The present invention solves the above-mentioned problems of the prior art. Even if the vias are deformed in the axial direction, the wide metallized layers such as the metal plane layers, or the wide metallized layers and the wiring patterns can be formed. It is an object of the present invention to provide a ceramic multilayer wiring board that can prevent a short circuit, can accurately mount an electronic component on an upper surface, and can reduce the thickness of a ceramic layer.

【0006】[0006]

【課題を解決するための手段】本発明は、上記課題を解
決するため、ビアが導通する広域メタライズ層又は配線
パターンにセラミック層を介して隣接する広域メタライ
ズ層に、ビアの変形を緩衝するための開口部を形成する
ことに着想して成されたものである。即ち、本発明のセ
ラミック多層配線基板は、複数のセラミック層の間に広
域メタライズ層と配線パターンとが形成されるセラミッ
ク多層配線基板であって、上記広域メタライズ層同士、
又は配線パターン同士、或いは広域メタライズ層と配線
パターンとの間を基板の厚さ方向に導通するビアと、上
記ビアの少なくとも一端が導通する広域メタライズ層又
は配線パターンにセラミック層を介して隣接する広域メ
タライズ層における上記ビアの軸方向と交差する位置を
含んで上記広域メタライズ層に設けた開口部と、を有す
ることを特徴とする。
SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a method for buffering via deformation in a wide metallized layer or a wide metallized layer adjacent to a wiring pattern via a ceramic layer. Is formed with an idea of forming the opening. That is, the ceramic multilayer wiring board of the present invention is a ceramic multilayer wiring board in which a wide metallization layer and a wiring pattern are formed between a plurality of ceramic layers, and the wide metallization layers are
Alternatively, a via that conducts between the wiring patterns or between the global metallization layer and the wiring pattern in the thickness direction of the substrate, and a wide area adjacent to the global metallization layer or the wiring pattern through which at least one end of the via conducts via a ceramic layer. An opening provided in the wide area metallization layer including a position in the metallization layer that intersects the axial direction of the via.

【0007】これによれば、ビアが軸方向に膨張又は収
縮して該ビアと接続する広域メタライズ層等の一部が変
形しても、この変形部分は隣接する広域メタライズ層に
設けた上記開口部付近に留まるので、広域メタライズ層
同士等の短絡を防止できる。また、係る開口部における
広域メタライズ層の厚さ分だけ、配線基板の上面への変
形が緩和されるので、電子部品を上面に正確に搭載する
こともできる。また、本発明には、上記開口部の直径又
は幅が、前記ビアの直径の2倍以上であるセラミック多
層配線基板も含まれる。ここで2倍以上としたのは、2
倍未満にすると短絡の防止が不十分になることがあり得
るためである。これによれば、前記短絡を一層確実に防
止することができる。
According to this, even if the via expands or contracts in the axial direction and a part of the wide metallization layer or the like connected to the via is deformed, the deformed part is formed by the opening provided in the adjacent wide metallization layer. Therefore, short circuit between the wide area metallized layers can be prevented. Further, the deformation of the upper surface of the wiring board is reduced by the thickness of the wide metallization layer in the opening, so that the electronic component can be accurately mounted on the upper surface. The present invention also includes a ceramic multilayer wiring board in which the diameter or width of the opening is at least twice the diameter of the via. Here, the reason for making the value twice or more is 2
If the number is less than twice, the prevention of short circuit may be insufficient. According to this, the short circuit can be more reliably prevented.

【0008】更に、上記ビアと導通する広域メタライズ
層又は配線パターンと、この広域メタライズ層又は配線
パターンと隣接する広域メタライズ層との間に形成され
たセラミック層の厚さが60μm以下であるセラミック
多層配線基板も含まれる。これによれば、セラミック層
を薄肉化しても前記短絡を容易に防止できるため、厚さ
方向により多くの配線パターンを有する多層配線基板を
提供することができる。尚、セラミック層の厚さが60
μmを超えるとビアが変形しても前記短絡を生じにくく
なるので、上記の60μm以下としたものである。更
に、前記ビアが複数個互いに平行且つ隣接して設けら
れ、且つ前記開口部がこれらの各ビアの軸方向と交差す
る各位置を含んで前記広域メタライズ層に設けられたセ
ラミック多層配線基板とすることもできる。これによれ
ば、互いに隣接する複数のビアによる広域メタライズ層
等の変形を1つの開口部によって吸収し、該広域メタラ
イズ層等と隣接する広域メタライズ層との短絡を防止す
ることが可能となる。
[0008] Furthermore, a ceramic multilayer in which the thickness of a ceramic layer formed between the wide metallization layer or wiring pattern that is electrically connected to the via and the wide metallization layer adjacent to the wide metallization layer or wiring pattern is 60 μm or less. A wiring board is also included. According to this, even if the ceramic layer is thinned, the short circuit can be easily prevented, so that a multilayer wiring board having more wiring patterns in the thickness direction can be provided. The thickness of the ceramic layer is 60
When the thickness exceeds μm, the short circuit hardly occurs even if the via is deformed. Therefore, the thickness is set to 60 μm or less. Further, a ceramic multilayer wiring board is provided in which the plurality of vias are provided in parallel with and adjacent to each other, and the opening is provided in the wide area metallization layer including each position intersecting with the axial direction of each via. You can also. According to this, the deformation of the wide area metallization layer or the like due to a plurality of vias adjacent to each other is absorbed by one opening, and it is possible to prevent a short circuit between the wide area metallization layer or the like and the adjacent wide area metallization layer.

【0009】また、前記開口部が、前記ビアの一端が導
通する広域メタライズ層又は配線パターンにセラミック
層を介して隣接する互いに平行な複数の広域メタライズ
層における上記ビアの軸方向と交差する各位置にそれぞ
れ設けられたセラミック多層配線基板とすることもでき
る。これによれば、ビアによる広域メタライズ層等の変
形が大きくても、セラミック層を挟んで隣接する複数の
広域メタライズ層に設けた各開口部内において、2層以
上の広域メタライズ層間における短絡を防止することが
可能となる。この場合、各開口部は互いに略同心となる
位置に設けられる。また、比較的ビアに近接する開口部
と離隔する開口部の寸法を相違させることにより、短絡
の防止と広域メタライズ層の面積の低減を抑えることが
可能となる。
[0009] Further, the opening may be located at a position intersecting the axial direction of the via in a wide area metallization layer or a plurality of parallel area metallization layers adjacent to the wiring pattern via a ceramic layer to one end of the via. May be ceramic multilayer wiring boards provided respectively. According to this, even if deformation of the wide area metallization layer or the like due to the via is large, a short circuit between two or more wide area metallization layers is prevented in each opening provided in a plurality of wide area metallization layers adjacent to each other with the ceramic layer interposed therebetween. It becomes possible. In this case, the openings are provided at positions substantially concentric with each other. In addition, by making the size of the opening relatively close to the via and the size of the opening separated from the via relatively small, it is possible to prevent short-circuiting and suppress the reduction of the area of the wide area metallization layer.

【0010】更に、前記開口部が、前記ビアの両端がそ
れぞれ導通する広域メタライズ層又は配線パターンにセ
ラミック層を介して隣接する基板の厚さ方向に離隔した
各広域メタライズ層における上記ビアの軸方向と交差す
る位置を含んでそれぞれ設けられたセラミック多層配線
基板とすることもできる。これによれば、ビア両端の変
形により基板の厚さ方向に離隔して配置された広域メタ
ライズ層又は配線パターンと、これらにセラミック層を
介して隣接する広域メタライズ層との短絡を防止するこ
とが可能となる。
[0010] Further, the opening may be formed in a wide metallization layer in which both ends of the via are electrically connected or in a wide metallization layer separated from a wiring pattern in a thickness direction of a substrate adjacent to the wiring pattern via a ceramic layer. Ceramic multilayer wiring boards provided so as to include positions intersecting with. According to this, it is possible to prevent a short circuit between the wide area metallized layer or the wiring pattern which is spaced apart in the thickness direction of the substrate due to deformation of both ends of the via, and the wide area metallized layer adjacent thereto via the ceramic layer. It becomes possible.

【0011】更にまた、前記開口部が平面視で略円形又
は略正多角形であり、且つ平面視で前記ビアの中心軸と
略同心となる前記広域メタライズ層の位置に上記開口部
が設けられたセラミック多層配線基板とすることもでき
る。これによれば、前記短絡を確実に予防することが可
能となる。尚、本明細書において、広域メタライズ層と
は配線基板の厚さ方向に直交する平面方向の略全面に渉
って導体が敷設される、例えば電源用のメタルプレーン
層のようなものを指す。
Further, the opening is provided at a position of the wide metallization layer which is substantially circular or substantially regular polygonal in a plan view and which is substantially concentric with a center axis of the via in a plan view. It is also possible to use a ceramic multilayer wiring board. According to this, it is possible to reliably prevent the short circuit. In this specification, the wide area metallization layer refers to a metal plane layer for a power supply, for example, in which a conductor is laid over substantially the entire surface in a plane direction perpendicular to the thickness direction of the wiring board.

【0012】[0012]

【実施の形態】以下において本発明の実施に好適な形態
を図面と共に説明する。図1は本発明のセラミック多層
配線基板1に関する。同図(A)の断面図に示すように、
この配線基板1は、絶縁層となる複数のセラミック層2
〜8の間に、例えば電源用のメタルプレーン層(広域メ
タライズ層)10,12と、配線パターン14とが配設
されている。上記セラミック層2〜8は、それぞれの厚
さが50μmで、主にアルミナを含むグリーンシートを
焼成したものであり、メタルプレーン層10,12と、
配線パターン14はタングステン(W)やモリブデン(M
o)等の高融点金属からなるペースト層を焼成したもの
である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 relates to a ceramic multilayer wiring board 1 of the present invention. As shown in the sectional view of FIG.
This wiring board 1 includes a plurality of ceramic layers 2 serving as insulating layers.
For example, metal plane layers (wide-area metallization layers) 10 and 12 for power supply and a wiring pattern 14 are disposed between the power-supply metal layers. Each of the ceramic layers 2 to 8 has a thickness of 50 μm and is obtained by firing a green sheet mainly containing alumina.
The wiring pattern 14 is made of tungsten (W) or molybdenum (M
This is obtained by firing a paste layer made of a high melting point metal such as o).

【0013】上記配線パターン14内には、所要の直径
を有する空隙部16が形成され、この空隙部16の略中
心を基板1の厚さ方向に沿ってビア18が貫通する。こ
のビア18は、その上端を下側のメタルプレーン層12
に接続し、図示しない下端を他の配線パターン又はメタ
ルプレーン層等の広域メタライズ層に接続して、これら
の間を導通している。尚、このビア18は、セラミック
層6,8の間における上記空隙16内の高さにおいて、
その上下の部分を接続する図示しないビアカバを介在さ
せている。また、上記空隙16は、ビア18と配線パタ
ーン14との間を絶縁するためのもので、配線パターン
14となる金属ペースト層をスクリーン印刷して形成す
る際に同時に形成される。
A void 16 having a required diameter is formed in the wiring pattern 14, and a via 18 penetrates substantially the center of the void 16 along the thickness direction of the substrate 1. The via 18 has an upper end formed on the lower metal plane layer 12.
, And the lower end (not shown) is connected to another wiring pattern or a wide area metallization layer such as a metal plane layer, and conduction is established between these. The via 18 has a height in the gap 16 between the ceramic layers 6 and 8.
A via cover (not shown) connecting the upper and lower parts is interposed. The gap 16 serves to insulate between the via 18 and the wiring pattern 14 and is formed at the same time when the metal paste layer serving as the wiring pattern 14 is formed by screen printing.

【0014】そして、図示で上側のメタルプレーン層1
0におけるビア18の軸方向が交差する位置を含む付近
には、円形の開口部11が形成される。図1(B)に示す
ように、この開口部11は、平面視においてビア18と
略同心の位置に形成される。尚、係る開口部11は、メ
タルプレーン層10となる金属ペースト層をスクリーン
印刷して形成する際に、同時に形成されたものである。
係る開口部11を形成することにより、前述したよう
に、ビア18が軸方向に相対的に膨張して下側のメタル
プレーン層12を突き上げた場合でも、図1(A)中の破
線で示すように、その突き上げた頂部分は開口部11に
接近するか開口部11内に入るが、上側のメタルプレー
ン層10には接触しない。また、ビア18が軸方向に相
対的に収縮してメタルプレーン層12,10を下向きに
引張った場合でも、図1(A)中の一点鎖線で示すよう
に、開口部11が上側のメタルプレーン層10における
変形部の最低部分となるため、下側のメタルプレーン層
12に接触しない。
The upper metal plane layer 1 shown in FIG.
The circular opening 11 is formed in the vicinity including the position where the axial direction of the via 18 at 0 crosses. As shown in FIG. 1B, the opening 11 is formed at a position substantially concentric with the via 18 in plan view. The opening 11 is formed at the same time when the metal paste layer that becomes the metal plane layer 10 is formed by screen printing.
By forming such an opening 11, as described above, even when the via 18 expands relatively in the axial direction and pushes up the lower metal plane layer 12, it is indicated by the broken line in FIG. As described above, the raised top portion approaches or enters the opening 11, but does not contact the upper metal plane layer 10. Even when the via 18 contracts relatively in the axial direction and pulls the metal plane layers 12 and 10 downward, as shown by the dashed line in FIG. Since it is the lowest part of the deformed portion in the layer 10, it does not contact the lower metal plane layer 12.

【0015】従って、基板1の製造工程においてビア1
8が上記何れの変形を生じても、上下のメタルプレーン
層10,12は、従来のように互いに短絡することはな
い。尚、上記開口部11の直径は0.5mmであり、且つ
ビア18の直径0.1mmの5倍である。開口部11の直
径は、前記短絡を防ぐため、少なくともビア18の直径
の2倍以上とする必要があり、望ましくは3倍以上であ
る。また、ビア18と接続されるのは、上記メタルプレ
ーン層12に限らず、配線パターン14と同様の配線パ
ターンであっても良い。ビア18の変形によって短絡を
生じるのは、セラミック層4を挟んで隣接するメタルプ
レーン層10が存在するためである。
Therefore, in the manufacturing process of the substrate 1, the via 1
No matter which of the above deformations occurs, the upper and lower metal plane layers 10 and 12 do not short-circuit each other as in the conventional case. The diameter of the opening 11 is 0.5 mm, which is five times the diameter of the via 18 of 0.1 mm. The diameter of the opening 11 must be at least twice as large as the diameter of the via 18 in order to prevent the short circuit, and is preferably three times or more. The connection with the via 18 is not limited to the metal plane layer 12, but may be a wiring pattern similar to the wiring pattern 14. The short circuit occurs due to the deformation of the via 18 because the metal plane layer 10 adjacent to the ceramic layer 4 is present.

【0016】図2は、異なる形態の開口部に関し、同図
(A)は前記と同じビア18に対し、その中心を略同心と
する隅の丸い正方形状の開口部20を示す。また、図2
(B)に示すように、2本のビア18,18が互いに平行
して隣接する場合には、メタルプレーン層10に各ビア
18を略中心として囲む長円形の開口部22を形成す
る。更に、図2(C)に示すように、同様な場合におい
て、各ビア18を略中心として囲む2つの円形部分2
6,26を繋いだまゆ形状の開口部24を形成しても良
い。
FIG. 2 relates to different types of openings.
(A) shows a square-shaped opening 20 with rounded corners whose center is substantially concentric with the same via 18 as described above. FIG.
As shown in (B), when the two vias 18 are adjacent to each other in parallel with each other, an oval opening 22 is formed in the metal plane layer 10 so as to surround each via 18 substantially at the center. Further, as shown in FIG. 2 (C), in a similar case, two circular portions
An opening 24 in the form of a cocoon may be formed by connecting 6 and 26.

【0017】特に、この開口部24のように、各ビア1
8を略中心とする円形部分26を活用することにより、
メタルプレーン層10の面積を余り減らさずに、前記短
絡を予防することができるので望ましい。そして、3本
以上のビア18が互いに平行して隣接する場合には、上
記開口部22に倣った変形長円形の開口部、或いは図2
(D)に示すような略L形状の開口部28にしたり、更に
は上記円形部分26を活用した略L形状や、略へ形状等
の変形した形状の開口部を形成することが望ましい。
In particular, like the opening 24, each via 1
By utilizing the circular portion 26 having the center at approximately 8,
This is desirable because the short circuit can be prevented without significantly reducing the area of the metal plane layer 10. When three or more vias 18 are adjacent to each other in parallel with each other, a modified oval opening following the opening 22 or FIG.
It is desirable to form an opening 28 having a substantially L-shape as shown in (D), or an opening having a deformed shape such as a substantially L-shape utilizing the above-mentioned circular portion 26 or a substantially rectangular shape.

【0018】図3は、異なる形態のセラミック多層配線
基板に関する。同図(A)に示す配線基板30は、厚さが
それぞれ50μmのセラミック層31〜35の間に、3
層のメタルプレーン層(広域メタライズ層)36〜38と
配線パターン39とを配設している。この配線パターン
39の空隙40内を垂直に貫通するビア41の上端は、
上から3層目のメタルプレーン層38と接続して導通し
ている。該ビア41の下端は、図示しない配線パターン
又はメタルプレーン層と導通している。また、上から1
層,2層目のメタルプレーン層36,37におけるビア
41の軸方向と交差する位置を含む付近には、それぞれ
円形の開口部42,43がビア41と同心状に形成され
ている。この場合、ビア41に近接する開口部43の直
径が、ビア18から離れた開口部42よりも比較的小さ
く設定されている。但し、この開口部43の直径は、ビ
ア41の直径の2倍以上である。
FIG. 3 relates to a different form of ceramic multilayer wiring board. The wiring board 30 shown in FIG. 3A has three ceramic layers 31 to 35 each having a thickness of 50 μm.
Metal plane layers (wide area metallization layers) 36 to 38 and wiring patterns 39 are provided. The upper end of the via 41 penetrating vertically through the space 40 of the wiring pattern 39 is
It is electrically connected to the third metal plane layer 38 from the top. The lower end of the via 41 is electrically connected to a wiring pattern (not shown) or a metal plane layer. Also, 1 from the top
Circular openings 42 and 43 are formed concentrically with the via 41 in the vicinity including the position intersecting the axial direction of the via 41 in the layers and the second metal plane layers 36 and 37. In this case, the diameter of the opening 43 close to the via 41 is set relatively smaller than that of the opening 42 remote from the via 18. However, the diameter of the opening 43 is twice or more the diameter of the via 41.

【0019】そして、配線基板30の製造工程におい
て、ビア41がその軸方向に沿って相対的に膨張した場
合、メタルプレーン層38が突き上げられても、図中の
破線で示すように、その突き上った頂部分は開口部43
の付近において略留まる。また、これに応じて該開口部
43が上方へ円錐状に盛り上がっても、その変形部分の
上端は最上層のメタルプレーン層36の開口部42付近
に留まる。従って、3層のメタルプレーン層36〜38
の相互間において、短絡を招来することはない。一方、
配線基板30の製造工程において、ビア41がその軸方
向に沿って相対的に収縮した場合、図中の一点鎖線で示
すように、上から3層目のメタルプレーン層38が下向
きに引っ張られる。すると、このプレーン層38の凹み
の上方にて、2層目のメタルプレーン層37における変
形部の最下端となる開口部43が留まる。且つ、最上層
のメタルプレーン層36の開口部42は、開口部43よ
りも大径であるため、殆んど下方へは変形しない。
In the manufacturing process of the wiring board 30, when the via 41 relatively expands along the axial direction, even if the metal plane layer 38 is pushed up, as shown by a broken line in FIG. The ascending top part is the opening 43
Approximately stays near. Even if the opening 43 rises conically upward, the upper end of the deformed portion remains near the opening 42 of the uppermost metal plane layer 36. Therefore, the three metal plane layers 36 to 38
No short circuit is caused between them. on the other hand,
In the manufacturing process of the wiring board 30, when the via 41 relatively shrinks along its axial direction, the third metal plane layer 38 from the top is pulled downward as shown by the dashed line in the figure. Then, the opening 43 that is the lowermost end of the deformed portion in the second metal plane layer 37 remains above the recess of the plane layer 38. In addition, since the opening 42 of the uppermost metal plane layer 36 has a larger diameter than the opening 43, it hardly deforms downward.

【0020】従って、上記開口部42,43を形成する
ことにより、3層のメタルプレーン層36〜38が隣接
する配線基板30においても、これら相互間の短絡を確
実に予防することができる。また、配線基板30の上面
30aの平坦性も保たれるので、上面30aに各種の電
子部品を正確に搭載することができる。尚、開口部4
2,43は上記とは逆に開口部42を開口部43より小
径にしても、ビア41が軸方向に収縮する場合に対応し
て短絡を防ぐことができる。また、ビア41に近接する
開口部43を円形とし、他方の開口部42を正多角形等
の非円形とすることもできる。更に、配線基板の厚さ方
向に沿って、3つ以上の開口部を略同心状にして各メタ
ルプレーン層に形成することもできる。更に、ビア41
と導通するメタルプレーン層38が、配線パターン39
と同様な配線パターンであっても上記の短絡を防止する
ことができる。
Therefore, by forming the openings 42 and 43, even in the wiring board 30 in which the three metal plane layers 36 to 38 are adjacent to each other, a short circuit between them can be reliably prevented. Moreover, since the flatness of the upper surface 30a of the wiring board 30 is also maintained, various electronic components can be accurately mounted on the upper surface 30a. The opening 4
Conversely, even if the diameter of the opening 42 is smaller than that of the opening 43, the short circuit can be prevented in correspondence with the case where the via 41 contracts in the axial direction. Further, the opening 43 close to the via 41 may be circular, and the other opening 42 may be non-circular such as a regular polygon. Furthermore, three or more openings can be formed in each metal plane layer so as to be substantially concentric along the thickness direction of the wiring board. In addition, via 41
The metal plane layer 38 that is electrically connected to the wiring pattern 39
Even with a wiring pattern similar to that described above, the above short circuit can be prevented.

【0021】図3(B)は別のセラミック多層配線基板4
5に関する。この基板45は、上方から各厚さが50μ
mのセラミック層46〜48,49a〜49e,48′
〜46′と、これらの間に上・下部に2層のメタルプレ
ーン層54,56及び56′,54′(広域メタライズ
層)、及び、6層の配線パターン50a〜50fとが厚
さ方向に沿って上下対称に積層されている。各配線パタ
ーン50a〜50fの所定の位置に形成された空隙51
内を、ビア52が貫通する。該ビア52の上下端は、上
下のメタルプレーン層56,56′に接続され、これら
を互いに導通している。
FIG. 3B shows another ceramic multilayer wiring board 4.
Regarding 5. The substrate 45 has a thickness of 50 μm from above.
m ceramic layers 46-48, 49a-49e, 48 '
46 ′, and two metal plane layers 54, 56 and 56 ′, 54 ′ (wide metallization layer) above and below, and six wiring patterns 50a to 50f in the thickness direction. The layers are stacked vertically symmetrically. A void 51 formed at a predetermined position of each of the wiring patterns 50a to 50f
A via 52 penetrates the inside. The upper and lower ends of the via 52 are connected to upper and lower metal plane layers 56 and 56 ', and these are electrically connected to each other.

【0022】また、最上・最下層のメタルプレーン層5
4,54′における上記ビア52の軸方向と交差する位
置を含む付近には、平面視においてビア52と略同心状
の円形の開口部58,58′が形成されている。上記ビ
ア52は、配線基板45の厚さ方向に沿って長大である
ため、焼成前のプレス時又は焼成後のセラミック層49
a〜49eとの収縮差により、その軸方向に沿って膨張
や収縮を生じ易い。例えば、ビア52が軸方向に沿って
相対的に膨張した場合、図中の破線で示すように上下の
メタルプレーン層56,56′を突き上げ、突き下げ
る。しかし、この変形部分の最上・最下端は各開口部5
8,58′付近に留まる。このため、上方の各メタルプ
レーン層54,56同士と、下方の各メタルプレーン層
54′,56′同士は互いに短絡することがない。
The uppermost and lowermost metal plane layers 5
In the vicinity including the position at which the via 52 intersects with the axial direction of the via 52, circular openings 58, 58 ′ that are substantially concentric with the via 52 in plan view are formed. Since the vias 52 are long along the thickness direction of the wiring board 45, the vias 52 are pressed at the time of pressing before firing or the ceramic layers 49 after firing.
Due to the difference in shrinkage from a to 49e, expansion and shrinkage tend to occur along the axial direction. For example, when the via 52 relatively expands in the axial direction, the upper and lower metal plane layers 56 and 56 'are pushed up and down as shown by broken lines in the figure. However, the uppermost and lowermost ends of this deformed portion are each opening 5
Stay near 8,58 '. Therefore, the upper metal plane layers 54 and 56 and the lower metal plane layers 54 'and 56' do not short-circuit with each other.

【0023】また、逆にビア52が軸方向に沿って相対
的に収縮した場合、図中の一点鎖線で示すように、ビア
52と導通する上下のメタルプレーン層56,56′も
中央側に引っ張られる。これに連れて最上・最下層のメ
タルプレーン層54,54′も同様に変形するが、各変
形部には開口部58,58′が形成されているため、上
記と同様に短絡を生じない。しかも、配線基板45の上
面54aには、開口部58によりビア52が変形しても
凸部や凹みが形成されにくい。従って、該上面54aに
搭載されるICチップ等の電子部品を正確に固着するこ
とも可能となる。尚、ビア52と上下で導通するメタル
プレーン層56,56′が、配線パターン50nに変っ
ても上記と同様の効果を得ることができる。
On the contrary, when the via 52 is relatively contracted along the axial direction, the upper and lower metal plane layers 56 and 56 'which are electrically connected to the via 52 are also located on the center side, as shown by the dashed line in the figure. Pulled. Accordingly, the uppermost and lowermost metal plane layers 54 and 54 'are similarly deformed. However, since the openings 58 and 58' are formed in the respective deformed portions, no short circuit occurs as described above. In addition, even if the via 52 is deformed by the opening 58, a convex portion or a dent is not easily formed on the upper surface 54 a of the wiring board 45. Therefore, it is also possible to accurately fix electronic components such as an IC chip mounted on the upper surface 54a. It should be noted that the same effects as described above can be obtained even if the metal plane layers 56 and 56 ′ that conduct vertically with the via 52 are changed to the wiring pattern 50 n.

【0024】本発明は以上において説明した各形態に限
定されるものではない。例えば、図4に示すように、複
数のセラミック層61〜65の中間に広域メタライズ層
66,68を配設し、その上下に配線パターン70,7
4を配設して積層したセラミック多層配線基板60にも
適用される。各広域メタライズ層66,68には、上方
又は下方からビア72,76が接続され、図示しない広
域メタライズ層等と互いに導通する。各ビア72,76
は、配線パターン70,74に形成された空隙71,7
5内の略中心を垂直に貫通する。
The present invention is not limited to the embodiments described above. For example, as shown in FIG. 4, wide metallization layers 66 and 68 are provided in the middle of a plurality of ceramic layers 61 to 65, and wiring patterns 70 and 7 are formed above and below them.
Also, the present invention is applied to a ceramic multilayer wiring board 60 in which the components 4 are arranged and laminated. Vias 72 and 76 are connected to the wide area metallization layers 66 and 68 from above or below, and are electrically connected to a wide area metallization layer and the like (not shown). Each via 72, 76
Are the voids 71, 7 formed in the wiring patterns 70, 74.
5 vertically penetrates substantially the center.

【0025】そして、上方の広域メタライズ層66にお
ける下方のビア76の軸方向と交差する位置を含む付近
には円形の開口部67が、下方の広域メタライズ層68
における上方のビア72の軸方向と交差する位置を含む
付近には円形の開口部69がそれぞれ形成されている。
従って、図中の破線や一点鎖線で示すように、各ビア7
1,76が前記同様に膨張や収縮変形しても、互いに平
行な広域メタライズ層66,68は、各開口部67,6
9によって相互間に短絡を生じない。尚、広域メタライ
ズ層66,68の何れか一方が配線パターンであって
も、残る他方の広域メタライズ層に開口部を形成してお
くと、両者間の短絡を防げることも明らかである。
A circular opening 67 is formed in the vicinity of the upper wide metallization layer 66 including a position intersecting with the axial direction of the lower via 76, and the lower wide metallization layer 68 is provided.
A circular opening 69 is formed in the vicinity including the position intersecting the axial direction of the upper via 72 in FIG.
Therefore, as shown by a broken line and a dashed line in the figure, each via 7
Even if the first and second members 76 expand and contract in the same manner as described above, the wide area metallized layers 66 and 68 which are parallel to each other form the respective openings 67 and
9 prevents short circuits between each other. It is apparent that even if one of the wide metallization layers 66 and 68 is a wiring pattern, a short circuit between the two can be prevented by forming an opening in the other wide metallization layer.

【0026】また、本多層配線基板中のセラミック層に
は、前記アルミナに限らず、窒化アルミニウム、ガラス
セラミック、ムライト等を用いることもできる。更に、
広域メタライズ層や配線パターンの材質も前記WやMo
に限らず、CuやCo及びこれらをベースとする合金、
Mo−Mn、Ag、Ag−Pd、Ag−Pt等を適用す
ることも可能である。更に、本発明の多層配線基板に
は、その上/下面にピンを植設するピングリッドアレイ
型配線基板や、上面に複数の電子部品や素子を搭載する
マルチチップモジュール等の表面実装型配線基板も含ま
れる。また、上面に搭載する電子部品も前記ICチップ
の他、トランジスタ、ダイオードやEFT等の素子を搭
載することもできる。
The ceramic layer in the multilayer wiring board is not limited to the above-mentioned alumina, but may be aluminum nitride, glass ceramic, mullite, or the like. Furthermore,
The material of the wide area metallization layer and the wiring pattern is also W or Mo.
Not limited to, Cu and Co and alloys based on these,
Mo-Mn, Ag, Ag-Pd, Ag-Pt, or the like can also be applied. Further, the multilayer wiring board of the present invention includes a pin grid array type wiring board having pins implanted on the upper / lower surfaces thereof, and a surface mount type wiring board such as a multi-chip module having a plurality of electronic components and elements mounted on the upper surface. Is also included. Further, the electronic components mounted on the upper surface may be mounted with elements such as transistors, diodes, and EFTs in addition to the IC chip.

【0027】[0027]

【発明の効果】本発明のセラミック多層配線基板によれ
ば、内蔵されるビアが軸方向に沿って膨張又は収縮する
変形を生じても、そのビアが導通する広域メタライズ層
又は配線パターンにセラミック層を挟んで隣接する広域
メタライズ層の所定の位置に開口部を形成したので、こ
の広域メタライズ層同士、又は配線パターンと広域メタ
ライズ層とが互いに接触して短絡を生じることがない。
特に、薄肉のセラミック層を用いても上記短絡を防止で
きるので、厚さ方向に沿ってより多くの配線パターンを
有する高密度のセラミック多層配線基板とすることが容
易となる。また、上記ビアの変形が生じても、上記開口
部を形成することにより、配線基板の上面に凸部や凹み
が生じるのを抑制するので、係る上面にICチップなど
の電子部品を正確に搭載することも可能となる。
According to the ceramic multi-layer wiring board of the present invention, even if the built-in via is deformed to expand or contract in the axial direction, the ceramic layer is formed on the wide metallization layer or the wiring pattern through which the via is conducted. Since the openings are formed at predetermined positions of the wide metallization layers adjacent to each other, the wide metallization layers or the wiring pattern and the wide metallization layers do not contact each other to cause a short circuit.
In particular, since the short circuit can be prevented even when a thin ceramic layer is used, a high-density ceramic multilayer wiring board having more wiring patterns in the thickness direction can be easily obtained. Also, even if the via is deformed, the formation of the opening suppresses the occurrence of a protrusion or a dent on the upper surface of the wiring board, so that an electronic component such as an IC chip is accurately mounted on the upper surface. It is also possible to do.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(A)は本発明のセラミック多層配線基板の一形
態を示す部分垂直断面図、(B)は(A)中のB−B断面
図。
FIG. 1A is a partial vertical sectional view showing one embodiment of a ceramic multilayer wiring board of the present invention, and FIG. 1B is a sectional view taken along line BB in FIG.

【図2】(A)乃至(D)は共に異なる形態の開口部を示す
図1(B)と同様の断面図。
FIGS. 2A to 2D are cross-sectional views similar to FIG. 1B, each showing an opening in a different form.

【図3】(A)及び(B)は異なる形態のセラミック多層配
線基板を示す部分垂直断面図。
FIGS. 3A and 3B are partial vertical sectional views showing different forms of ceramic multilayer wiring boards.

【図4】更に異なる形態のセラミック多層配線基板を示
す部分垂直断面図。
FIG. 4 is a partial vertical sectional view showing a ceramic multilayer wiring board of still another form.

【図5】(A)は従来の積層体とこれを焼成したセラミッ
ク多層配線基板を示す部分垂直断面図、(B)及び(C)は
その変形状態を示す部分垂直断面図。
FIG. 5 (A) is a partial vertical sectional view showing a conventional multilayer body and a ceramic multilayer wiring board obtained by firing the same, and FIGS. 5 (B) and (C) are partial vertical sectional views showing their deformed states.

【符号の説明】[Explanation of symbols]

1,30,45,60…………………………………………
多層配線基板 2,4,6,8,31〜35,46〜49,61〜65………
セラミック層 10,12,36〜38,54,56,66,68……………
広域メタライズ層 11,20〜28,42,43,58,58′,67,69…
…開口部 14,39,50a〜50f,70,74……………………
配線パターン 18,41,52,72,76…………………………………
ビア
1,30,45,60 ………………………………………
Multilayer wiring board 2,4,6,8,31-35,46-49,61-65 ...
Ceramic layer 10,12,36-38,54,56,66,68 ……………
Wide area metallization layer 11,20-28,42,43,58,58 ', 67,69 ...
… Openings 14,39,50a to 50f, 70,74 …………………
Wiring pattern 18,41,52,72,76 ………………………………
Via

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】複数のセラミック層の間に広域メタライズ
層と配線パターンとが形成されるセラミック多層配線基
板であって、 上記広域メタライズ層同士、又は配線パターン同士、或
いは広域メタライズ層と配線パターンとの間を基板の厚
さ方向に導通するビアと、 上記ビアの少なくとも一端が導通する広域メタライズ層
又は配線パターンにセラミック層を介して隣接する広域
メタライズ層における上記ビアの軸方向と交差する位置
を含んで上記広域メタライズ層に設けた開口部と、 を有することを特徴とするセラミック多層配線基板。
1. A ceramic multilayer wiring board in which a wide metallization layer and a wiring pattern are formed between a plurality of ceramic layers, wherein the wide metallization layers, the wiring patterns, or the wide metallization layer and the wiring pattern are formed. A via that conducts in the thickness direction of the substrate between the via, and a position that intersects the axial direction of the via in a global metallization layer or a global metallization layer adjacent to the wiring pattern via a ceramic layer at least one end of the via passes through the ceramic layer. And an opening provided in the wide area metallization layer.
【請求項2】前記開口部の直径又は幅が、前記ビアの直
径の2倍以上である、ことを特徴とする請求項1に記載
のセラミック多層配線基板。
2. The ceramic multilayer wiring board according to claim 1, wherein the diameter or width of the opening is at least twice the diameter of the via.
【請求項3】前記ビアと導通する広域メタライズ層又は
配線パターンと、この広域メタライズ層又は配線パター
ンと隣接する広域メタライズ層との間に形成されたセラ
ミック層の厚さが60μm以下である、ことを特徴とす
る請求項1又は2に記載のセラミック多層配線基板。
3. A wide metallized layer or wiring pattern which is electrically connected to the via, and a ceramic layer formed between the wide metallized layer or the wide metallized layer adjacent to the wide metallized layer or wiring pattern has a thickness of 60 μm or less. The ceramic multilayer wiring board according to claim 1 or 2, wherein:
JP23873097A 1997-09-03 1997-09-03 Ceramic multilayer wiring board Expired - Fee Related JP3688444B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23873097A JP3688444B2 (en) 1997-09-03 1997-09-03 Ceramic multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23873097A JP3688444B2 (en) 1997-09-03 1997-09-03 Ceramic multilayer wiring board

Publications (2)

Publication Number Publication Date
JPH1187917A true JPH1187917A (en) 1999-03-30
JP3688444B2 JP3688444B2 (en) 2005-08-31

Family

ID=17034414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23873097A Expired - Fee Related JP3688444B2 (en) 1997-09-03 1997-09-03 Ceramic multilayer wiring board

Country Status (1)

Country Link
JP (1) JP3688444B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009231649A (en) * 2008-03-25 2009-10-08 Ngk Spark Plug Co Ltd Wiring substrate and production method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009231649A (en) * 2008-03-25 2009-10-08 Ngk Spark Plug Co Ltd Wiring substrate and production method

Also Published As

Publication number Publication date
JP3688444B2 (en) 2005-08-31

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