JPH1187407A - Integrated circuit - Google Patents
Integrated circuitInfo
- Publication number
- JPH1187407A JPH1187407A JP9242498A JP24249897A JPH1187407A JP H1187407 A JPH1187407 A JP H1187407A JP 9242498 A JP9242498 A JP 9242498A JP 24249897 A JP24249897 A JP 24249897A JP H1187407 A JPH1187407 A JP H1187407A
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- integrated circuit
- electrode
- substrate
- signal input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1903—Structure including wave guides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、基板上に集積回路
素子を搭載して成る集積回路に関するものである。[0001] 1. Field of the Invention [0002] The present invention relates to an integrated circuit having an integrated circuit element mounted on a substrate.
【０００２】[0002]
【従来の技術】従来、基板上に集積回路素子を搭載して
成る集積回路がある。この集積回路の概略的な構成の一
例の斜視図を図７に示し、図７に示す集積回路のＤ−
Ｄ’線における断面図を図８に示す。この集積回路の基
板１０１は、両端部が突起しており、その断面形状は凹
形となるものである。この基板１０１の中央の平面１０
２上に集積回路素子１０３が固定される。そして、金
（Ａｕ）等から成るボンディングワイヤ１０７ａ，１０
７ｂ，１０７ｃの一方の端部が、集積回路素子１０３上
に形成される複数の第１の電極１０５ａ，１０５ｂ，１
０５ｃにそれぞれ接着されるとともに、ボンディングワ
イヤ１０７ａ，１０７ｂ，１０７ｃの他方の端部が基板
１０１の一方の端部上の平面１０１ａ上に形成される複
数の第２の電極１０６ａ，１０６ｂ，１０６ｃにそれぞ
れ接着されて、複数の第１の電極１０５ａ，１０５ｂ，
１０５ｃと複数の第２の電極１０６ａ，１０６ｂ，１０
６ｃとがそれぞれ電気的に接続される。また、基板１０
１は、一般的には、内部に形成される配線の信号出力部
が端部に複数形成されており、これらの複数の信号出力
部と複数の第２の電極１０６ａ，１０６ｂ，１０６ｃと
がそれぞれ接続されて、集積回路素子１０３内の電気信
号が外部に出力される。2. Description of the Related Art Conventionally, there is an integrated circuit in which an integrated circuit element is mounted on a substrate. FIG. 7 is a perspective view showing an example of a schematic configuration of this integrated circuit.
FIG. 8 shows a cross-sectional view taken along line D ′. The substrate 101 of this integrated circuit has both ends protruding, and its cross-sectional shape is concave. Central plane 10 of this substrate 101
2, the integrated circuit element 103 is fixed. Then, bonding wires 107a, 10 made of gold (Au) or the like.
One end of each of the first electrodes 105a, 105b, 1c is formed on the integrated circuit element 103.
05c, and the other ends of the bonding wires 107a, 107b, 107c are respectively connected to a plurality of second electrodes 106a, 106b, 106c formed on a plane 101a on one end of the substrate 101. The plurality of first electrodes 105a, 105b,
105c and a plurality of second electrodes 106a, 106b, 10
6c are electrically connected to each other. The substrate 10
1, generally, a plurality of signal output portions of wiring formed inside are formed at an end portion, and the plurality of signal output portions and the plurality of second electrodes 106a, 106b, and 106c are respectively provided. As a result, the electric signal in the integrated circuit element 103 is output to the outside.
【０００３】[0003]
【発明が解決しようとする課題】ところで、現在、集積
回路は、広い周波数帯域で動作すること、特に高周波数
帯域で動作することが望まれている。At present, it is desired that integrated circuits operate in a wide frequency band, particularly in a high frequency band.
【０００４】一方、上述した従来の集積回路は、複数の
ボンディングワイヤ１０７ａ，１０７ｂ，１０７ｃを用
いて、集積回路素子１０３上の複数の第１の電極１０５
ａ，１０５ｂ，１０５ｃと、基板１０１上の複数の第２
の電極１０６ａ，１０６ｂ，１０６ｃとを接続している
ので、ボンディングワイヤ１０７ａ，１０７ｂ，１０７
ｃのインダクタンスによって、複数の第１の電極１０５
ａ，１０５ｂ，１０５ｃと複数の第２の電極１０６ａ，
１０６ｂ，１０６ｃとの間に流れる電気信号パルスの波
形が劣化する。この電気信号パルスの波形の劣化を低減
するためには、ボンディングワイヤ１０７ａ，１０７
ｂ，１０７ｃの長さを短くする必要がある。On the other hand, the conventional integrated circuit described above uses a plurality of bonding wires 107a, 107b, 107c to form a plurality of first electrodes 105 on an integrated circuit element 103.
a, 105b, 105c and a plurality of second
Of the bonding wires 107a, 107b, 107c.
c, the plurality of first electrodes 105
a, 105b, 105c and a plurality of second electrodes 106a,
The waveform of the electric signal pulse flowing between the electric signals 106b and 106c deteriorates. In order to reduce the deterioration of the waveform of the electric signal pulse, the bonding wires 107a, 107
It is necessary to shorten the lengths of b and 107c.
【０００５】しかし、例えば１０ＧＨｚ以上の高周波数
で変調された電気信号パルスの波形を劣化させないで出
力できるようなボンディングワイヤ１０７ａ，１０７
ｂ，１０７ｃを作製することは困難である。However, for example, the bonding wires 107a and 107 can be output without deteriorating the waveform of an electric signal pulse modulated at a high frequency of 10 GHz or more.
It is difficult to manufacture b and 107c.
【０００６】そこで、本発明は、高周波数の電気信号パ
ルスの波形を劣化させずに出力できる集積回路を提供す
ることを目的とする。Accordingly, an object of the present invention is to provide an integrated circuit that can output a high-frequency electric signal pulse without deteriorating its waveform.
【０００７】[0007]
【課題を解決するための手段】上記課題を解決するため
に、本発明の集積回路は、矩形状の基板と集積回路素子
とが電気的に接続される集積回路において、前記基板上
に前記集積回路素子が固定され、前記集積回路素子上に
形成される複数の第１の電極と、前記複数の第１の電極
上に配設され、前記複数の第１の電極のうちのいずれか
１つの電極と一方の端部とが接続される１つの信号入出
力用電極と、前記信号入出力用電極の２つの長辺とそれ
ぞれ対向し、前記複数の第１の電極のうちの他の２つの
電極と一方の端部とがそれぞれ接続される２つの接地用
電極とから成る、少なくとも１組の第２の電極と、を備
えることを特徴とする。In order to solve the above problems, an integrated circuit according to the present invention is an integrated circuit in which a rectangular substrate and an integrated circuit element are electrically connected to each other. A circuit element is fixed, a plurality of first electrodes formed on the integrated circuit element, and one of the plurality of first electrodes is disposed on the plurality of first electrodes. One signal input / output electrode to which the electrode and one end are connected, and two long sides of the signal input / output electrode, respectively, and the other two of the plurality of first electrodes At least one set of a second electrode including an electrode and two grounding electrodes to each of which one end is connected is provided.
【０００８】また、前記基板の端部は突起形状であり、
前記端部により前記複数の第２の電極を支持することを
特徴とする。The end of the substrate has a protruding shape,
The plurality of second electrodes are supported by the end portions.
【０００９】また、前記基板の端部近傍に、前記複数の
第２の電極を支持する突起形状の支持部が配設されるこ
とを特徴とする。[0009] A projection-shaped support portion for supporting the plurality of second electrodes is provided near an end of the substrate.
【００１０】さらに、前記複数の第２の電極上に、絶縁
性を有する薄膜が配設されることを特徴とする。Further, a thin film having an insulating property is provided on the plurality of second electrodes.
【００１１】[0011]
【発明の実施の形態】以下に、本発明の実施の形態を詳
細に説明する。Embodiments of the present invention will be described below in detail.
【００１２】図１は、本発明に係る集積回路の第１の実
施の形態の概略的な構成の斜視図を示し、図２は、図１
に示す集積回路のＡ−Ａ’線における断面図を示す。FIG. 1 is a perspective view of a schematic configuration of a first embodiment of an integrated circuit according to the present invention, and FIG.
1 is a cross-sectional view taken along line AA ′ of the integrated circuit shown in FIG.
【００１３】この第１の実施の形態の集積回路は、矩形
状の基板１上に集積回路素子３が固定され、前記集積回
路素子３上に形成される複数の第１の電極８ａ，８ｂ，
８ｃと、前記複数の第１の電極８ａ，８ｂ，８ｃ上に配
設され、前記複数の第１の電極８ａ，８ｂ，８ｃのうち
のいずれか１つの電極８ａと一方の端部とが接続される
１つの信号入出力用電極１０ａと、前記信号入出力用電
極１０ａの２つの長辺とそれぞれ対向し、前記複数の第
１の電極８ａ，８ｂ，８ｃのうちの他の２つの電極８
ｂ，８ｃと一方の端部とがそれぞれ接続される２つの接
地用電極１０ｂ，１０ｃとから成る、少なくとも１組の
第２の電極と、を備えるものである。In the integrated circuit according to the first embodiment, an integrated circuit element 3 is fixed on a rectangular substrate 1, and a plurality of first electrodes 8a, 8b,
8c, and one of the plurality of first electrodes 8a, 8b, 8c, which is disposed on the plurality of first electrodes 8a, 8b, 8c, is connected to one end. One of the plurality of first electrodes 8a, 8b, and 8c, which faces one of the signal input / output electrodes 10a and two long sides of the signal input / output electrode 10a.
b, 8c and at least one pair of second electrodes, each of which includes two grounding electrodes 10b, 10c to which one end is connected.
【００１４】また、前記基板１の端部１１，１２は突起
形状であり、前記端部１１，１２上の平面１１ａ，１２
ａにより前記複数の第２の電極である信号入出力用電極
１０ａ及び接地用電極１０ｂ，１０ｃを支持するもので
ある。なお、この第１の実施の形態では、端部１１，１
２の形状は、基板１の端辺に沿って連続した、いわゆる
突条形状として示している。また、基板１の２つの端部
１１，１２を突起形状として示しているが、支持する第
２の電極の位置や個数等に応じて、基板１の全ての端部
を突起形状としてもよい。The ends 11 and 12 of the substrate 1 have a projection shape, and the flat surfaces 11 a and 12 on the ends 11 and 12 are formed.
a supports the plurality of second electrodes, ie, the signal input / output electrode 10a and the grounding electrodes 10b and 10c. In the first embodiment, the ends 11, 1
The shape 2 is shown as a so-called ridge shape that is continuous along the edge of the substrate 1. Further, although the two ends 11 and 12 of the substrate 1 are shown as projections, all the ends of the substrate 1 may be projections according to the position and the number of the second electrodes to be supported.
【００１５】次に、この集積回路の作製方法について説
明する。基板１は矩形状であり、突起形状の端部１１，
１２は、基板１と同じ材料を使用して、基板１と一体化
されて形成される。Next, a method of manufacturing the integrated circuit will be described. The substrate 1 has a rectangular shape, and has a protruding end 11,
12 is formed integrally with the substrate 1 using the same material as the substrate 1.
【００１６】一方、集積回路素子３には、金等を使用し
て、蒸着法、メッキ法又はスパッタリング法等の手法に
より複数の第１の電極８ａ，８ｂ，８ｃを予め形成す
る。さらに、金等により作製された信号入出力用電極１
０ａの一方の端部を第１の電極８ａに接続し、また、接
地用電極１０ｂ，１０ｃの一方の端部を第１の電極１０
ｂ，１０ｃにそれぞれ接続して、半田等によりそれぞれ
固定する。これらの第２の電極は、いわゆるリード線で
あり、伝送線路としてはコプレーナ線路を構成する。On the other hand, a plurality of first electrodes 8a, 8b, 8c are formed in advance on the integrated circuit element 3 by using a method such as a vapor deposition method, a plating method, or a sputtering method using gold or the like. Further, a signal input / output electrode 1 made of gold or the like.
0a is connected to the first electrode 8a, and one end of the ground electrodes 10b and 10c is connected to the first electrode 10a.
b and 10c, respectively, and fixed with solder or the like. These second electrodes are so-called lead wires, and constitute a coplanar line as a transmission line.
【００１７】そして、半田又は導電性接着剤等を用いた
ダイボンディング等の手法により、集積回路素子３の複
数の第１の電極８ａ，８ｂ，８ｃが形成されていない面
を基板１上の平面２に固定するとともに、信号入出力用
電極１０ａ及び接地用電極１０ｂ，１０ｃを端部１１上
の平面１１ａに接着、固定して支持する。Then, the surface of the integrated circuit element 3 on which the plurality of first electrodes 8a, 8b, 8c are not formed is flattened on the substrate 1 by a technique such as die bonding using solder or a conductive adhesive. 2, and the signal input / output electrode 10a and the grounding electrodes 10b and 10c are adhered and fixed to the flat surface 11a on the end portion 11 to be supported.
【００１８】ここで、信号入出力用電極１０ａの幅をＷ
1 とし、信号入出力用電極１０ａと接地用電極１０ｂと
の空隙幅及び信号入出力用電極１０ａと接地用電極１０
ｃとの空隙幅をそれぞれＷ2 とするときに、例えば、 Ｗ2 ／Ｗ1 ＝０．１７ の値を保持するように、複数の第２の電極を配設するこ
とにより、特性インピーダンスが５０オームのコプレー
ナ線路を形成できる。なお、信号入出力用電極１０ａ及
び接地用電極１０ｂ，１０ｃの形状を平板状として示し
ているが、信号入出力用電極１０ａ及び接地用電極１０
ｂ，１０ｃの形状は平板状に限定されることはなく、上
述の特性インピーダンスの値を維持できるならば、例え
ば円筒状等の種々の形状とすることが可能である。Here, the width of the signal input / output electrode 10a is W
1 , the gap width between the signal input / output electrode 10a and the ground electrode 10b, and the signal input / output electrode 10a and the ground electrode 10b.
When the gap width with respect to c is W 2 , for example, by arranging a plurality of second electrodes so as to maintain a value of W 2 / W 1 = 0.17, the characteristic impedance becomes 50%. An ohmic coplanar line can be formed. Although the shape of the signal input / output electrode 10a and the ground electrodes 10b and 10c is shown as a flat plate, the signal input / output electrode 10a and the ground electrode
The shapes of b and 10c are not limited to the flat plate shape, but may be various shapes such as a cylindrical shape as long as the above-described characteristic impedance value can be maintained.
【００１９】上述した集積回路の第１の実施の形態の構
成では、集積回路素子３上の第１の電極８ａ，８ｂ，８
ｃと、第２の電極を構成する信号入出力用電極１０ａ及
び接地用電極１０ｂ，１０ｃとがそれぞれ直接に接続さ
れて固定されるので、第１の電極８ａと信号入出力用電
極１０ａとの間を流れる高周波数の電気信号パルスは、
従来の集積回路のように寄生インダクタンスの影響を受
けることがない。これにより、電気信号パルスの波形を
劣化させないで出力できる。In the configuration of the first embodiment of the integrated circuit described above, the first electrodes 8a, 8b, 8
c and the signal input / output electrode 10a and the grounding electrodes 10b and 10c constituting the second electrode are directly connected and fixed, respectively, so that the first electrode 8a and the signal input / output electrode 10a are connected to each other. High frequency electrical signal pulses flowing between
It is not affected by the parasitic inductance unlike the conventional integrated circuit. Thus, it is possible to output the electric signal pulse without deteriorating the waveform.
【００２０】また、信号入出力用電極１０ａ及び接地用
電極１０ｂ，１０ｃの支持部として、予め形成された基
板１の突起形状の端部１１上の平面１１ａ又は端部１２
上の平面１２ａを利用するので、信号入出力用電極１０
ａ及び接地用電極１０ｂ，１０ｃを容易に支持できる。As a support for the signal input / output electrode 10a and the ground electrodes 10b and 10c, a flat surface 11a or an end 12
Since the upper plane 12a is used, the signal input / output electrode 10
a and the grounding electrodes 10b and 10c can be easily supported.
【００２１】次に、本発明に係る集積回路の第２の実施
の形態について説明する。図３は、本発明に係る集積回
路の第２の実施の形態の概略的な構成の斜視図を示し、
図４は、図３に示す集積回路のＢ−Ｂ’線における断面
図を示す。なお、図３及び図４において、図１及び図２
で示す符号と同じ符号で示す各部は、図１及び図２を用
いて説明した構成と同じ構成であるので、詳細な説明は
省略する。Next, a description will be given of a second embodiment of the integrated circuit according to the present invention. FIG. 3 is a perspective view of a schematic configuration of a second embodiment of the integrated circuit according to the present invention,
FIG. 4 is a cross-sectional view taken along line BB ′ of the integrated circuit shown in FIG. In FIGS. 3 and 4, FIGS.
The components indicated by the same reference numerals as those indicated by the symbols have the same configurations as those described with reference to FIGS. 1 and 2, and a detailed description thereof will be omitted.
【００２２】この第２の実施の形態の構成は、基板１の
端部近傍に、１組の第２の電極である信号入出力用電極
１０ａ及び接地用電極１０ｂ，１０ｃを支持する突起形
状の支持部１３が配設されるものである。この支持部１
３上の平面１３ａに信号入出力用電極１０ａ及び接地用
電極１０ｂ，１０ｃを接着して固定する。The configuration of the second embodiment is such that a projection-like shape supporting a pair of second electrodes, ie, a signal input / output electrode 10a and grounding electrodes 10b, 10c, is provided near an end of the substrate 1. The support part 13 is provided. This support 1
The signal input / output electrode 10a and the grounding electrodes 10b and 10c are adhered and fixed to the flat surface 13a on the upper surface 3.
【００２３】この集積回路を作製するときには、まず、
基板１上の端部に支持部１３を形成する。支持部１３
は、ガラスや誘電体等を使用し、印刷等の手法により形
成する。また、予め形成された支持部１３を取り付ける
ようにしてもよい。次に、複数の第１の電極８ａ，８
ｂ，８ｃが形成された集積回路素子３を基板１上に固定
する。そして、第２の電極である信号入出力用電極１０
ａ及び接地用電極１０ｂ，１０ｃの一方の端部を第１の
電極８ａ，８ｂ，８ｃにそれぞれ接続して固定するとと
もに、支持部１３上の平面１３ａに接着、固定して支持
する。このように、集積回路素子３の固定処理の後で、
第２の電極を第１の電極に接続させ、固定するので、第
１の実施の形態で示す集積回路よりも第２の電極の第１
の電極への接続処理を容易に行うことができる。When manufacturing this integrated circuit, first,
A support 13 is formed at an end on the substrate 1. Support part 13
Is formed by a method such as printing using glass or a dielectric. Further, a support 13 formed in advance may be attached. Next, the plurality of first electrodes 8a, 8
The integrated circuit element 3 on which b and 8c are formed is fixed on the substrate 1. Then, the signal input / output electrode 10 which is the second electrode
a and one ends of the grounding electrodes 10b and 10c are connected to and fixed to the first electrodes 8a, 8b and 8c, respectively, and are also adhered, fixed and supported on the flat surface 13a on the support portion 13. Thus, after the fixing process of the integrated circuit element 3,
Since the second electrode is connected to and fixed to the first electrode, the first electrode of the second electrode is larger than the integrated circuit shown in the first embodiment.
Can easily be connected to the electrodes.
【００２４】次に、本発明に係る集積回路の第３の実施
の形態について説明する。図５は、本発明に係る集積回
路の第３の実施の形態の概略的な構成の斜視図を示し、
図６は、図５に示す集積回路のＣ−Ｃ’線における断面
図を示す。なお、図５及び図６において、図１及び図２
で示す符号と同じ符号で示す各部は、図１及び図２を用
いて説明した構成と同じ構成であるので、詳細な説明は
省略する。Next, a third embodiment of the integrated circuit according to the present invention will be described. FIG. 5 is a perspective view of a schematic configuration of a third embodiment of the integrated circuit according to the present invention,
FIG. 6 is a sectional view taken along line CC ′ of the integrated circuit shown in FIG. 5 and FIG. 6, FIG. 1 and FIG.
The components indicated by the same reference numerals as those indicated by the symbols have the same configurations as those described with reference to FIGS. 1 and 2, and a detailed description thereof will be omitted.
【００２５】この第３の実施の形態で示す構成は、第１
の実施の形態の構成において、１組の第２の電極である
信号入出力用電極１０ａ及び接地用電極１０ｂ，１０ｃ
上に、絶縁性を有する薄膜１４が配設されるものであ
る。この薄膜１４は、例えばポリイミド等の誘電体等を
使用して形成される。なお、この第３の実施の形態は、
第２の実施の形態で示した構成においても適用可能であ
る。The configuration shown in the third embodiment is similar to the first embodiment.
In the configuration of the embodiment, the signal input / output electrode 10a and the grounding electrodes 10b and 10c, which are a pair of second electrodes, are provided.
An insulating thin film 14 is provided thereon. The thin film 14 is formed using a dielectric such as polyimide, for example. Note that this third embodiment is
The present invention is also applicable to the configuration shown in the second embodiment.
【００２６】この集積回路を作製するときには、予め、
薄膜１４上に第２の電極である信号入出力用電極１０ａ
及び接地用電極１０ｂ，１０ｃを形成する。そして、信
号入出力用電極１０ａ及び接地用電極１０ｂ，１０ｃの
一方の端部を第１の電極８ａ，８ｂ，８ｃにそれぞれ接
続して固定するとともに、端部１１上の平面１１ａに接
着、固定して支持する。このように、複数の第２の電極
を薄膜１４に形成して用いることにより、第１の実施の
形態で示す集積回路よりも第２の電極の搭載及び接続処
理を容易に行うことができる。When manufacturing this integrated circuit,
A signal input / output electrode 10a serving as a second electrode on the thin film 14.
And the grounding electrodes 10b and 10c are formed. One end of the signal input / output electrode 10a and one end of the grounding electrodes 10b, 10c are connected to and fixed to the first electrodes 8a, 8b, 8c, respectively, and are adhered and fixed to the flat surface 11a on the end 11. And support. In this manner, by using the plurality of second electrodes formed on the thin film 14, the mounting and connection processing of the second electrodes can be performed more easily than the integrated circuit described in the first embodiment.
【００２７】なお、上述した集積回路の第１、第２及び
第３の実施の形態では、説明を簡略化するために、第２
の電極を１組のみ示しているが、通常は複数組形成され
る。このとき、第１の電極も第２の電極の個数に対応す
る個数分形成されるものである。In the first, second, and third embodiments of the integrated circuit described above, the second circuit is used to simplify the description.
Although only one set of electrodes is shown, a plurality of sets are usually formed. At this time, the first electrodes are also formed by the number corresponding to the number of the second electrodes.
【００２８】また、高周波数で動作可能な集積回路を形
成するために、第２の電極が構成する伝送線路をコプレ
ーナ線路として説明しているが、伝送線路はコプレーナ
線路に限定されることはなく、例えば、第２の電極を多
層にして形成するときにはマイクロストリップ線路を構
成することが好ましい。また、第２の電極を外部に取り
出す途中で交差させた構成とすることも可能である。Although the transmission line formed by the second electrode is described as a coplanar line in order to form an integrated circuit operable at a high frequency, the transmission line is not limited to the coplanar line. For example, when the second electrode is formed as a multilayer, it is preferable to form a microstrip line. It is also possible to adopt a configuration in which the second electrodes intersect while being taken out to the outside.
【００２９】[0029]
【発明の効果】以上説明したように、本発明の集積回路
は、基板上に固定された集積回路素子上に形成される複
数の第１の電極のうちのいずれか１つの電極と一方の端
部とが接続される１つの信号入出力用電極と、前記信号
入出力用電極の２つの長辺とそれぞれ対向し、前記複数
の第１の電極のうちの他の２つの電極と一方の端部とが
それぞれ接続される２つの接地用電極とから成る、少な
くとも１組の第２の電極を備えることにより、集積回路
素子上の複数の第１の電極と、第２の電極を構成する１
つの信号入出力用電極及び２つの接地用電極とがそれぞ
れ直接に接続して固定されるので、第１の電極と信号入
出力用電極との間を流れる高周波数の電気信号パルス
は、従来の集積回路のように寄生インダクタンスの影響
を受けることがない。これにより、電気信号パルスの波
形を劣化させないで出力できる。As described above, the integrated circuit according to the present invention has one of a plurality of first electrodes formed on an integrated circuit element fixed on a substrate and one end thereof. A signal input / output electrode connected to a portion, two opposing long sides of the signal input / output electrode, and one end of the other of the plurality of first electrodes A plurality of first electrodes on the integrated circuit element and a plurality of first electrodes on the integrated circuit element by providing at least one pair of second electrodes each including two grounding electrodes connected to the respective parts.
Since the two signal input / output electrodes and the two grounding electrodes are directly connected and fixed, respectively, a high-frequency electric signal pulse flowing between the first electrode and the signal input / output electrode is of a conventional type. It is not affected by parasitic inductance unlike an integrated circuit. Thus, it is possible to output the electric signal pulse without deteriorating the waveform.
【００３０】また、矩形状の基板の端部は突起形状であ
り、前記端部により前記複数の第２の電極を支持するこ
とにより、第２の電極を容易に支持できる。Further, the end of the rectangular substrate has a protruding shape, and the second electrode can be easily supported by supporting the plurality of second electrodes by the end.
【００３１】また、前記基板の端部近傍に、前記複数の
第２の電極を支持する突起形状の支持部が配設されるこ
とにより、支持部の厚さを調整して第２の電極を支持し
固定することが可能となり、第２の電極の接続処理を容
易に行うことができる。Further, a projection-shaped support portion for supporting the plurality of second electrodes is provided near an end of the substrate, so that the thickness of the support portion is adjusted to allow the second electrode to be formed. The second electrode can be supported and fixed, and the connection processing of the second electrode can be easily performed.
【００３２】また、前記複数の第２の電極上に、絶縁性
を有する薄膜が配設されることにより、薄膜に予め形成
された複数の第２の電極を複数の第１の電極にそれぞれ
接続して固定すればよいので、第２の電極の搭載及び接
続処理を容易に行うことができる。Further, by disposing an insulating thin film on the plurality of second electrodes, the plurality of second electrodes formed in advance on the thin film are respectively connected to the plurality of first electrodes. Then, the mounting and connection processing of the second electrode can be easily performed.
【図１】本発明に係る集積回路の第１の実施の形態の概
略的な構成の斜視図である。FIG. 1 is a perspective view of a schematic configuration of a first embodiment of an integrated circuit according to the present invention.
【図２】図１に示す集積回路のＡ−Ａ’線における断面
図である。FIG. 2 is a cross-sectional view taken along line AA ′ of the integrated circuit shown in FIG.
【図３】本発明に係る集積回路の第２の実施の形態の概
略的な構成の斜視図である。FIG. 3 is a perspective view of a schematic configuration of a second embodiment of the integrated circuit according to the present invention.
【図４】図３に示す集積回路のＢ−Ｂ’線における断面
図である。FIG. 4 is a cross-sectional view taken along line BB ′ of the integrated circuit shown in FIG. 3;
【図５】本発明に係る集積回路の第３の実施の形態の概
略的な構成の斜視図である。FIG. 5 is a perspective view of a schematic configuration of a third embodiment of the integrated circuit according to the present invention.
【図６】図５に示す集積回路のＣ−Ｃ’線における断面
図である。6 is a cross-sectional view of the integrated circuit shown in FIG. 5, taken along line CC ′.
【図７】従来の集積回路の概略的な構成の斜視図であ
る。FIG. 7 is a perspective view of a schematic configuration of a conventional integrated circuit.
【図８】図７に示す集積回路のＤ−Ｄ’線における断面
図である。8 is a cross-sectional view of the integrated circuit shown in FIG. 7, taken along line DD '.
１・・・基板 ３・・・集積回路素子 ８ａ，８ｂ，８ｃ・・・第１の電極 １０ａ・・・信号入出力用電極 １０ｂ，１０ｃ・・・接地用電極 １１，１２・・・端部 １３・・・支持部 １４・・・薄膜 DESCRIPTION OF SYMBOLS 1 ... Substrate 3 ... Integrated circuit element 8a, 8b, 8c ... 1st electrode 10a ... Signal input / output electrode 10b, 10c ... Grounding electrode 11, 12 ... End part 13 ... support part 14 ... thin film
Claims (4)
に接続される集積回路において、 前記基板上に前記集積回路素子が固定され、 前記集積回路素子上に形成される複数の第１の電極と、 前記複数の第１の電極上に配設され、前記複数の第１の
電極のうちのいずれか１つの電極と一方の端部とが接続
される１つの信号入出力用電極と、前記信号入出力用電
極の２つの長辺とそれぞれ対向し、前記複数の第１の電
極のうちの他の２つの電極と一方の端部とがそれぞれ接
続される２つの接地用電極とから成る、少なくとも１組
の第２の電極と、 を備えることを特徴とする集積回路。1. An integrated circuit in which a rectangular substrate and an integrated circuit element are electrically connected, wherein the integrated circuit element is fixed on the substrate, and a plurality of first circuits formed on the integrated circuit element. And one signal input / output electrode provided on the plurality of first electrodes and connected to one of the plurality of first electrodes and one end thereof. , Two opposite sides of the signal input / output electrode, and two ground electrodes to which the other two electrodes of the plurality of first electrodes and one end are respectively connected. An integrated circuit comprising: at least one set of second electrodes.
端部により前記複数の第２の電極を支持することを特徴
とする請求項１記載の集積回路。2. The integrated circuit according to claim 1, wherein an end of the substrate has a projection shape, and the end supports the plurality of second electrodes.
の電極を支持する突起形状の支持部が配設されることを
特徴とする請求項１記載の集積回路。3. A method according to claim 1, wherein the plurality of second substrates are provided near an end of the substrate.
2. The integrated circuit according to claim 1, further comprising a projection-shaped support portion for supporting said electrode.
する薄膜が配設されることを特徴とする請求項１〜請求
項３のうちのいずれかに記載の集積回路。4. The integrated circuit according to claim 1, wherein an insulating thin film is provided on the plurality of second electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9242498A JPH1187407A (en) | 1997-09-08 | 1997-09-08 | Integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9242498A JPH1187407A (en) | 1997-09-08 | 1997-09-08 | Integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1187407A true JPH1187407A (en) | 1999-03-30 |
Family
ID=17089993
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9242498A Pending JPH1187407A (en) | 1997-09-08 | 1997-09-08 | Integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1187407A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013102005A (en) * | 2011-11-07 | 2013-05-23 | Shindengen Electric Mfg Co Ltd | Method of manufacturing semiconductor device, semiconductor device, and manufacturing jig for semiconductor device |
-
1997
- 1997-09-08 JP JP9242498A patent/JPH1187407A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013102005A (en) * | 2011-11-07 | 2013-05-23 | Shindengen Electric Mfg Co Ltd | Method of manufacturing semiconductor device, semiconductor device, and manufacturing jig for semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0993005A (en) | Electrode for high frequency circuit, transmission line and resonator using the same | |
| JP2944403B2 (en) | Semiconductor device | |
| JPH0818187A (en) | Electronic device and manufacture thereof | |
| US4694347A (en) | Television receiver having a liquid crystal display device | |
| JPH113967A (en) | High-frequency module | |
| JPH1187407A (en) | Integrated circuit | |
| JP2000091801A (en) | Connection line substrate | |
| US6529105B1 (en) | Process and device for bonding two millimeter elements | |
| JPH1075024A (en) | Shielded delay line and its manufacture | |
| JPH0773282A (en) | High frequency circuit device | |
| JP2636550B2 (en) | Signal circuit | |
| JPS6271301A (en) | Microwave integrated circuit device | |
| JPS6359101A (en) | Microwave circuit connector | |
| JP2802375B2 (en) | Frequency characteristic expansion method for mixed circuit of electric and optical elements | |
| JPH06177500A (en) | Flexible wiring board | |
| JP2590686B2 (en) | Hybrid integrated circuit | |
| JP2001345606A (en) | Mmic amplifier | |
| JP2529778Y2 (en) | Microwave integrated circuit | |
| JPH11205012A (en) | High frequency circuit | |
| JPS61113301A (en) | Microstrip line terminator | |
| JPH01141402A (en) | Microwave integrated circuit device | |
| JP2557081Y2 (en) | Micro stripline filter | |
| JPH0758243A (en) | Semiconductor package | |
| JPH07263923A (en) | 90× distributor | |
| JP2533277Y2 (en) | Chip capacitor grounding structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090511 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090511 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 9 Free format text: PAYMENT UNTIL: 20100511 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 9 Free format text: PAYMENT UNTIL: 20100511 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 9 Free format text: PAYMENT UNTIL: 20100511 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 10 Free format text: PAYMENT UNTIL: 20110511 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120511 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 11 Free format text: PAYMENT UNTIL: 20120511 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130511 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140511 Year of fee payment: 13 |