JPH118318A - Formation of semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CMOS semiconductor element structure in which element formation areas for both PMOS and NMOS are identical in size, and the CMOS circuit characteristics are not sacrificed. SOLUTION: As a specific method for correcting the unbalance in ability of an element, a gate oxide film thickness of each of PMOS and NMOS is changed. When the thickness of the gate oxide film of a PMOS formation area is Tox(P) and that of the gate oxide film of an NMOS formation area is Tox(N), a relation that Tox(P)≈1/2.5-1/3Tox(N) is generally maintained. In this way, a difference in mobilities is completely absorbed by adjusting the thickness of the gate oxide film which decides the current ability of the element. As a result, noise margin that can be considered as a characteristic of a CMOS circuit can be significantly improved. Further, a PMOS element formation area size can be reduced to the same size as that of the NMOS, realizing reduction in the occupied area of a basic cell and reduction in an occupied area of an element of an I/O pad part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for forming a complementary element on a wafer in the manufacture of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Conventionally, there has been a CMOS manufacturing technique as one method of manufacturing a silicon integrated circuit.

In recent years, attention has been paid to CMOS technology for low power consumption as a technical trend in recent years.
U and the like have become more and more CMOS-friendly, and gate arrays and the like for the production of chips with a short delivery date are rapidly spreading.

However, in response to these technical trends, CMO
When the element structure of S is reviewed, the reality is that the advantages of the CMOS integrated circuit are not always fully utilized.

[0005] 1. For example, a channelless structure (generally SOG: Sea Of) which is mainly used in gate arrays
Gate structure), the element array structure formed in the element formation area is a PMO
It is desired to secure the same size in the S formation area and the NMOS formation area. This is because by maintaining the element area balance, it is possible to take advantage of the advantage that the wiring areas can be uniformly allocated.

FIG. 5 shows an example of a conventional CMOS device structure. In the drawing, Tox (N) indicates the gate oxide film thickness of the NMOS transistor, and Tox (P) indicates the gate oxide film thickness of the PMOS transistor. A'-B 'is a line indicating a cut edge of the wafer sectional structure.

In a conventional CMOS manufacturing process, after forming a WELL (a reverse conductivity type region formed by diffusion of different impurities) for separating a PMOS region and an NMOS region,
A thin high-quality oxide film is formed on the entire surface of the wafer (gate oxidation step). Therefore, Tox (N) = Tox (P)
Please note that it is a structure.

[0008] 2. However, PMO mainly with P-type conduction
The S element channel portion has a mobility (mobility: carrier) that controls channel conduction (charged particles contributing to conduction).
(The mobility of the charged particles due to the electric field) is about 1 / 2.5 to 1/3 of that of the N-type conductive carrier. As a result, in the conventional structure shown in FIG.
The element current coefficient of OS is approximately 1 compared to that of NMOS.
／.

Such a large difference in carrier mobility in a solid means that positive (+) charged particles (actually holes without electrons) are effective in a periodic potential space created by a silicon crystal lattice. This is due to the fact that the mass becomes larger than the effective mass of negatively charged particles (actually, the electron itself), and is concluded by a mathematical model in solid state physics.

[0010] 3. The imbalance in the electrical characteristics of the device current capability causes the following disadvantages of the characteristics after the CMOS circuit is formed.

For the sake of simplicity, the following description is based on a "full CMOS structure" and an "inverter (logic inversion cell) of a logic circuit basic cell".

The inverter is formed by connecting each of PMOS and NMOS one by one.

The most excellent point of the CMOS device is that a logic threshold value (a boundary voltage regarded as 0 or 1) can be set just at the center (Vdd / 2) of the power supply voltage. The fact that the threshold value can be located at the center of the operating power supply voltage means, in other words, that the circuit is resistant to external noise, that is, resistant to malfunction of a circuit caused by noise superimposed on a signal line. (For example, assuming a power supply of + 5V, + 5V
It is clear from either the spiking noise from the side or the spiking noise from the 0 V side that the central value of the power supply voltage has the maximum margin. When the threshold value is, for example, about 2 V, the allowable noise peak from the 0 V side is within 2 V, and conversely, the noise from the +5 V side is within 3 V. When discussing the noise resistance of the circuit, Will be discussed on behalf of the weaker side. The optimum conditions for arranging this logical threshold value at the center of the power supply voltage are PMOS and NMOS forming an inverter.
It is important that the current capability coefficient (β) of the device be completely equal. For the detailed relationship between the logical threshold value and the current capability coefficient, refer to the following equation (1).

VLL = (Vdd−Vtp) / ((βn / βp) ^1/2 + 1) + Vtn / ((βp / βn) ^1/2 + 1) (1) VLL: logic threshold, βp: PMOS Current coefficient, βn: N
MOS current coefficient Vtp: PMOS gate threshold voltage, Vtn: NMO
S gate threshold voltage Vdd: power supply voltage.

4. As is apparent from the above description, when the element area is formed with the same element size by giving priority to the conditions from the element layout surface, the PMOS, N
The electric current capability between the MOSs deteriorates, and the noise margin characteristic of the CMOS circuit is sacrificed.

In the above equation (1), βp = 1 / 3βn,
When adopting the values of Vdd = 5.0V and Vtn = Vtp = 0.75V, VLL becomes around 1.63V, and 1 /
It can be understood that the threshold value shifts to the ground side with respect to 2Vdd = 2.5V. Completely 1 in CMOS
Although Vtp = Vtn is one condition for setting the threshold value at the / 2Vdd point, the contribution of the current coefficient ratio is high as is clear from the equation.

5. In a deeper submicron process, such as in recent years, this characteristic degradation leads to a rather serious situation if it is mentioned a little more from the viewpoint of noise margin. With the miniaturization of the entire device, the capability of the internal device is increased, and the delay of the internal connection wiring is no longer dominant than the gate delay, while considerations for internal noise are increasing.
For example, even when the coupling from the adjacent wiring is assumed as the noise wraparound path, the coupling capacitance tends to increase due to the narrowing between the adjacent wirings. In addition, the increase in the current capability of the individual elements increases the through current (PMO) peculiar to the CMOS logic circuit.
In the course of the transition of the ON / OFF operation from S to NMOS or vice versa, a simultaneous PMOS and NMOS ON state occurs. The current flowing between the power supplies at this timing)
The peak value of cannot be ignored. If the resistance value of the power supply metal layer is high, the internal voltage is easily fluctuated by this through current. In that sense, it can be said that it is increasingly necessary to secure a noise margin inside the chip.

If the P and N element capacity imbalance is designed as it is, the logic threshold value is drawn to the ground side, so that it is a familiar case that a malfunction easily occurs with respect to the ground bounce inside the integrated circuit. I can say.

6. From a different viewpoint, let's think from the standpoint of affirming the design under the current manufacturing conditions. In the cell design giving priority to the balance in terms of element performance, the difference in occupied area between the PMOS and the NMOS becomes large, and the design of a compact cell becomes a bottleneck. Not only that, this imbalance in the size of the MOS element means that when designing to output internal signals to the outside of the chip at high speed, it is necessary to optimize the driving capability of the details while balancing the performance of the entire signal line. become.

By the way, although there are no cases where prior applications have been filed, it is clear that the aims are different.

For example, Japanese Patent Application Laid-Open No. Sho 59-182555 describes that the oxide film thickness on the NMOS side is simply increased. A specific configuration example is PMO
The description is based on the value of NMOS 1500 Å with respect to S 750 Å. Although the contents of this prior application are evident for the reasons described above, it is not an invention which leads to a device for maximizing the device performance as a CMOS.

Japanese Patent Application Laid-Open No. 62-037959 is a similar prior art. However, this prior application is intended to enhance the convenience in manufacturing as described below.

That is, it is an object of the present invention to provide a method of manufacturing a CMOS having a single well structure, which does not hinder the change of the P type and the N type of the silicon substrate.

Another similar example is disclosed in Japanese Patent Application Laid-Open No. 01-061.
No. 048 is listed, but the optimum conditions of the gate film structure of each of the PMOS and NMOS are not specified, and it cannot be said that the characteristics are sufficiently improved. In particular, the specific numerical basis was poor, and conditions for causing a specific effect such as an improvement in the balance between mutual conductance and on-resistance were not clear.

Further, the prior application of Japanese Patent Application Laid-Open No. 06-334132 aims at a structural change as a measure for preventing deterioration of device characteristics due to hot electrons which tend to occur in NMOS devices. Hot electrons are generated in NMOS devices because electrons are the main conduction carriers. (Hot electrons are electrons that pass through a channel and are accelerated by this electric field to obtain energy above a certain level due to an electric field generated when a voltage is applied between the source and the drain.
Since the energy exceeding the potential wall at the gate oxide film-silicon semiconductor interface is injected into the gate electrode regardless of the presence of the gate oxide film, the basic characteristics of the MOS device are greatly shaken. Specific problems include:
Since the element characteristics change with time, the long-term reliability of the circuit operation is significantly deteriorated. )

[0026]

As is apparent from the above description, the problem to be solved by the present invention is exactly this CM.
It is to obtain complete uniformity of OS element characteristics. That is, the first point of the present invention to solve the problem is such a CM that “the element formation area can be set to the same size for both the PMOS and the NMOS and the CMOS circuit characteristics are not sacrificed”.
An OS semiconductor device structure is provided.

[0027]

As a concrete solution of the present invention, a CMO integrated on a silicon substrate is used.
In an S (complementary MOS) semiconductor device, CMOS basic element, that is, P-channel MOSFE
1. The element formation area sizes of the T and N channel MOSFETs substantially match; In addition, the gate oxide film thickness of the PMOSFET is
An element structure which is formed to be thin in a range of 1/2 to 1/3 of an oxide film thickness of a FET.

A specific semiconductor element forming step is Well
Drive-in, LOCOS oxidation process (field formation)
In the later gate oxidation step, first, the PMOS, NMOS
After the simultaneous formation of the gate oxide film, a. Providing a gate oxide film etching step in the PMOS element formation area to expose the PMOS side silicon surface; In the second gate oxide film forming step, PM
OS formation area (bare silicon), NMOS formation area (oxide film already formed by first gate oxidation step)
Forming a gate oxide film for PMOS and NMOS for different thicknesses by performing simultaneous oxidation.

Alternatively, a specific process of forming a semiconductor device is a PMO process first in a gate oxidation process after a well drive-in and LOCOS oxidation process (field formation).
After the simultaneous formation of the S and NMOS gate oxide films, c. B. A step of forming a mask layer for suppressing diffusion of oxygen atoms, such as a Si3N4 film, is provided again in the PMOS element formation area. Thereafter, the gate oxide film forming process is restarted to form a gate oxide film for PMOS and NMOS to a different thickness.

The above is realized.

[0031]

According to the first aspect of the present invention, it is possible to correct the non-uniformity of the device current capability caused by the physical constraint of the CMOS basic device in the most effective portion in the MOS manufacturing process. Characteristics can be guaranteed.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described.

FIG. 1 shows an example of an element layout to which the present invention is applied. The broken line AB drawn in the drawing indicates the cross-sectional position in FIG.

FIG. 2 is a cross-sectional structural view of the device of the present invention.
The symbol Tox (P) in the figure indicates the gate oxide film thickness on the PMOS formation area side, and Tox (N) indicates the NMOS.
It shows the thickness of the gate oxide film in the formation area.

The specific relation of the gate oxide film thickness in the present invention is approximately Tox (P) ≒ 1 / 2.5 in FIG.
The relationship of １ ／ Tox (N) is maintained.

The current capacity can be adjusted by this setting because M
The equation for determining the OS current capability is: β = μ · Cox · (W / L) = μ × ε × (W / L) / T
ox Here, μ: mobility, ε: dielectric constant, Tox: gate oxide film W: MOS channel formation width, L: MOS channel formation length.

That is, the difference in mobility can be completely absorbed by adjusting the thickness of the gate oxide film that determines the current capability of the device.

FIG. 3 shows an embodiment of a first manufacturing process for realizing the present invention. 3 (a) to 3 (e) show cross sections of the silicon substrate in each of the manufacturing steps, and the emphasis will be given to specific manufacturing steps of the present invention.

FIG. 3A is a view of a silicon substrate on which a necessary well has already been formed. Where well is PM
It may be a twin-well structure for OS and NMOS, or it may be understood that P-well (Nwell) has just been formed in the case of a single well process of N-type silicon (P-type). In the figure, reference numeral 1 denotes a cross section of a silicon substrate.

FIG. 3B shows a gate oxide film process which is performed for the first time, and shows a situation in which a gate oxide film is simultaneously formed on the PMOS and NMOS element formation areas. In the figure, reference numeral 2 denotes a gate oxide film formed at this stage.

FIG. 3C shows that the PMOS element forming area where the element performance is deteriorated is subjected to a photo process and then etched to remove the gate film formed in the step of FIG. The step of exposing the silicon surface is shown. In the figure, reference numeral 3 denotes a gate oxide film after the gate film is removed from the PMOS area.

FIG. 3D is a view showing a state of forming a gate oxide film after performing a second gate oxidation step after exposing silicon in the PMOS area. 4 in FIG.
The gate oxide film when the silicon wafer after the removal of the oxide film in the PMOS area is oxidized in the same step as the oxidation condition of (b) is shown. As is clear from the figure, the PMOS once removed
It can be seen that a thin oxide film is formed in the area, and a thick oxide film is formed in the NMOS area which is not to be removed.

The gate oxidation conditions may be changed between the initial gate film simultaneous oxidation condition and the condition after the gate oxide film on the PMOS side is removed. Although the increase in the process conditions complicates the production, the lowering of the temperature to some extent leads to the advantage that the oxide film formation rate can be kept low and the film thickness can be controlled more precisely.

The process of FIG. 3E is performed by LOCOS (Loc
FIG. 2 shows a process diagram for forming an Al Oxidation of Silicon (local oxidation of silicon). In the case of LOCOS formation, it is necessary to increase the thickness of the oxide film. Therefore, the silicon oxidation rate is increased by wet oxidation. Subsequent steps are very ordinary CMOS element manufacturing steps, and therefore, detailed description is omitted in this embodiment.

FIG. 4 shows an embodiment of the second manufacturing process for realizing the present invention. 4 (a) to 4 (e) show cross sections of the silicon substrate in each of the manufacturing steps, and the emphasis will be given to the specific manufacturing steps of the present invention. In addition, differences from FIG. 3 will also be mainly described.

FIG. 4A is a view of a silicon substrate on which necessary wells are already formed. Where well is PM
It may be a twin-well structure for OS and NMOS, or it may be understood that P-well (N-well) is just formed if it is a single well process of N-type silicon (P-type). In the figure, reference numeral 1 denotes a silicon substrate.

FIG. 4B shows a gate oxide film process which is performed for the first time, and shows a situation in which a gate oxide film is simultaneously formed on the PMOS and NMOS element formation areas. Reference numeral 2 in the figure denotes a gate oxide film formed at this stage.

FIG. 4C is a diagram in which an Si ₃ N ₄ (silicon nitride) film through which oxygen molecules do not pass is formed so that the oxidation does not proceed further to the PMOS element formation area. In the figure, reference numeral 6 denotes a Si ₃ N ₄ film serving as an oxidation prevention mask.

FIG. 4D is a cross-sectional view of the element structure in the case where the oxidation prevention mask for the PMOS area is applied in FIG. 4C and then the gate oxidation is continued. In the drawing, reference numeral 4 denotes a gate oxide film formed in this step.

The process of FIG. 4E is performed by LOCOS (Loc
FIG. 2 shows a process diagram for forming an Al Oxidation of Silicon (local oxidation of silicon). After this step, it is a very ordinary CMOS element manufacturing step.
Description is omitted.

In FIG. 4, as described above,
After forming the gate oxide film on the PMOS side to a certain thickness,
In this method, oxidation is prevented by an oxygen molecular mask. In this method, unlike the above-described removal of the oxide film on the PMOS side, there is the convenience that the silicon-oxide film interface can be connected to the final step without being exposed.

[0052]

As is clear from the examples described above, the present invention makes it possible to solve the above-mentioned problems in the prior art. Not only that, PMOS, N
Since the MOS element balance is improved, the PMOS element area occupying a large area can be reduced to about 1/3 (equivalent to the NMOS element area) in the layout design of the basic cell, and the cell size can be made compact (simple). Assuming an inverter cell as a calculation example, the height of the basic cell can be reduced by about 40% by adopting the present invention).

In a pattern layout of a so-called I / O terminal (a pad for connecting a logic circuit inside a chip and an external signal; hereinafter, abbreviated as an I / O cell) requiring a large current driving capability, a PMOS size, The size of the NMOS formation area is well-balanced, and the conventional I / O
The height of the cell (here, the height refers to the distance from the bonding pad Al wiring area to the internal logic via the buffer transistor) can be reduced by about 40%.

This effect means that, when an integrated circuit having the same chip size is assumed, the effective area of the internal logic formation area can be increased, so that an integrated circuit with a high degree of integration can be manufactured.

The present invention is not limited to a specific solution for simply balancing P and N of CMOS. For example, in recent years, the process has evolved from the sub-micron region to the deep sub-micron region, but it is generally difficult to shorten the channel length of the PMOS by 1: 1 following the channel length of the NMOS. This is mainly due to the low punch-through breakdown voltage of the PMOSFET. Under such circumstances, the current capacity balance between PMOS and NMOS may be further expanded. In the present invention, the identity of element areas has been described from a priority standpoint, but application to such issues is also possible. In that case, although the size does not reach the same size, the area expansion on the PMOS side can be kept to a necessary minimum, and the application range is wide.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of an element layout according to the present invention.

FIG. 2 is a cross-sectional structural view of an element according to the present invention.

3 (a) to (e) each according to the invention,
FIG. 4 is an explanatory diagram of a first element manufacturing process.

4 (a) to (e) each according to the present invention,
Explanatory drawing of a 2nd element manufacturing process.

FIG. 5 is a diagram of an example of a conventional CMOS device structure.

[Explanation of symbols]

1 ... silicon substrate 2 ... gate oxide film 3 ... PMOS area portion oxide film removal after the gate oxide film formed by the gate oxide film 4 ... reoxidation of 5, 6 ... _Si 3 N ₄ membranes

Claims (3)

[Claims] 1. In forming a CMOS semiconductor device integrated on a silicon substrate, CMOS basic element, that is, P-channel MOSFE
1. The element formation area sizes of the T and N channel MOSFETs are substantially equal; In addition, the gate oxide film thickness of the PMOSFET is
A method for forming a semiconductor device, comprising forming a thin film in a range of 1/2 to 1/3 of an oxide film thickness of a FET. 2. In the step of forming a semiconductor element, a PMOS and an NMOS gate oxide film are simultaneously formed first in a gate oxidation step before a LOCOS oxidation step (field formation) after a well drive-in. 1. Provide a gate oxide film etching step in the PMOS element formation area to expose the silicon surface on the PMOS side; In the second gate oxide film forming step, PM
OS formation area (bare silicon), NMOS formation area (oxide film already formed by first gate oxidation step)
Forming a gate oxide film for PMOS and NMOS with different thicknesses by performing simultaneous oxidation. 3. A specific step of forming a semiconductor element according to claim 2 is that, in the gate oxidation step after the Well drive-in and before the LOCOS oxidation step (field formation), a PMOS and NMOS gate oxide film are simultaneously formed. After applying, 1. A step of forming a mask layer for suppressing diffusion of oxygen atoms, such as a Si ₃ N ₄ film, is provided again in the PMOS element formation area; Thereafter, a gate oxide film for PMOS and NMOS is formed to a different thickness by restarting the gate oxide film forming step.