JPH1175083A - Horizontal synchronization stabilizing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent large fluctuation in an oscillation frequency of a voltage controlled oscillator during a vertical blanking period and after the end of the vertical blanking period. SOLUTION: A frequency comparison section 2000 detects whether or not an oscillation frequency fVXO of a voltage controlled oscillator 100 is within a predetermined frequency range based on an oscillation frequency fVIO of a reference oscillation source 600, frequency detection output signals APCOH, APCOL are fed to a low pass filter 500 in place of error output signals (a), (b), for a vertical blanking period by switches 10, 20 and an output signal of the low pass filter 500 is fed back to the voltage controlled oscillator 100 as a control voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a horizontal synchronization stabilizing device for realizing synchronization stabilization of a voltage controlled oscillator which is phase-locked to a composite synchronization signal.

[0002]

2. Description of the Related Art Conventionally, as a horizontal synchronization stabilizing device used for phase synchronization of a horizontal synchronization signal, a phase locked loop configuration as shown in FIG. 7 is employed. FIG.
, 1 is a composite synchronization signal input terminal to which the composite synchronization signal CSYNC is input. Reference numerals 10 and 20 are switches. 100 is the frequency f _VC according to the control voltage
_It is a voltage controlled oscillator (VCO) that generates the voltage of _O.
Reference numeral 200 denotes a 1 / N frequency divider that divides the output signal of the voltage controlled oscillator 100 by 1 / N to generate a frequency-divided signal DEV. 300 is a composite synchronizing signal CSYNC and a divided signal DEV
And a phase comparator that generates two error output signals a and b by comparing 400 is a composite synchronizing signal CSY
A vertical blanking generator for generating a vertical blanking period signal VBLK indicating a vertical blanking period based on NC. Reference numeral 500 denotes a low-pass filter which receives two error signals a 'and b' passed through the switches 10 and 20, respectively, generates an output signal c, and feeds it back to the voltage controlled oscillator 100 as a control voltage.

The operation of the horizontal synchronization stabilizing device having the above configuration will be described with reference to a time chart of FIG. In this horizontal synchronization stabilizing device, the horizontal synchronization signal of the composite synchronization signal CSYK, the frequency-divided signal DEV obtained by dividing the output signal of the voltage controlled oscillator 100 by 1 / N by the 1 / N frequency divider 200, and Are compared in phase by a phase comparator 300, the error output of the phase comparator 300 is smoothed by a low-pass filter 500, and the smoothed voltage is fed back to the voltage controlled oscillator 100 to form a phase locked loop. , The output signal of the voltage controlled oscillator 100 is phase-synchronized with the horizontal synchronization signal.

[0006] The phase comparison by the phase comparator 300 is performed only during the period of the width of the horizontal synchronizing signal, and is not performed outside the period. A frequency- _divided signal DEV obtained by dividing the output signal (frequency f _VCO ) of the voltage-controlled oscillator 100 to 1 / N by the 1 / N frequency divider 200 has a low level (hereinafter, referred to as “H”) in the width of the horizontal synchronization signal. Error output signals a and b are output from the phase comparator 300 by occupying a period of “Lo”) or a period of a high level (hereinafter referred to as “Hi”).

The error output signals a and b become a charging current and a discharging current for the low-pass filter 500, respectively. By feeding back the output voltage c of the low-pass filter 500 to the voltage controlled oscillator 100, the phase of the horizontal synchronizing signal CSYNC and the frequency-divided signal DEV obtained by dividing the frequency by 1 / N are synchronized.

[0006]

Conventionally, in a phase locked loop used for phase synchronization of a horizontal synchronization signal, an error output during a vertical blanking period is required when comparing phases in the width period of the horizontal synchronization signal. Met. More specifically, in the vertical blanking period shown in FIG. 8, that is, during the period when the vertical blanking period signal VBLK is "Hi", not only the horizontal synchronizing signal but also the equalizing pulse and the cut-in pulse are present.

Therefore, during the vertical blanking period, the error outputs a and b of the phase comparator 300 do not correspond to the original phase error. Therefore, conventionally, the switch 10,
20 and the error outputs a,
b, that is, the error output a becomes “Lo”
This problem has been solved by fixing the error output b to "Hi". The switches 10, 2
The error signals after passing through 0 are a 'and b'.

However, when the error outputs a and b of the phase comparator 300 are stopped during the vertical blanking period, the output voltage of the low-pass filter 500 slightly fluctuates due to the leak current, and the oscillation frequency f _VCO of the voltage controlled oscillator 100 is reduced. to be influenced. As a result, the vertical blanking period ends, and the error output a ′ of the phase comparison by the first horizontal synchronization signal
Alternatively, a maximum error output is generated as b '. For example, the maximum error output at time t ₁₀ will be fed back to the voltage controlled oscillator 100 via the low-pass filter 500, and had a new problem causing problems related to large variations in the oscillation frequency. In this figure, generating a maximum error output even time t _11.

It is an object of the present invention to provide a horizontal synchronization stabilizing device capable of preventing a large fluctuation in the oscillation frequency of a voltage controlled oscillator during and after a vertical blanking period.

[0010]

In order to achieve this object, a horizontal synchronization stabilizing apparatus according to the present invention is provided in which the oscillation frequency of a voltage controlled oscillator falls within a predetermined frequency range with respect to the oscillation frequency of a reference oscillation source. In the vertical blanking period, a frequency detection output signal of the frequency comparison unit is supplied to the low-pass filter in place of the output signal of the phase comparator during the vertical blanking period.

According to this configuration, it is possible to continuously supply a signal equivalent to the error signal to the low-pass filter even during the vertical blanking period, and the oscillation of the voltage controlled oscillator during and after the vertical blanking period is completed. A stable phase-locked loop without a large frequency fluctuation is obtained.

[0012]

A horizontal synchronization stabilizing device according to a first aspect of the present invention includes a reference oscillation source oscillating at a reference frequency, a voltage controlled oscillator oscillating at a frequency corresponding to a control voltage, a composite synchronization signal and a voltage controlled oscillator. A phase comparator for performing a phase comparison with the output signal of the reference oscillation source, and a frequency comparison unit that detects whether the oscillation frequency of the voltage-controlled oscillator is within a predetermined frequency range based on the oscillation frequency of the reference oscillation source, A low-pass filter that smoothes the error output of the phase comparator and the frequency detection output signal of the frequency comparator and feeds it back to the voltage controlled oscillator as a control voltage, and outputs the error output of the phase comparator during periods other than the vertical blanking period. Selectively supply to the low-pass filter, and selectively supply the frequency detection output signal of the frequency comparison unit to the low-pass filter during the vertical blanking period. It is way.

According to this configuration, during a period other than the vertical blanking period, the output of the phase comparator is fed back to the voltage-controlled oscillator through the low-pass filter, so that the output signal of the voltage-controlled oscillator is converted to the horizontal synchronization signal in the composite synchronization signal. And can be synchronized. Further, during the vertical blanking period, a signal equivalent to the error signal is continuously supplied to the low-pass filter, and during the vertical blanking period, the oscillation frequency of the voltage controlled oscillator falls within a predetermined frequency range. It is possible to fit. Therefore, large fluctuations in the oscillation frequency of the voltage controlled oscillator during and after the vertical blanking period can be avoided, and a stable phase locked loop can be obtained.

According to a second aspect of the present invention, there is provided a horizontal synchronization stabilizing apparatus, wherein the frequency comparison unit in the horizontal synchronization stabilizing apparatus according to the first aspect counts an output signal of a reference oscillation source as a clock input; A second counter that counts the output signal of the controlled oscillator as a clock input, and generates an output signal when the count value of the first counter reaches a first predetermined value to a reset input terminal of the second counter A first decoder for supplying an output signal when the count value of the first counter becomes a second predetermined value larger than the first predetermined value, and supplies the output signal to a reset input terminal of the first counter; A second decoder, a third decoder for generating an output signal when the count value of the second counter reaches a third predetermined value, and a count value of the second counter larger than the third predetermined value And a fourth decoder that generates an output signal when the predetermined value becomes 4, and operates only during the vertical blanking period, and inputs the output signals of the first, second, third, and fourth decoders, The third period during the period from the generation of the output signal of the first decoder to the generation of the output signal of the second decoder
And a detector for detecting whether or not the output signal of the fourth decoder is generated.

According to this configuration, during the vertical blanking period, the oscillation frequency of the voltage controlled oscillator can be set very accurately in the predetermined frequency range by the detection unit.
Therefore, the frequency fluctuation of the voltage controlled oscillator during and after the vertical blanking period can be predicted, and a stable phase locked loop can be obtained.

According to a third aspect of the present invention, in the horizontal synchronization stabilizing device, the detecting section of the horizontal synchronization stabilizing device is reset by an output signal of the first decoder and set by an output signal of the third decoder. A first RS latch which is reset by an output signal of the first decoder, a second RS latch which is set by an output signal of a fourth decoder, and an output signal of the second decoder. It comprises a first D flip-flop which takes in the output signal of the first RS latch and a second D flip-flop which takes in the inverted output signal of the second RS latch by the output signal of the second decoder. .

According to this configuration, when the oscillation frequency of the voltage-controlled oscillator exceeds a predetermined frequency range preset in the detecting section during the vertical blanking period, the information can be stored in the same detecting section. Further, according to the stored information, a signal equivalent to the output of the phase comparator in a period other than the vertical blanking period can be supplied to the low-pass filter, and a stable phase locked loop can be obtained.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a horizontal synchronization stabilizing device according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a composite synchronization signal input terminal to which a composite synchronization signal CSYNC is input. Reference numerals 10 and 20 denote switches for interrupting signals. 30 and 4
Reference numeral 0 denotes a signal synthesizer that synthesizes two signals.
_{Reference numeral} 100 denotes a voltage controlled oscillator (VCO) that generates a voltage having a frequency f _VCO according to the control voltage.

Reference numeral 200 designates an N-divided signal which generates the frequency-divided signal DEV by dividing the output signal of the voltage-controlled oscillator 100 by 1 / N and generates an enable signal EN having the same frequency as the frequency-divided signal DEV and a narrow pulse width. 1 divider. Reference numeral 300 denotes a phase comparator that generates two error output signals a and b by comparing the composite synchronization signal CSYNC with the frequency-divided signal DEV. Reference numeral 400 denotes a vertical blanking generator that generates a vertical blanking period signal VBLK indicating a vertical blanking period based on the composite synchronization signal CSYNC.
Reference numeral 500 denotes a low-pass filter (LPF) that receives two signals a ″ and b ″ output from the signal synthesizers 30 and 40 as input, generates an output signal c, and feeds back the control signal to the voltage-controlled oscillator 100 as a control voltage. Reference _numeral 600 denotes a reference oscillation source (VXO) that oscillates at an oscillation frequency f _VXO .

Reference numerals 700 and 800 denote a decoder which counts the pulses of the oscillation signal of the voltage controlled oscillator 100 and generates a frequency detection output signal when the value of each signal reaches a predetermined value. _{Reference numeral} 900 denotes a 1 / M frequency divider that divides the oscillation frequency f _VXO by 1 / M. 1000 is a detection unit. A frequency comparison unit 2000 detects whether the oscillation frequency f _VCO of the voltage controlled oscillator 100 falls within a predetermined frequency range based on the oscillation frequency f _VXO of the reference oscillation source 600.

The signal synthesizers 30 and 40 operate the switches 10 and 20 during periods other than the vertical blanking period.
Is turned on and the detection unit 1000 does not operate, so that the error output signals a and b of the phase comparator 300 are selectively supplied to the low-pass filter 500. During the vertical blanking period, the switches 10 and 20 are turned off, and the detection unit 100
Since 0 operates, the frequency detection output signals APCOH and APCOL of the frequency comparison unit 2000 are selectively supplied to the low-pass filter 500.

The operation of the horizontal synchronization stabilizing device having the above configuration will be described below. In this horizontal synchronization stabilizing device, the output signal of the reference oscillation source 600 is applied to the input terminal of the 1 / M frequency divider 900, and the decode signals dec1 and dec2 output from the 1 / M frequency divider 900 are detected. It is sent to the unit 1000. A decoder (frequency divider) 70
An output signal of the voltage controlled oscillator 100 is applied to input terminals 0 and 800, and a decode signal dec1 is sent to decoders (frequency dividers) 700 and 800.

On the other hand, the output signal of the voltage controlled oscillator 100 is applied to the input terminal of the 1 / N frequency divider 200. Of the output signals of the 1 / N frequency divider 200, the frequency-divided signal is output. DEV is sent to phase comparator 300, and enable signal EN is sent to detection section 1000. Also, the decoded signals dec output from the decoders 700 and 800
3 and dec4 are sent to the detection unit 1000. Then, the detection unit 1000 includes the vertical blanking generator 400
Operates only during the high level period of the vertical blanking period signal VBLK input from
Based on c2, dec3 and dec4, the frequency detection output signals APCOH and APCOL are respectively converted into signal combiners 30 and 4
Send to 0. Signals a ″ and b ″ are output from the signal synthesizers 30 and 40 respectively, and the low-pass filter 50
The signal is sent to 0, smoothed, and fed back to the voltage controlled oscillator 100 as a control voltage.

The error output signals a and b of the phase comparator 300 pass through the switches 10 and 20 to output the error signals a 'and
After the signal b ′, the signals a ″ and b ″ pass through the signal combiners 30 and 40, and the signals a ″ and b ″ are further reduced by the low-pass filter 500 to the control voltage c of the voltage controlled oscillator 100.
, A phase locked loop is formed.

The configuration and operation of the frequency comparing section 2000 in the horizontal synchronization stabilizing apparatus of the present embodiment configured as described above will be specifically described below with reference to FIG. In FIG. 2, reference numeral 15 denotes an enable signal EN.
Is an enable signal input terminal to which is input. Reference numeral 16 denotes an input terminal to which the vertical blanking period signal VBLK is input. 17 and 18 are frequency detection output signals AP, respectively.
This is a frequency detection output signal output terminal from which COH and APCOL are output. 610 is a reference oscillation source signal input terminal. A first counter 620 counts an output signal of the reference oscillation source 600 as a clock input CK. 110 is a voltage controlled oscillator signal input terminal. Reference numeral 120 denotes a second counter that counts an output signal of the voltage controlled oscillator 100 as a clock input CK.

630 is a decode signal dec1 when the count value of the first counter 620 reaches a first predetermined value.
And supplies it as a reset input R to the second counter 120. 640 is a second counter where the count value of the first counter 620 is larger than the first predetermined value.
Is a second decoder that generates a decode signal dec2 when the predetermined value is reached and supplies it to the first counter 620 as a reset input R. 710 is the second counter 12
The third decoder generates a decode signal dec3 when the count value of 0 becomes a third predetermined value. 810
When the count value of the second counter 120 reaches a fourth predetermined value larger than the third predetermined value, the decode signal de
A fourth decoder for generating c4. Reference numeral 900 denotes a 1 / M frequency divider that divides the reference frequency by 1 / M.

Reference numeral 1000 denotes a vertical blanking period signal V
The first, second, third and fourth decoders 63 operate only during the vertical blanking period by inputting BLK.
Decode signals dec1, dec2, dec3, and dec4 output from 0, 640, 710, and 810 are input, and from the generation of the decode signal dec1 of the first decoder 630 to the generation of the decode signal dec2 of the second decoder 640. And fourth decoder 71 in the period
This is a detection unit that detects whether or not the decoded signals dec3 and dec4 of 0 and 810 are generated.

In FIG. 2, the second counter 12
0 and the third decoder 710 correspond to the decoder 700 in FIG.
The combination of and the fourth decoder 810 corresponds to the decoder 800 in FIG. Hereinafter, the frequency comparison unit 2
000 will be described. The first counter 620 counts the clock input CK of the frequency f _VXO ,
Is reset when the decoder 640 counts M clock inputs and outputs the decode signal dec2. When the first counter 620 is reset, the second decoder 64
The decode signal dec2 of 0 also disappears, and counting is started again. The first counter 620 and the second decoder 640 repeatedly perform this series of operations, whereby the 1 / M frequency division operation is performed.

On the other hand, the first counter 620 is also decoded by the first decoder 630. First decoder 63
0 outputs a decode signal dec1 when Q (Q <M) clock inputs are counted, and outputs the decoded signal dec1 to the second counter 1
20 as a reset input R, and to the detector 1000. Therefore, clock input C
The second counter 120 counting the output signal of the frequency f _VCO of the voltage controlled oscillator 100 as K repeats the counting operation while being reset by the decode signal dec1.

Then, during one cycle from reset to reset by the decode signal dec1 of the second counter 120, the third decoder 710 and the fourth decoder 8
10, decode signals dec3 and dec4 are generated and supplied to the detection unit 1000. In this case, the decode value of the third decoder 710 L _- is set to - _{(<L +} L), the decoded value of the fourth decoder 810 L _+.

Here, the count value of the second counter 120 is between the decode signal dec1 which is the reset signal of the second counter 120 and the decode signal dec2 which is the reset signal of the first counter 620.
_- unless generate a frequency detection output signal APCOL reached, the frequency detection output signal AP if reaches the decoded value L ₊
Generating a COH, decoded value L _- reached, the decode value L
If the value does not reach ₊ , the detection unit 1000 performs an operation of not generating anything as a detection output.

A series of operations in the detecting section 1000 are performed only in the vertical blanking period, and are not performed in other periods. Further, the frequency detection output signal APCOH,
APCOL is configured to be output only during the period of the enable signal EN. The configuration and operation of the detection unit 1000 in the frequency comparison unit 2000 performing the above operation will be described below with reference to FIG. FIG.
In the figure, reference numeral 11 denotes a decode signal input terminal for inputting the decode signal dec1 of the first decoder 630. 12
Is a decode signal input terminal for inputting a decode signal dec3 of the third decoder 710. Reference numeral 13 denotes a decode signal input terminal for inputting the decode signal dec2 of the second decoder 640. Reference numeral 14 denotes an input terminal for inputting a decode signal dec4 of the fourth decoder 810. Reference numeral 15 denotes an enable signal input terminal for inputting an enable signal EN. Reference numeral 16 denotes a vertical blanking period signal input terminal for inputting a vertical blanking period signal VBLK. 17 and 18 are frequency detection output signals APCOH, APCOL
Output terminal for outputting a frequency detection output signal.

Numerals 2 and 3 denote match gates (NAND gates), which constitute an RS latch 21. The decode signal dec1 is a reset input (or set input), and the decode signal dec3 is a set input (or reset input). ). Numerals 4 and 5 denote coincidence gates (NAND gates), which constitute an RS latch 22. The decode signal dec1 is a reset input (or set input), and the decode signal dec4 is a set input (or reset input). Reference numeral 6 denotes a D flip-flop, which uses the output of the RS latch 21 as a D input and the decode signal dec2 as a CK input. Reference numeral 7 denotes a D flip-flop, which has an inverted output of the RS latch 22 as a D input and a decode signal dec2 as a CK input. Reference numeral 8 denotes a coincidence gate (NAND gate) which receives the output signal of the D flip-flop 6 and the enable signal EN to generate a frequency detection output signal APCOH. 9 is a match gate (NAN
D gate), receives the output signal of the D flip-flop 7 and the enable signal EN as inputs, and outputs the frequency detection output signal AP
Generate COL.

The detecting section 1000 having the above configuration will be described in detail below. The decode signal dec1 is R
The decode signal dec3, dec4 is applied to one input terminal of each of the -S latch 21 and the RS latch 22, and the other input terminal of each of the RS latches 21, 22 is applied. The output signal of the RS latch 21 (the output of the coincidence gate 2) is applied to the D input terminal of the D flip-flop 6,
The output signal of the RS latch 22 (the output of the match gate 5) is applied to the D input terminal of the D flip-flop 7, and the decode signal dec2 is applied to the clock input terminals of the D flip-flops 6 and 7. The enable signal EN is applied to one input terminal of the match gates 8 and 9, and the output signals of the D flip-flops 6 and 7 are applied to the other input terminals of the match gates 8 and 9. The output signals of the coincidence gates 8 and 9 are input to the detection output signal output terminals 17 and 18, respectively, and the vertical blanking period signal VBLK is applied to the reset input terminals of the D flip-flops 6 and 7.

Here, the operation of the detection unit 1000 in FIG. 3 will be described with reference to the time chart in FIG. Decode signal d
When ec1 is input to the RS latches 21 and 22, the output 2a of the match gate 2 and the output 4a of the match gate 4 change from “Lo” to “Hi”, and the respective RS latches 21 and 22 change.
22 is a decode signal dec3 and a decode signal d, respectively.
It will be in a state of waiting for the arrival of ec4.

Next, the count value of the second counter 120 is decoded value L of the third decoder 710 _- to reach the decode signal dec3 is outputted, the coincidence gate 2 outputs 2a
Returns to “Lo”. Further, the second counter 120
Of the decoded value L ₊ of the fourth decoder 810
, The decode signal dec4 is output, and the output 4a of the coincidence gate 4 returns to “Lo”. Between the decode signal dec3 and the decode signal dec4, the reset signal of the first counter 620, that is, the second decoder 64
When the 0 decoded signal dec2 arrives (time t _A ),
No frequency detection output signals APCOH and APCOL are output (fixed to "Hi").

Next, at time t _B , the decode signal dec
When the second signal arrives, the count value of the second counter 120 exceeds the decode value L ₊ of the fourth decoder 810, and the RS latch 21 and the RS latch 22 at the timing of the edge of the decode signal dec2. As the output state, “Lo” is taken into the D flip-flop 6 and “Hi” is taken into the D flip-flop 7. As a result, APCOL is used as the frequency detection output signal to output the next decode signal d.
The period (width) of the enable signal EN is output until the arrival of ec2.

Next, at time t _C , the decoded signal dec2
Is reached, the count value of the second counter 120 becomes the third value.
Decode value L of the decoder 710 _- so not reached, respectively to the D flip-flop 6, 7 "Hi", "L
o ”is taken in, and APCO is output as a frequency detection output signal.
H is output during the period (width) of the enable signal EN until the next decode signal dec2 arrives. Therefore, the decoded value of the first decoder 630 is set to Q, and the second decoder 64
Assuming that the decoded value of 0 is M, the interval between the decoded signals dec1 and dec2 is (1 / f _VCO ) × (M−Q) [sec]. decode value L of the decoder 710 _-, in either no more than each greater than or decode value L ₊ of the fourth decoder 810,
The decode signal dec3 and the decode signal dec4 may or may not be output. Then, as a whole, the decoded value L _- if not exceeded (time t _C), and outputs the APCOH as a frequency detection output signal, the up frequency of the voltage controlled oscillator 100, when exceeding the decoded value L ₊ (time t _B ), AP as a frequency detection output signal
Outputs COL, bring down the frequency of the voltage controlled oscillator 100, the decode value L _- beyond and if not exceeded the decoded value L ₊ (time t _A), the frequency detection output signal has an operation that does not output. With such an operation, the voltage controlled oscillator 10 can be operated even during the vertical blanking period.
The oscillation frequency of 0 is stabilized.

Next, FIG. 5 shows the configuration of the signal combiners 30 and 40 in the horizontal synchronization stabilizing device of FIG. In FIG. 5, 31 and 41 are input terminals of error signals a 'and b' from the phase comparator 300 through the switches 10 and 20. 17 'and 18' are input terminals for frequency detection output signals APCOH and APCOL from the detection unit 1000. 35 and 45 are output terminals for output signals a ″ and b ″ output from the signal synthesizers 30 and 40, respectively.

The signal synthesizer 30 is composed of a coincidence gate 34 and an inverter 33. One input terminal of the coincidence gate 34 is applied with the frequency detection output signal APCOH, and the other input terminal is connected via the inverter 33. Error signal a '
Is applied, and the output terminal of the match gate 34 is
0 output terminal 35. On the other hand, the signal combiner 40 is composed of only a match gate (AND gate) 42, and a frequency detection output signal APCOL and an error signal b 'are applied to input terminals, respectively. It is connected to the output terminal 45.

The signal synthesizers 30 and 4 configured as described above
0, the frequency detection output signals APCOH, APCOH during periods other than the vertical blanking period, that is, during the normal comparison period.
Since PCOL is not output and is fixed at “Hi”, the output signals of the signal combiners 30 and 40 are respectively a ″ = a ′ and b ″ =
b '. On the other hand, during the vertical blanking period, the error signals a ′ and b ′ of the phase comparator 300 are not output, and a ″ = /
APCOH, b ″ = APCOL. The signal / A
PCOH is an inverted signal of the signal APCOH.

FIG. 6 is a time chart showing the operation before and after the vertical blanking, and corresponds to FIG. 8 of the conventional example. The composite synchronizing signal CSYNC, the frequency-divided signal DEV, and the vertical blanking period signal VBLK are the same as those of the conventional example. Is the same as
Looking at the output signal c of the low-pass filter 500, it can be seen that the fluctuation after the end of the vertical blanking period is small.
This is because the signal APCOL is supplied to the low-pass filter 500 as the signal b ″.

[0043]

As described above, according to the horizontal synchronization stabilizing device of the first aspect of the present invention, the oscillation frequency of the voltage controlled oscillator falls within the predetermined frequency range with respect to the oscillation frequency of the reference oscillation source. The frequency comparator detects whether the frequency is within the frequency range. During the vertical blanking period, the frequency detection output signal of the frequency comparator is supplied to the low-pass filter instead of the output signal of the phase comparator. Even if the operation of the phase locked loop phase comparator is stopped during the period, the signal equivalent to the error signal can be continuously supplied to the low-pass filter even during the vertical blanking period. During and after the end of the period, a stable horizontal synchronization phase locked loop without significant fluctuations in the oscillation frequency of the voltage controlled oscillator is obtained. That.

The horizontal synchronization stabilizing device of the present invention is integrated together with the video signal processing device. The video processing signal processing originally includes a reference oscillation source, and is provided with another reference oscillation source. Since there is no need, the cost increase can be minimized. Further, claim 2 of the present invention
According to the horizontal synchronization stabilizing device described above, during the vertical blanking period, the oscillation frequency of the voltage controlled oscillator can be set very accurately in the predetermined frequency range by the detection unit. Therefore, the frequency fluctuation of the voltage controlled oscillator during and after the vertical blanking period can be predicted, and a stable phase locked loop can be obtained.

According to the horizontal synchronization stabilizing device of the third aspect of the present invention, when the oscillation frequency of the voltage-controlled oscillator exceeds a predetermined frequency range set in advance in the detection section during the vertical blanking period, the apparatus is activated. Information can be stored in the same detection unit. Further, according to the stored information, a signal equivalent to the output of the phase comparator in a period other than the vertical blanking period can be supplied to the low-pass filter, and a stable phase locked loop can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a horizontal synchronization stabilization device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of a frequency comparison unit in the horizontal synchronization stabilization device shown in FIG.

FIG. 3 is a block diagram showing a specific configuration of a detection unit in the horizontal synchronization stabilization device shown in FIG.

FIG. 4 is a time chart showing an operation of the horizontal synchronization stabilizing device of FIG. 1;

FIG. 5 is a block diagram showing a specific configuration of a signal combiner in the horizontal synchronization stabilizing device shown in FIG.

FIG. 6 is a time chart showing an operation of the horizontal synchronization stabilizing device of FIG. 1;

FIG. 7 is a block diagram showing a configuration of a conventional horizontal synchronization stabilizing device.

FIG. 8 is a time chart illustrating an operation of the horizontal synchronization device illustrated in FIG. 7;

[Explanation of symbols]

 Reference Signs List 1 composite synchronization signal input terminal 2 match gate 3 match gate 4 match gate 5 match gate 6 D flip-flop 7 D flip-flop 15 enable signal input terminal 16 vertical blanking period signal input terminal 17 frequency detection output signal output terminal 17 'input terminal 18 Frequency detection output signal output terminal 18 'Input terminal 21 RS latch 22 RS latch 30 Signal combiner 31 Input terminal 32 Input terminal 33 Inverter 34 Match gate 35 Output terminal 40 Signal combiner 41 Input terminal 42 Match gate 45 Output terminal 100 Voltage controlled oscillator 110 Voltage controlled oscillator signal input terminal 120 Second counter 200 1 / N frequency divider 300 Phase comparator 400 Vertical blanking generator 500 Low pass filter 600 Reference oscillation source 610 Reference oscillation source signal input terminal Child 620 First counter 630 First decoder 640 Second decoder 700 Decoder 710 Third decoder 800 Decoder 810 Fourth decoder 900 1 / M frequency divider 1000 Detector 2000 Frequency comparator

Claims (3)

[Claims] A reference oscillation source that oscillates at a reference frequency; a voltage controlled oscillator that oscillates at a frequency corresponding to a control voltage; and a phase comparator that compares the phase of the composite synchronization signal with the output signal of the voltage controlled oscillator. A frequency comparison unit that detects whether the oscillation frequency of the voltage-controlled oscillator is within a predetermined frequency range based on the oscillation frequency of the reference oscillation source, an error output of the phase comparator, and the frequency A low-pass filter that smoothes a frequency detection output signal of a comparison unit and feeds it back to the voltage-controlled oscillator as a control voltage, and selectively outputs the error output of the phase comparator during a period other than a vertical blanking period. And selectively supplies a frequency detection output signal of the frequency comparison unit during the vertical blanking period to the low-pass filter. Horizontal synchronization stabilizer which is characterized in that so as to supply. 2. A frequency comparator, comprising: a first counter that counts an output signal of a reference oscillation source as a clock input; a second counter that counts an output signal of a voltage controlled oscillator as a clock input; A first decoder that generates an output signal when the count value of the counter reaches a first predetermined value and supplies the output signal to a reset input terminal of the second counter; A second decoder that generates an output signal when the second predetermined value is larger than a predetermined value of 1 and supplies the output signal to a reset input terminal of the first counter; A third decoder for generating an output signal when a predetermined value of 3 is output, and generating an output signal when a count value of the second counter becomes a fourth predetermined value larger than the third predetermined value. Do A fourth decoder that operates only during a vertical blanking period, receives output signals of the first, second, third, and fourth decoders and outputs the second signal from the output signal generation of the first decoder. 2. The horizontal synchronization stabilizing device according to claim 1, further comprising a detection unit that detects whether or not the output signals of the third and fourth decoders are generated until the output signal of the decoder is generated. A first RS latch that is reset by an output signal of the first decoder and is set by an output signal of the third decoder; and a reset unit that is reset by an output signal of the first decoder. A second RS latch set by an output signal of a fourth decoder; and a first D flip-flop that captures an output signal of the first RS latch by an output signal of the second decoder. 3. The horizontal synchronization stabilization device according to claim 2, further comprising a second D flip-flop that takes in an inverted output signal of the second RS latch with an output signal of the second decoder.