JPH1174534A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize an operating characteristic of a SOI type insulation gate transistor in a wide temperature range. SOLUTION: In a semiconductor device having insulation gate transistors 30 and 40 formed by using a silicon supporting substrate 1, an embedded film oxide (an insulation film) 2, and a silicon thin film 3, impurity concentration layers 33 and 43 formed near an interface between the silicon supporting substrate 1 and the embedded film oxide 2, and added more impurity than the impurity concentration of the silicon supporting substrate, electrodes 32 and 42 for controlling a potential of the impurity concentration layer, and a temperature compensation circuit varying the potential of the impurity concentration layer depending on the temperature through the electrodes and suppressing the formation of a back channel near the interface to the embedded film oxide of the silicon thin film, are formed. The voltage applied to impurity concentration layers 33 and 43 are controlled depending on the temperature variation, and a back channel generation is suppressed and a threshold voltage is stabilized in a wide temperature range.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an SOI (silicon-on-insulator) type MOS (metal oxide) in a semiconductor device.
semiconductor) A transistor.

[0002]

2. Description of the Related Art The structure of a conventional SOI-MOS transistor is shown in FIG. The silicon support substrate 1 contains a phosphorus element. On the silicon support substrate 1, a buried oxide film 2 is formed as an insulator thin film, and a single crystal silicon thin film 3 is formed thereon. Using this single crystal silicon thin film 3, an n-channel MOS transistor 30
And a p-channel MOS transistor 40
An OS transistor is formed. 7 is a source, 6 is a drain, 5 is a gate insulating film, and 4 is a gate electrode.
In the vicinity of the interface with the buried oxide film 2 of the silicon support substrate 1 immediately below the n-channel MOS transistor 30, a p-type impurity concentration layer 12 to which boron element is added at a concentration lower than 10 ¹⁷ cm ^-3 is formed. Further, in the p-type impurity concentration layer 12, the boron element contains 10 ¹⁷ cm in the vicinity of the interface with the buried oxide film 2 directly under the gate electrode 4.
A p-type impurity concentration layer 13 doped to a concentration of ^-3 or more is formed. The electrode 15 is formed on the p-type impurity concentration layer 12.
Is connected. Similarly, also in the p-channel MOS transistor 40, an n-type impurity concentration layer 14 to which phosphorus element is added to 10 ¹⁷ cm ⁻³ or more is formed near the interface with the buried oxide film 2 of the silicon support substrate 1 immediately below the gate electrode 4. The electrode 16 is connected to the layer 14.

[0003]

The SOI-MOS transistor may have a back channel due to its structure. That is, a parasitic MOS transistor having the single crystal silicon thin film 3 as an active layer, the buried oxide film 2 as a gate insulating film, and the silicon support substrate as a gate electrode is formed, and a back channel is formed at the interface between the crystalline silicon thin film 3 and the buried oxide film 2. Is formed. As the temperature increases, the carrier concentration of the inversion layer increases, so that a back channel is easily formed. Therefore, the SOI-CMOS transistor having the structure in FIG. 3 has a problem that a back channel is formed as the temperature increases, and a circuit using the SOI-CMOS transistor malfunctions. This SOI-MOS
In order to suppress the formation of a back channel due to a temperature rise in the transistor, the p-type impurity concentration layer 13 is biased to a potential as small as possible (negatively large) and n
It is necessary to bias the potential of the type impurity concentration layer 14 to a potential as large as possible. However, conventional MO
In the S transistor, if the potential of the p-type impurity concentration layer 13 is excessively reduced (negatively increased), the n-channel M
There is a problem that the threshold voltage of the OS transistor 30 largely changes in the positive direction. Further, if the potential of the n-type impurity concentration layer 14 is excessively increased, there is a problem that the threshold voltage of the p-channel MOS transistor largely changes in the negative direction. As a result, there arises a problem that a desired circuit operation cannot be obtained. According to the present invention, in a conventional SOI-MOS transistor, the formation of a back channel which is easily formed due to a rise in temperature is suppressed irrespective of a temperature change, and the potential of the p-type impurity concentration layer 13 or the n-type impurity concentration layer 14 is reduced. It is an object of the present invention to stabilize the operating characteristics of a transistor over a wide temperature range by minimizing the variation of the threshold voltage for turning on and off the transistor to the applied potential.

[0004]

According to the present invention, there is provided an insulator film formed on a silicon supporting substrate, a silicon film formed on the insulator film, and a silicon film formed using the silicon film. In a semiconductor device having an insulated gate transistor, an impurity concentration layer formed near an interface between a silicon support substrate and an insulator film and doped with an impurity equal to or higher than the impurity concentration of the silicon support substrate, and a potential of the impurity concentration layer. An electrode for controlling, and a temperature compensation circuit for changing the potential of the impurity concentration layer via the electrode in accordance with the temperature to suppress formation of a back channel near an interface between the silicon film and the insulator film. It is characterized by.

When the above-mentioned insulated gate transistor is a p-channel MIS transistor, the impurity concentration layer is n-type, and when the above-mentioned insulated gate transistor is an n-channel MIS transistor, the impurity concentration layer is n-type. Is p-type. Further, a complementary transistor in which a p-channel MIS transistor and an n-channel MIS transistor are arranged in series on a silicon support substrate may be used. Transistors are enhancement type (normally-off type) and depletion type (normally-on type)
Any of the above is applicable.

[0006] The temperature compensation circuit connects, for example, a series connection of a temperature-sensitive resistance element such as a thermistor and a resistance element whose resistance value does not change with temperature to a voltage source, and connects the potential of the connection point of the resistance element to an electrode. It can be configured with a circuit to apply. This temperature compensation circuit may be provided outside the above semiconductor device, or may be formed on a silicon support substrate or a silicon thin film.

Further, the temperature compensation circuit may be a circuit in which a carbon layer is formed on the impurity concentration layer, and a voltage is applied to the impurity concentration layer via the carbon layer. This carbon layer may be formed in a silicon thin film and connected to the impurity concentration layer. At this time, an electrode for controlling the potential of the impurity concentration layer is formed on the carbon layer.

[0008]

The semiconductor device according to the present invention has a structure in which a potential is applied to the impurity concentration layer formed near the interface of the silicon support substrate with respect to the insulator film via an electrode. It is configured to change. The temperature characteristic of this potential is such that the formation of a back channel formed near the interface between the silicon film and the insulator film is suppressed regardless of the temperature. Therefore, the present semiconductor device is a semiconductor device that can operate over a wide temperature range.

A circuit in which a temperature compensating circuit is connected in series with a temperature-sensitive resistance element such as a thermistor and a resistance element whose resistance value does not change with temperature to a voltage source, and a potential at a connection point of the resistance element is applied to an electrode. With this configuration, the usable temperature range of the semiconductor device can be expanded with a simple circuit configuration.
The temperature compensation circuit is a circuit in which a carbon layer is formed in the impurity concentration layer, and a voltage is applied to the impurity concentration layer through the carbon layer. The potential applied to the impurity concentration layer is determined by the temperature characteristic of the resistance value of the carbon layer. Can be varied with temperature.
Thus, the operable temperature range of the semiconductor device can be expanded with a simple circuit configuration.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described based on specific embodiments. The present invention is not limited to the following examples. FIG. 1 shows a cross-sectional structure of a semiconductor device according to a first embodiment of the present invention. The silicon support substrate 1 contains a phosphorus element. On the silicon support substrate 1, a buried oxide film 2 having a thickness of 85 nm is formed as an insulator thin film.
A single crystal silicon thin film 3 of 175 nm is formed. A MOS transistor is formed in the single-crystal silicon thin film 3 as an insulated gate transistor.

The single-crystal silicon thin film 3 has an n-channel M
A C-MOS transistor including the OS transistor 30 and the p-channel MOS transistor 40 is formed. The n-channel MOS transistor 30 has an n-conductivity type source 37 and a drain 36 and a p-conductivity type channel region 3.
1, a gate insulating film 35 and a gate electrode 34. Similarly, p-channel MOS transistor 40
It comprises a conduction type source 47 and a drain 46, an n conduction type channel region 41, a gate insulating film 45 and a gate electrode 44. The source 37 is connected to a 0V power supply (earth), and the drain 47 is connected to a 3V power supply.

In the vicinity of the interface between the silicon support substrate 1 and the buried oxide film 2 immediately below the n-channel MOS transistor 30, a p-type impurity concentration layer 33 doped with boron element at a concentration of about 10 ¹⁷ cm ^-3 is formed. I have. Then, a carbon layer 38 is formed by sputtering of a carbon element on a portion where the electrode forming portion of the p-type impurity concentration layer 33 and the buried insulating film 2 and the silicon thin film 3 thereon are etched. The carbon layer 38 has a depth of 0.3 μm and an area of 1 μm × 1 μm.
It has the size of The electrode 32 is formed on the carbon layer 38. A voltage of -5 V is applied to the electrode 32.

Further, a p-type impurity concentration layer 18 to which boron element is added at a concentration of about 10 ¹⁶ cm ^-3 is formed in a part of the p-type impurity concentration layer 33. This p-type impurity concentration layer 18 has a depth of 0.3 μm and an area of 18 μm × 1.
8 μm. The p-type impurity concentration layer 18 is connected to a 0 V power supply (earth).

Similarly, p-channel MOS transistor 4
Near the interface with the buried oxide film 2 of the silicon support substrate 1 just below zero, an n-type impurity concentration layer 43 in which phosphorus element is added at a concentration of about 10 ¹⁷ cm ⁻³ is formed. Then, a carbon layer 48 having the same size as the carbon layer 38 is formed on a part of the n-type impurity concentration layer 43, and the electrode 42 is formed on the carbon layer 48. A voltage of 5 V is applied to the electrode 42.

Further, in a part of the n-type impurity concentration layer 43,
An n-type impurity concentration layer 19 in which phosphorus element is added at a concentration of 10 ¹⁶ cm ⁻³ is formed. The size of the n-type impurity concentration layer 19 is the same as that of the p-type impurity concentration layer 18. This n-type impurity concentration layer 19 is connected to a 0 V power supply (earth).

The carbon layers 38 and 48 have a characteristic that the resistance value decreases with an increase in temperature. Due to this characteristic, as the temperature rises from 27 ° C. to 300 ° C., the potential of the p-type impurity concentration layer 33 decreases from −3 V to −4 V,
The potential of the n-type impurity concentration layer 43 increases from 3V to 4V. As a result, it is possible to suppress the occurrence of a back channel, which is easily formed due to a rise in temperature, and to minimize fluctuations in the threshold voltage due to the application of a substrate bias, thereby achieving stable circuit operation over a wider temperature range. can do. The carbon layers 38 and 48 and the electrodes 32 and 4
2 and a power supply connected to this electrode and a p-type impurity concentration layer 1
8. The temperature compensation circuit is constituted by the n-type impurity concentration layer 19.

FIG. 2 shows a sectional structure of a second embodiment of the present invention. The configurations of the silicon support substrate 1, the buried oxide film 2, the n-channel MOS transistor 30, and the p-channel MOS transistor 40 are the same as those of the first embodiment and the semiconductor device. Further, as in the first embodiment, the p-type impurity concentration in which boron element is added to a concentration of about 10 ¹⁷ cm ⁻³ near the interface with the buried oxide film 2 of the silicon support substrate 1 immediately below the n-channel MOS transistor 30. Layer 33 and p-channel M
Immediately below the OS transistor 40, an n-type impurity concentration layer 43 to which a phosphorus element is added at a concentration of about 10 ¹⁷ cm ⁻³ is formed near the interface with the buried oxide film 2 of the silicon support substrate 1. An electrode 32 is provided on the p-type impurity concentration layer 33,
An electrode 42 is formed on the p-channel MOS transistor 40.

The temperature compensating circuit of the n-channel MOS transistor 30 is constituted by a series connection circuit of a thermistor 123 whose resistance value decreases as the ambient temperature increases, a resistor 124 having a lower temperature dependency than the thermistor 123, and a power supply 121. Have been. Then, the thermistor 123 and the resistor 124
Is connected to the electrode 32. Similarly, p
The temperature compensating circuit of the channel MOS transistor 40 has a thermistor 223 whose resistance value decreases as the ambient temperature increases.
And a resistor 224 having a lower temperature dependency than the thermistor 223
And a power supply 221.
The connection point b between the thermistor 223 and the resistor 224 is connected to the electrode 42.

The power supply 121 is at -5V, and the power supply 221 is at 5V. In the semiconductor device of this embodiment, as in the first embodiment, as the temperature increases from 27 ° C. to 300 ° C.,
The potential of the p-type impurity concentration layer 33 decreases from -3V to -4V, and the potential of the n-type impurity concentration layer 43 increases from 3V to 4V. As a result, it is possible to suppress the occurrence of a back channel that is likely to be formed due to a rise in temperature, to minimize fluctuations in threshold voltage due to application of a substrate bias, and to realize stable circuit operation over a wider temperature range. can do.

This temperature compensation circuit may be formed in the silicon holding substrate 1 or in the silicon thin film 3.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of a semiconductor device according to a first specific example of the present invention.

FIG. 2 is a sectional view showing a configuration of a semiconductor device according to a second specific example of the present invention;

FIG. 3 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 silicon support substrate 2 buried oxide film 3 silicon thin film 30 n-channel MOS transistor 40 p-channel MOS transistor 33 p-type impurity concentration layer 34 gate electrode 35 gate oxide film 37 and 47 sources 36 and 46 ... Drains 31, 41 ... Channel layers 38,48 ... Carbon layers 123,223 ... Thermistors

Claims (1)

[Claims] 1. A semiconductor having an insulator film formed on a silicon support substrate, a silicon film formed on the insulator film, and an insulated gate transistor formed using the silicon film. An apparatus, comprising: an impurity concentration layer formed near an interface between the silicon support substrate and the insulator film, the impurity concentration layer being doped with an impurity concentration equal to or higher than the impurity concentration of the silicon support substrate; and controlling an electric potential of the impurity concentration layer. An electrode, and a temperature compensation circuit that changes the potential of the impurity concentration layer via the electrode in accordance with the temperature and suppresses the formation of a back channel near the interface between the silicon film and the insulator film. A semiconductor device characterized by the above-mentioned.