JPH1173788A - Non-volatile semiconductor multi-value memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the storage of multi-value information by successively impressing plural different voltages on the control gate of a memory cell and judging whether a memory cell reaches a desired threshold voltage based on the current value of the memory cell. SOLUTION: Memory cells M1-Mmn store data of four values, '10', '11', '01', '00' in correspondence to the threshold voltages, V1 to V4. Desired word lines W1-Wm are selected and a verification word line voltage VR1 is impressed using a verification word line voltage generating circuit VWG1. The voltage VR1 is a voltage between the threshold voltages V1 and V2 and the memory cells M1-Mmn which is made on by this voltage is discriminated to have data '10'. Y selection signals YS1-YSn are successively made on and the results on each bit line B1-Bn are stored. The verification word line voltages, VR2 and VR3, which are voltages interposing between each of V2 to V4 are successively impressed and the memory cells M1-Mmn that are made on are discriminated to find each of storage data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device suitable for a flash memory which performs writing / erasing using a Fowler-Nordheim tunnel current, and in particular, stores information of 2 bits or more per memory cell. The present invention relates to a nonvolatile semiconductor multi-value storage device.

[0002]

2. Description of the Related Art Conventionally, as a nonvolatile semiconductor memory device,
A flash memory having a configuration shown in FIG. 18 is known.
In the following description, reference numerals representing terminal names also serve as wiring names and signal names, and in the case of a power supply, also serve as a voltage value.

[0003] The configuration of the flash memory shown in FIG. 18 is based on the 1994 Symposium on VSI.
Circuits Digest of Technical Papers Pages 61-62 (1994 Symposium on VLSI Circ
uits Digest of Technical Papers, pp. 61-62). Writing and erasing to a memory cell are performed using a Fowler-Nordheim tunnel current. FIG.
In the figure, reference numerals M11 to Mmn indicate flash memory cells, and the source and the drain of the m memory cells are commonly connected to each other. For example, the memory cell M1
In M1, M21 to Mm1, the source of each memory cell is connected at each source diffusion layer to become a source s1, and the drain is connected at each drain diffusion layer to become a drain d1. With such a configuration, the area of the memory cell is reduced by reducing the number of contacts. The MOS transistors MD1 to MDn and MS1 to MSn respectively include sources s1 to sn and drains d1 to dn and bit lines B1 to Bn or a common source line VN of a plurality of m memory cells.
And a switching MOS transistor connected to the switch. NS
1 and NS2 are control signals for these switching MOS transistors. W1 to Wm are word lines, and WD
1 to WDm are word drivers. VH and VL are power supply terminals of the word drivers WD1 to WDm, and the chip has a plurality of sets each including the word drivers WD1 to WDm, and the corresponding voltage VH or VL is selectively applied. . D1 to Dm are gate signal terminals of the word driver. The bit lines B1 to Bn are connected to circuits K1 to Kn including a sense circuit, an information holding circuit at the time of writing, and an automatic write verifying circuit.

As described in the above-mentioned conventional example, the threshold voltage of each memory cell is determined for every memory cell connected to one word line using the circuits K1 to Kn. Is controlling. IO connects the read signal of the bit line selected by the Y select signals YS1 to YSn among the read signals appearing on the bit lines to the subsequent amplifier, and also writes the write information to the circuits K1 to Kn.
This is an input / output signal line selected and transferred by S1 to YSn.
In the figure, Y select signals YS1 to YS are applied to one input / output line IO.
Although the case where connection is selected by n has been described, a plurality of input / output lines IO may be provided and connected to a plurality of bit lines at the same time. MZ1 to MZn are MOS transistors that determine whether or not all memory cells are in a written state after write verification. When all the bit lines B1 to Bn reach the voltage VS after the write verification, the signal line A
No current flows through L.

[0005] In the flash memory having the above configuration, the charge of the floating gate of each memory cell is injected or released by the tunnel current, and information is stored by the threshold voltage of the transistor at that time. Two values are selected as threshold voltages, and one bit of information is stored per memory cell. The conventional flash memory cell has a so-called AND type configuration.

[0006] Regarding a multi-valued flash memory, for example, 1995 IEE International Solid State Circuits Conference, pp. 132-133 (1995 IEEE Interna
tional Solid-State Circuits Conference, pp.132-13
It is described in 3). The flash memory cell has a so-called NOR type configuration, in which hot electron injection is used for writing, and Fowler-Nordheim tunnel current is used for erasing. In this conventional example, a two-stage sense amplifier and a plurality of dummy cells are provided for each of input / output lines (IO lines) outside the memory cell array, and these are switched to generate a current corresponding to information when a word line is activated. Is detected.

[0007]

However, in the above-described conventional flash memory shown in FIG. 18, the degree of integration can be improved by devising a fine processing technique, but the process cost increases with the miniaturization. There was a disadvantage that it became. In order to solve this problem, a so-called multi-value storage that stores information of 2 bits or more per memory cell is considered. On the other hand, in the latter conventional example described above, a multi-valued flash memory of a NOR type configuration is realized by using a plurality of sense amplifiers for input / output lines because of a configuration in which reading is performed in byte units. In this case, for example, 512 bytes are read in parallel at a time. Therefore, if provided for each bit line, there is a problem that the circuit scale becomes large.

Therefore, an object of the present invention is to perform both writing and erasing by using a Fowler-Nordheim tunnel current as in the above-mentioned AND type conventional example, and to perform all memory cells connected to one word line. Therefore, it is an object of the present invention to provide a nonvolatile semiconductor multi-value storage device capable of storing multi-bit information of 2 bits or more suitable for a flash memory having a configuration in which the threshold voltage of the memory cell is controlled for each memory cell.

[0009]

In order to achieve the above object, in a nonvolatile semiconductor multi-value storage device according to the present invention, a memory cell has a floating gate and a control gate, and a tunneling phenomenon is used for the floating gate. In a non-volatile semiconductor multi-valued memory device for storing and storing a plurality of bits of information per memory cell by taking in and out a charge, voltage generating means for generating a plurality of voltages for reading and verifying, and a voltage applied to a control gate of the memory cell Means for sequentially applying a plurality of voltages of the generating means and determining whether or not the memory cell has reached a desired threshold voltage based on a current value flowing through the memory cell at this time. Things.

Further, in the nonvolatile semiconductor multi-value storage device according to the present invention, the memory cell has a floating gate and a control gate, and charges are taken in and out of the floating gate by using a tunnel phenomenon, so that a plurality of memory cells are provided for each memory cell. In a nonvolatile semiconductor multi-valued memory device that stores bit information, a plurality of dummy cells each having a different threshold voltage, and a predetermined voltage applied to a control gate of the memory cell to reduce a current value flowing through the memory cell at this time. Means for determining whether or not the memory cell has reached a desired threshold voltage based on the plurality of dummy cells based on the threshold value.

Alternatively, in the nonvolatile semiconductor multi-value storage device according to the present invention, the memory cell has a floating gate and a control gate, and charges are taken in and out of the floating gate by using a tunnel phenomenon, so that a plurality of memory cells are provided for each memory cell. In a nonvolatile semiconductor multilevel storage device for storing bit information, a plurality of sense latch circuits provided via a switch for each bit line, and desired different threshold voltages connected to the respective sense latch circuits via a switch And at least a plurality of dummy cells each having
A predetermined voltage is applied to the control gate of the memory cell, and based on the current value flowing through the memory cell at this time, whether or not the memory cell has reached a desired threshold voltage is sequentially switched and connected to the sense latch circuit. The sense latch circuit may be configured to sequentially switch and connect the plurality of dummy cells to make a determination.

Further, in the nonvolatile semiconductor multi-value storage device according to the present invention, the memory cell has a floating gate and a control gate, and charges are taken in and out of the floating gate by using a tunnel phenomenon, so that a plurality of memory cells are provided for each memory cell. In a nonvolatile semiconductor multi-value storage device for storing bit information, a sense latch circuit provided for each bit line and used in a binary read mode, a plurality of dummy cells having different threshold voltages, and each dummy cell are selected. A multi-valued sense circuit for use in a multi-valued read mode comprising a plurality of sense amplifiers for comparing and judging each threshold voltage of a memory cell, and each of the sense latch circuits and the multi-valued sense circuit are connected to data output lines by switching. At least a plurality of switches, a burst read binary mode and a random read It can be configured to be capable of switching the multi-level mode.

In any of the above nonvolatile semiconductor multi-value storage devices, an operation of applying a write pulse for giving a voltage necessary for taking in and out the electric charge to each memory cell, and thereafter, the memory cell is set to a desired threshold voltage An operation of applying a voltage to the control gate of the memory cell to verify whether or not the operation has been completed based on the current value flowing through the memory cell at this time is defined as 1
As a cycle, when the write / verify cycle is repeated, the write / verify cycle proceeds a predetermined number of times, and the pulse width of the write pulse is set to be large, or the absolute value of the pulse voltage of the write pulse is increased. It is preferable that the setting is made such that

[0014] In addition, 1 corresponding to the plurality of bit information.
It is preferable to set the Hamming distance between information corresponding to adjacent threshold voltages to a minimum among a plurality of threshold voltages that can be set for the memory cell.

In this case, the plurality of pieces of bit information are set as 2-bit information, and the four threshold voltages that can be set in one memory cell corresponding to the 2-bit information are sequentially set from the lowest or the highest. The corresponding information is “00”, “0”
1 "," 11 ", and" 10 "may be set.

Further, the threshold voltage of the memory cell after the irradiation of the ultraviolet ray is the lowest threshold voltage among the four settable threshold voltages, that is, the lowest threshold voltage among the four threshold voltages. The lowest voltage within the variation range around the voltage and the maximum voltage of the threshold voltage adjacent thereto, ie, 4
Between the maximum voltage within the variation range around the highest threshold voltage, or between the maximum voltage of the highest threshold voltage and the minimum voltage of the adjacent threshold voltage. It is preferable to set such that.

In addition, a threshold value when the Hamming distance between information corresponding to adjacent threshold voltages is the largest among the plurality of threshold voltages that can be set in one memory cell corresponding to a plurality of information. Between the voltages, the threshold voltage of the memory cell after the ultraviolet irradiation may be set.

In this case, the information of the plurality of bits is set as 2-bit information, and the four threshold voltages that can be set for one memory cell corresponding to the 2-bit information are arranged in order from the lowest or the highest. The corresponding information is “00”, “0”
When the threshold voltage is “1”, “10”, or “11”, the threshold voltage of the memory cell after the irradiation of the ultraviolet ray is the threshold voltage corresponding to “01” and the threshold voltage corresponding to “10”. It may be set in the middle.

[0019]

According to the nonvolatile semiconductor multi-value storage device of the present invention, at the time of reading or verification, voltage means for generating a plurality of voltages, that is, the word line voltage generating circuit VWG1 in FIG. The memory cell having the lowest threshold voltage among the plurality of threshold voltages of the memory cells corresponding to the multi-value information is determined by the first word line voltage from the lowest. Next, a memory cell having the next lower threshold voltage is determined based on the second word line voltage. Similarly, a plurality of word line voltages are used in accordance with the number of bits per memory cell. Alternatively, as shown in FIGS. 4 and 5, a plurality of dummy cells having a threshold voltage corresponding to an intermediate voltage between the threshold voltages of the written memory cells are provided, and the dummy cells and the current of the memory cells are reduced. Reading or verification of multi-valued information is performed by successive comparison.

At the time of writing, as shown in FIG.
Writing is performed on the memory cell in the state with the highest threshold voltage (erase state), and it is verified whether or not the writing has been performed, that is, whether or not the threshold voltage of the memory cell has reached a desired value. The determination is made based on whether the memory cell current flows from the first word line voltage. At this time, a memory cell to be set to a lower threshold voltage is also determined by the first word line voltage. As a result, the memory cells having the threshold voltage to be determined by the first word line voltage and the memory cells having the threshold voltage lower than the threshold voltage are all the threshold voltage determined by the first word line voltage. Becomes Next, writing is performed on a memory cell having a threshold voltage lower than the threshold voltage determined by the first word line voltage,
The verification of whether or not the data has been written is determined by whether or not the memory cell current flows by the second word line voltage from the higher side. At this time, memory cells having a threshold voltage lower than the threshold voltage determined by the second word line voltage are also performed at the same time. Similarly, the verification is performed using a plurality of word line voltages corresponding to the number of bits per memory cell.

[0021]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a nonvolatile semiconductor multi-value storage device according to the present invention.

<Embodiment 1> FIG. 1 is a circuit diagram of a main part showing a first embodiment of a nonvolatile semiconductor multilevel storage device according to the present invention. In FIG. 1, the same components as those of the conventional example shown in FIG. 18 will be described with the same reference numerals.

In this embodiment, word line voltage generating circuits VWG1 and VWG2 are provided for generating a plurality of word line voltages during read and write / verify operations. As a result, a plurality of bits can be read or written per memory cell as described below. Note that the word line voltage generation circuits VWG1 and VWG1
WG2 can also include a decode function, in which case a voltage can be applied only to a specific set of word drivers. In particular, reading and verification are performed using a word line voltage generation circuit VWG1 that generates a plurality of voltages, and the circuit configuration and the like will be described later. The word line voltage generation circuit VWG2 is a circuit that generates a negative voltage or a ground voltage at the time of writing, and can suitably use the internal power supply generation circuit disclosed in Japanese Patent Application Laid-Open No. 8-115599 filed by the present applicant.

In FIG. 1, reference numerals SL1 to SLn denote sense latch circuits, Vr denotes a reference voltage terminal, and PR denotes a signal for controlling a MOS transistor connecting the reference voltage terminal Vr and the sense latch circuits SL1 to SLn. In this figure, the automatic verification circuit and the like included in the circuits K1 to Kn of the conventional example shown in FIG. 18 are omitted.

FIGS. 2A and 2B are diagrams showing an operation example when reading multi-valued information using the circuit configuration of the first embodiment shown in FIG. 1, wherein FIG. 2A shows a word line waveform diagram, and FIG. FIG. 4B is a diagram showing a threshold voltage distribution of a memory cell and information corresponding to the threshold voltage. Here, a case where the multi-value information is 2 bits per memory cell as shown in FIG. 2B will be described as an example. In this case, the threshold voltage of the memory cell has four possible cases V1 to V4, each of which has a variation. Here, when the information is "10", the threshold voltage is V1, and when the information is "11", the threshold voltage is V2.
In the case of "01", it is V3, and in the case of "00", it is V4. With this setting, the Hamming distance of the information corresponding to the adjacent threshold voltage is 1, so that the error correction circuit configuration due to the variation of the threshold voltage and the retention (change of the threshold value when left unattended) There is a feature that can be easily.

In this embodiment, these four threshold voltages V1 to V4 are read out using a plurality of word line voltages VR1 to VR3 as shown in FIG. First, the word line voltage is set to VR1. This word line voltage VR1 is
As shown in (b), the memory cells whose threshold voltages are V2 to V4 do not turn on. The information of the memory cell turned on by the word line voltage VR1 is "10", and the information of the memory cell not turned on is another value. This content is stored in a buffer on the memory chip or taken out of the memory chip and stored.

Next, the word line voltage is set to VR2. The information of the memory cell turned on by the word line voltage VR2 is "1".
0 ”or“ 11. ”This content is also stored in a buffer on the memory chip or taken out of the memory chip and stored.
And The information of the memory cell turned on by the word line voltage VR3 is “10”, “11”, or “01”,
The memory cells that are not turned on are “00”.

By providing a plurality of word line voltages in this manner, a multi-value storage read operation can be performed. Note that the word line voltages are VR2, V3 starting from VR3.
It may be performed in the order of R1, starting from VR2,
Since the flash memory is nonvolatile, the order can be changed. When two or more bits of information are stored per memory cell, the types of word line voltages are increased.

FIGS. 3 (a) and 3 (b) show an operation example of the circuit configuration of this embodiment shown in FIG. 1 at a timing 1, FIG. 3 (b) shows a timing 2 subsequent to the timing 1, and FIG. This is shown in a timing chart as timing 3 following 2. In FIG. 3, only the word lines W1 and bit lines B1 to B4 and the Y selection signals YS1 and YS2 necessary for the description are provided.
Only shows. The solid lines of the bit lines B1 and B2 indicate the voltage waveform of the bit line on the memory cell side of the sense latch circuit, and the dotted lines indicate the voltage waveform of the reference voltage Vr of the sense latch circuit.

At timing 1 in (a), first, the bit lines B1 and B2 are precharged. Thereafter, the word line W
The voltage of No. 1 is VR1. Thus, for example, a current flows in the memory cell M11 connected to the bit line B1, and the potential of the bit line B1 decreases. On the other hand, bit line B
No current flows in the memory cell M12 connected to No. 2, and the potential of the bit line B2 does not change. Thereafter, this signal is sensed. As a result, a signal having an amplitude about the power supply voltage is obtained on each of the bit lines B1 to Bn. Thereafter, the Y selection signals YS1 and YS2 are sequentially turned on, and the bit lines B1, B
2 is read out. When all the signals have been read, the process proceeds to the next timing 2.

At timing 2 in (b), the word line W1
A similar read operation is performed with the voltage of VR2 as VR2. At this time, a current also flows through the bit line B1 to which the memory cell through which the current flows when reading with the word line voltage VR1 is connected. In this example, it is assumed that a current flows in the memory cell M12 connected to the bit line B2. It is also assumed that no current flows in bit line B3. As described above, the information of the bit line is read by the Y selection signals YS1 and YS2.

At timing 3 in (c), the word line W1
Is VR3. The potential of the bit lines B1 and B2 to which the current has flowed at the voltage VR2 decreases. Further here,
It is assumed that a current starts flowing through the bit line B3. It does not flow to the bit line B4.

With the above operation, the information "10" is read from the memory cell M11 connected to the bit line B1, the information "11" is read from the memory cell M12 connected to the bit line B2, and the bit line B2 is read. Memory cell M connected to B3
13 is read out from the bit line B4.
Is read from the memory cell M14 connected to.

Next, the write / verify operation of this embodiment will be described with reference to FIG. FIG. 9 is an explanatory diagram showing a write / verify operation, and shows a case where two bits are stored in one memory cell (hereinafter abbreviated as a cell). As shown in FIG. 2, each cell has four possible threshold voltage states, and “10”, “11”,
"01" and "00" are made to correspond. In FIG. 9, there is a case where there are four memory cells and 8-bit information is written into them. Assume “00011110” as a data string. Since two bits are stored per cell, for example, "00" is stored in cell 1, "01" is stored in cell 2, "11" is stored in cell 3, and so on.
It is assumed that "10" is written in cell 4. That is, the cell 1 has the highest threshold voltage, the cells 2 and 3 have the lowest threshold voltages, and the cell 4 has the lowest threshold voltage.

First, as shown in FIG.
All four cells are in the erased state. The erased state is the state with the highest threshold voltage, and corresponds to information “00”. In this state, the cell 1 to which "00" is to be written has a desired threshold voltage. The information to be written to cells 2, 3 and 4 corresponds to a lower threshold voltage.

Therefore, first, as shown in (b) Write 1, the write / verify operation is repeated for three cells (cell 2, cell 3, cell 4) aiming at the threshold voltage corresponding to "01". . That is, the word line W is set to a write voltage, for example, -9 V using the write word line voltage generation circuit VWG2.
For example, 0 V is applied to the drain of the cell 1 by a power supply (not shown), and 4 V is applied to the drains of the cells 2, 3, and 4 for example. As a result, although the threshold voltage of the cell 1 does not change much, electrons are emitted from the control gates of the cells 2, 3 and 4 by the tunnel phenomenon, and the threshold voltage decreases. At this time, the word line voltage at the time of verification supplied from the word line voltage generation circuit VWG1 of the present embodiment corresponds to “01” since no current flows in the cell 1 having the threshold voltage corresponding to “00”. In the cells 2 to 4 having the threshold voltage, the voltage at which the current starts to flow. When the writing 1 is completed, the cell 2 has a desired threshold voltage.

Next, as shown in (c) Write 2, the write / verify operation is repeated for the cells 3 and 4 aiming at the threshold voltage corresponding to "11". That is, the word line W is set to a writing voltage, for example, -9 V by using the word line voltage generation circuit VWG2, and 0 V is applied to the drains of the cells 1 and 2 and 4 V is applied to the drains of the cells 3 and 4, for example. Add. Thereby, cell 1 and cell 2
Of the cell 3 and cell 4
Threshold voltage decreases. At this time, the word line voltage at the time of verification supplied from the word line voltage generation circuit VWG1 of the present embodiment has a threshold voltage corresponding to “00” and “01”. In the cells 3 and 4 having the threshold voltage corresponding to “11”, the current starts flowing. This word line voltage is lower than the word line voltage of write 1. When writing 2 is completed, cell 3
Becomes a desired threshold voltage.

Finally, as shown in (d) Write 3,
The write / verify operation is repeated for cell 4 aiming at the threshold voltage corresponding to “10”. For example, 0V is applied to the drains of the cells 1, 2 and 3 by a power source (not shown), and 4V is applied to the drain of the cell 4 and the word line voltage generation circuit VWG2 is used to write the word line W with a voltage for writing, for example. -9V. At this time, the word line voltage at the time of verification supplied from the word line voltage generation circuit VWG1 of this embodiment is the current in the cells 1 to 3 having the threshold voltages corresponding to “00”, “01”, and “11”. Does not flow, and a current starts flowing into the cell 4 having the threshold voltage corresponding to “10”. This word line voltage is even lower than the word line voltage at the time of writing 2. By doing so, the threshold voltage of each cell can be set to a desired value. Note that the word line voltage at the time of verification may use the same value.

As described above, by associating “10”, “11”, “01”, and “00” from the lower one of the threshold voltages shown in FIG. Since the hamming distance between data becomes 1, the circuit configuration for error correction becomes easy. In particular, the threshold voltage Vthi of the flash memory at the time of ultraviolet irradiation is the threshold voltage V4 in FIG. 2, that is, the threshold voltage corresponding to information is the highest, and this is near the voltage at the time of electrically erasing. In such a case, it is preferable to set such a Hamming distance. This is because the charge in the floating gate at the time of Vthi is in a thermal equilibrium state of the memory cell, and when the memory cell is left for a long time, the threshold voltage of the memory cell changes toward Vthi. Therefore, the memory cell having the threshold voltage of V1 in FIG. 2 is most likely to cause the threshold voltage to increase when left unattended, and the memory cell having the threshold voltage of V1 in FIG. Memory cell having a threshold voltage of If the Hamming distance is 1, the circuit configuration for error correction at this time becomes easy. As described above, one feature of the nonvolatile semiconductor multilevel storage device of the present invention is that data is set so that the Hamming distance becomes 1 when Vthi is close to the threshold voltage V4. Of course, conversely, bringing Vthi near the state where the threshold voltage is the lowest is the same idea.

It is to be noted that, from the lower threshold voltage, that is, "11" for the threshold voltage V1, "10" for V2,
When associating "01" with V3 and "00" with V4,
The Hamming distance of the information corresponding to the threshold voltages V2 and V3 is 2. However, this data configuration method divides the threshold voltage into a lower set V1, V2 and a higher set V3, V4,
The upper bits “1” and “0” are made to correspond to this, and in each set, “1” is made to correspond to the lower voltage and “0” to the higher voltage as the lower bits. This is 2 per cell
It is a configuration method that can be easily expanded to more than bits, and data coding and decoding are easy. In this case, the threshold voltage Vthi in the thermal equilibrium state is set between the threshold voltages V2 and V3 where the Hamming distance is 2. In this case, since the voltage difference between Vthi and V2 and the voltage difference between Vthi and V3 are small, it is difficult to change the threshold voltage when left unattended. Therefore, the possibility of erroneous data can be reduced.
The same applies to the case where “1” and “0” are exchanged, and setting Vthi while the hamming distance is long is also a feature of the nonvolatile semiconductor multilevel storage device of the present invention.

As described with reference to FIG. 9, "10", "11", "01", "0"
In the case of writing “0”, “00” corresponds to the erased state. Therefore, the cell 1 storing this is not written. In the writing divided into three times, the cell 2 storing “01” is not. The cell 3 that stores "11" receives one write operation, and the cell 3 that stores "10" receives two write operations, and the cell number 4 which stores "10" receives three write operations. May be performed by a microprocessor or the like separate from the chip of the nonvolatile semiconductor multi-value storage device of the circuit of the present embodiment, or may be provided on the chip of the circuit of the present embodiment.

In the above control device provided on the chip of the circuit of this embodiment or on another chip, if both of the two bits are "0", no writing is performed, and in the first writing, one of the two-bit information is not written. In the case of “1”, a write operation is performed. In the second write, write in the case where the upper bit is “1” is performed. In the third write, the lower bit is inverted, and the inverted result and the upper bit are both “1”. In the case of "", a control device can be realized with a simple logic circuit if a write operation is performed.

This write operation will be described with reference to FIG. First, the data string “00011110” is divided into two bits, “00”, “01”, “11”, and “10”, which are divided into an upper bit “0011” and a lower bit “01”.
10 "for convenience. The original data at this time may include a code for error correction.
Register A for upper bits and register B for lower bits
These data are stored in memory cells, for example, memory cells M11, M12, M13, M14 connected to word line W1.
Is stored in association with. The data in this register is subjected to the simple operation as described above, and the sense latch SL1 is operated.
To SL4. That is, in the first write, any one of the 2-bit information is “1”, so that the data is “0111” in the register A or B,
The second time is when the upper bit is "1", so that the data of the register A is "0011". The third time is when the result of inverting the lower bit and the upper bit are both "1". and B￣ (where the symbol ￣ represents inverse) is data “0001”. By doing so, it is possible to write data in which the Hamming distance is all 1 according to the present invention.

FIG. 11 shows an example of the word line timing at the time of the write / verify operation shown in FIGS.
In the first example of (1), the word line voltage at the time of writing is Vw
And the pulse width is constant. At the time of verification, three types of voltages are required as described with reference to FIG. 9, and Vv1, Vv2, and Vv3 are used in descending order of voltage. That is, after erasing, writing is performed on a word line having a constant pulse width and a voltage of Vw, and it is verified whether or not writing has been performed on a word line voltage of Vv1 in the second state from the higher cell threshold voltage. This writing and verification are repeated until all cells to be written are written. Next, also with a constant pulse width,
The writing with the word line voltage w and the verification with the voltage Vv2, which is lower than the verification voltage Vv1, are repeated. As a result, the desired cell is written to the third state from the higher threshold voltage. Further, writing with a word line voltage of Vw with a constant pulse width and verification with Vv3, which is lower than Vv2, are repeated to write a desired cell to the fourth state. The number of bits per cell is 3
In the case of bits, the same operation is performed for eight threshold voltages including the erased state, and in the case of 4 bits per cell, the same operation is performed for 16 threshold voltages including the erased state.

In the second example of (2), the word line voltage at the time of writing is constant at Vw, but the pulse width is increased as the writing / verification cycle advances. That is, in the writing for performing the verification using the first verification voltage Vv1, the writing / verification cycle is repeated several times with the first pulse width t11, and then the writing / verification cycle is repeated several times with the pulse width t12 larger than t11. . Hereinafter, similarly, the pulse width is increased. By doing so, the number of verification operations can be reduced compared to the case where writing is repeated with a constant pulse width in a memory cell in which the threshold voltage does not easily change, that is, writing is difficult, so that the operation speed is increased. For example, after repeating the write / verify cycle four times with the same pulse width, the pulse width is doubled.
In the writing for performing the verification with the next voltage Vv2, the first pulse width is t21 (in the drawing, the pulse width t21 is smaller than the previous pulse width t12 due to space limitations. ) Is equal to or larger than the last write pulse width at the same time. The same applies to the pulse width t31). In the write operation based on the verification with the verification voltage Vv1, the pulse width is large at the end corresponding to the memory cell that is difficult to write. Therefore, the pulse width t21 of the write word line voltage Vw at the verification voltage Vv2 is What is necessary is just to make it equal to or larger than the last pulse width in the write operation by verification at Vv1. This is because the threshold voltage of the cell in which the writing is performed is difficult to change with a short pulse width. Of course, it is possible to increase the accuracy of the threshold voltage setting by making the length shorter. Thereafter, after a certain repetition of the write / verify cycle, the pulse width is extended to t22, and further, as the write / verify proceeds, the pulse width is extended.

As described above, by gradually increasing the pulse width from a small value each time a different threshold voltage is obtained, the threshold voltage of the cell can be accurately controlled in each writing. Further, the number of times of verification is significantly reduced as compared with the case of a fixed pulse width, so that writing is performed at high speed.

Similarly, a write / verify operation for verifying with the voltage Vv3 is performed. At this time, the initial pulse width of the write word line voltage Vw is t31. The relationship between the pulse width t31 and the final pulse width in the write / verify cycle for verifying with the voltage Vv2 is similar to the above-described method of setting the pulse width t21. FIG. 12 is a flowchart showing the above processing. When the number of bits per cell is 3 bits, the threshold voltage is 8 including the erased state, and when the number of bits per cell is 4 bits, the threshold voltage is 16 including the erased state. The same operation is performed.

In the third example of FIG. 11 (3), the word line at the time of writing is increased while the pulse width is increased from a small value for each of the constant pulse widths or the target threshold voltage as in the second example. The voltage also increases in absolute value as the write / verify cycle progresses. In writing by verification at the voltage Vv1,
The word line voltage starts from Vw11, and in the drawing, the word line voltage is increased in absolute value to Vw12 in the next cycle. Needless to say, the voltage may be changed to the voltage Vw12 after repeating the process a certain number of times while maintaining the voltage of Vw11. By doing so, it is possible to accurately write the threshold voltage even in a cell in which writing is fast or a cell in which writing is slow due to variations in cell characteristics. Further, it is possible to reduce the tunnel current density of a cell in which writing is fast.

Next, in the writing by verification at the voltage Vv2, the word line voltage is started from Vw21, and the word line voltage is changed to Vw22 in the next cycle or after a certain cycle.
Here, the word line voltage Vw21 is a value lower in absolute value than the final word voltage in the write / verify cycle for verifying with the verify voltage Vv1. In the write / verify cycle for verifying with the verify voltage Vv3, the word line voltage starts from Vw31 and changes to the word line voltage Vw32 in the next cycle or after a certain cycle.

In the third example, it is also possible to increase the write pulse width as the write / verify cycle advances as in the second example of FIG. 11B. This is because, for example, when the word line voltage is increased in absolute value, if there is a limit to increase the word line voltage due to a disturb relationship or the like, writing is performed at the maximum word line voltage allowed by this absolute value instead of increasing the absolute value. What is necessary is just to increase a pulse width. FIG. 13 is a flowchart showing the above processing. When the number of bits per cell is 3 bits, the threshold voltage is 8 including the erased state, and when the number of bits per cell is 4 bits, the threshold voltage is 16 including the erased state. The same operation is performed. As described above, in the present embodiment, by performing writing and verification as shown in FIGS. 9 to 13, multi-valued information can be accurately written in one cell.

Hereinafter, referring to FIGS. 14 to 17, the read operation of this embodiment shown in FIG. 2 and the write / read operation shown in FIGS. 9 and 10 will be described.
A plurality of word line voltage generation circuits used in the verification operation will be described. Note that the write word line voltage generation circuit VWG2
Is the same as that of the internal power supply generating circuit disclosed in Japanese Patent Application Laid-Open No. 8-115599, and the description thereof is omitted. FIG. 14 is a circuit diagram showing a configuration example of the word line voltage generation circuit VWG1 at the time of a read or verify operation. In this circuit configuration, the three word line voltages VR1, VR2, VR3 described in FIG. 2 are generated in advance, and these three voltages are applied to the switches SWv1, S3.
Switching between Wv2 and SWv3 is used. In order to generate a voltage for verification, another set of the same voltage may be provided and connected to the output in parallel. Of course, the voltage at the time of reading and the voltage at the time of verification may be the same. In this figure, there are internal power supply voltage circuits VP1, VP2, VP3, and the gates of output transistors M1, M2, M3 are connected to operational amplifier AM based on the outputs of reference voltage generation circuits VG1, VG2, VG3.
1, AM2 and AM3. Internal power supply voltage circuit VP
1, VP2 and VP3 may be a charge pump circuit or a voltage lowering circuit. Also, two or more may be used as one. With this configuration, it is possible to generate an internal power supply voltage required for multi-value reading and verification of the present invention.

FIG. 15 is a circuit diagram showing another example of the structure of word line voltage generation circuit VWG1 at the time of reading or verifying operation. VP is an internal power supply voltage generation circuit, which generates a constant voltage. VG is a plurality of reference voltage generation circuits. The principle of the word line voltage generation circuit VWG1 is that the output transistor M1 is controlled by the operational amplifier AM based on a plurality of voltages from the reference voltage generation circuit VG, and a desired voltage is output from a constant voltage output of the internal power supply voltage generation circuit VP. It will happen. M2 is a MOS transistor for leak current, which is controlled by a control signal φ1. With this configuration, a plurality of word line voltages required for the present embodiment can be generated.

Next, a configuration example of a plurality of reference voltage generation circuits VG is shown in FIGS. In FIG. 16, BGG is a single reference voltage generation circuit, a bandgap generator using a bipolar transistor, and a configuration in which two types of MOS transistors of the same conductivity type having different threshold voltages are formed and the voltage difference is used. Alternatively, there is a configuration in which flash memory cells having different threshold voltages are used and the voltage difference is used. As a bipolar transistor constituting the band gap generator, a parasitic bipolar transistor which can be formed when a CMOS having a triple well structure is formed can be used. Such a bipolar transistor can be easily formed since a triple well structure is indispensable in a method using a negative voltage for a word line. In FIG. 16, the output voltage of such a single reference voltage generation circuit BGG and VG
The voltage generated by dividing the output terminal voltage VR by the variable resistors R11 and R12 is input to the operational amplifier AM1, and the output terminal voltage VR is controlled. By changing the values of the variable resistors R11 and R12, a desired output terminal voltage VR can be generated. The variable resistors R11 and R12 are, for example,
This can be realized by connecting a plurality of switching MOS transistors connected in series having different resistance values and a plurality of resistors having different resistance values in parallel with a set of resistors and turning on which switching MOS transistor. The selection of the switching MOS transistor may be performed depending on the difference between the time of reading and the time of verification, and the difference of the threshold voltage of the cell. As a result, a plurality of word line voltages necessary for the present embodiment can be generated.

FIG. 17 shows another example of the reference voltage generation circuit VG. Unlike the case of FIG. 16, the output of one single reference voltage generation circuit BGG is
Input to M1, AM2 and AM3. Different operational amplifiers use different voltages in different modes (for reading and verification)
Occurs in Taking the operational amplifier AM1 as an example, based on the reference voltage generated by the single reference voltage generation circuit BGG, the switch SR is turned on at the time of reading to generate a voltage for controlling the resistance division of the resistors RR1 and R11, and at the time of verification, SV is turned on to generate a voltage for controlling the resistance division of the resistors RV1 and R11. The same applies to the operational amplifiers AM2 and AM3, and the resistors RR2 and RR3 are used at the time of reading based on the reference voltage generated by the single reference voltage generating circuit BGG.
In verification, a desired voltage is generated using the resistors RV2 and RV3, respectively. The output of each operational amplifier is connected to the output terminal VR of the reference voltage generation circuit VG by switches SW1 to SW
W3 is switched and connected as appropriate.

<Embodiment 2> FIG. 4 is a circuit diagram showing a main part of a second embodiment of the nonvolatile semiconductor multi-value storage device according to the present invention. In this embodiment, two sets of sense latch circuits are provided for each of the bit lines B1 to Bn. Switch SW11
Latch circuits SL11 to SL connected by SWn1 to SWn1
n1 and two sets of sense latch circuits SL12 to SLn2 connected by switches SW12 to SWn2. here,
Based on the sense results of the first set of sense latch circuits SL11 to SLn1, the second set of sense latch circuits SL12 to SL12 to
The operation of SLn2 is made different. That is, the first set of sense latch circuits SL11 to SLn1 operates with a current difference between the dummy cells DM11 to DMn1 having the threshold voltage Vr1 and the memory cells M11 to Mnm, and when the result of the sensing is determined, the second Of sense latch circuits SL12
~ 2 types of dummy cells DM12 to be connected to SLn2 ~
DMn2 (threshold voltage is Vr2), dummy cell DM1
One of three to DMn3 (the threshold voltage is Vr3) is selected for each sense latch.

Specifically, for example, the sense latch circuit SL
11, the node N11 is at a high level and the node N12
Is at a low level and the switch is turned on at a high level, in the sense latch circuit SL12, the switch S
W13 is off and switch SW14 is on.
Therefore, of the two types of dummy cells DM12 and DM13, the dummy cell DM12 is electrically connected to the sense latch circuit SL12. The dummy cell may be formed of a normal MOS transistor as shown in FIG. 4 to obtain a desired threshold value by adjusting the ion implantation concentration of the channel, or may have a structure having a floating gate like a memory cell. May be written so as to have a desired threshold voltage. Alternatively, although the signals Sr1 to Sr3 are signals for controlling the dummy cells, a desired threshold voltage may be set according to the voltage value. For example, this can be realized by preparing dummy cells having a floating gate structure only for the types of threshold voltages, and transmitting the current value to the dummy cells DM11 to DM13 formed of ordinary MOS transistors by a current mirror.

In FIG. 4, YS1 to YSn are switches for connecting the upper input / output line IOU and the lower input / output line IOD and the sense latch in accordance with the Y address information. YS1 to Y shown in 1
(Must be configured with MOS transistors like Sn)
CV is a conversion circuit that outputs binary information to the input / output line IO from information on the upper and lower input / output lines IOU and IOD. Also, W1 to Wm are word lines, and MS1 to Wm.
MSn and MD1 to MDn are switching transistors for selecting a set of m memory cells.
And SS.

The principle by which multi-valued memory cell information can be read out by the circuit of the present embodiment having the above-described structure will be described with reference to FIG.
This will be described with reference to FIG. Now, the dummy cells DM11 to DMn
1 is Vr1, and the dummy cells DM12 to
The threshold voltage of DMn2 is Vr2, and the dummy cell DM13
Let Vr3 be the threshold voltage of .about.DMn3. And 2
In the case of a bit / cell (a four-valued threshold voltage, each of which has a lower central value from V1 to V4), the threshold voltage Vr1 is between the voltages V2 and V3, and the threshold voltage Vr2 is Between the voltages V3 and V4, the threshold voltage Vr3
Is set to be between V1 and V2. The setting of the threshold voltage is performed as described above by adjusting the ion implantation concentration of the channel.

Now, in FIG. 4, a word line, for example, W1
Is selected, and the control signals SD and SS are also selected such that the MOS transistors connected thereto are turned on. Here, the switches SW11 to SWn1 are turned on,
The control signal Sr1 rises and the dummy cells DM11-DM
Turn on n1. Since the threshold voltages of DM11 to DMn1 are Vr1, sense latch circuits SL11 to SL11 are output.
Using SLn1, the threshold voltage of the memory cell is V1,
It is determined whether the set is a set of V2 or a set of V3 and V4. Specifically, among the nodes N11 to Nn1, the high level one is a set of V3 and V4, and the nodes N12 to Nn2
Among them, the one having a high level is a set of V1 and V2. Note that the sense latch circuit SL1
1 to SLn1.

Taking the sense latch circuit SL11 as an example, it is assumed that the node N11 is at a high level and the node N12 is at a low level. Therefore, the threshold voltage of the memory cell is V
3 or V4. Since the node N11 is at a high level, the switch SW14 is turned on, and the switch SW13 is not turned on because the node N12 is at a low level. Next, the switch SW11 is turned off, the switch SW12 is turned on, and the control signals Sr2 and Sr3 are set to a high level to turn on the dummy cells. Since the switch SW14 is ON, the comparison between the dummy cell DM12 and the memory cell is performed by the sense latch circuit SL12. Dummy cell DM
Since the threshold voltage of Twelve is between V3 and V4, it can be determined whether the threshold voltage of the memory cell is V3 or V4. If the node N11 is at a low level and the node N12 is at a high level in the sense latch circuit SL11, the threshold voltage of the memory cell is V1 or V2. In this case, the switch SW13 is on and the switch SW14 is off. Therefore, the dummy cell DM13 whose threshold voltage is Vr3 is used. Since the threshold voltage Vr3 is between V1 and V2, it can be determined which threshold voltage of the memory cell is. The same applies to two sets of sense latch circuits connected to other bit lines.

Thus, two sets of data corresponding to the binary data are stored in the sense latch circuit. This data is converted into binary data by the conversion circuit CV. That is, when one of the Y selection switches YS1 to YSn is opened and the input / output lines IOU and IOD are both at a high level, for example, the threshold voltage of the memory cell becomes V
4 and the information “00” is output to the input / output line IO. If the multi-valued information is 2 bits or more per cell, increase the number of sense latch circuits and dummy cells, or transfer the data outside the array when the upper information is determined, and read the lower information. To go.

The above operation is shown in a timing chart of FIG. In FIG. 6, the precharge operation of the bit lines and the like are omitted. In the sense latch circuit, the node N1
1, N12, Nn1, N13, N23, Nn3 are at high level, and nodes N12, N22, Nn2, N14, N2
4, Nn4 are preset to a low level.

First, the word line W1 and the control signal S
D and SS become high level, the information of the memory cell is read, the switch SW11 and the control signal Sr1 become high level, and the current signal of the memory cell and the current signal of the dummy cell are inputted to the sense latch circuit. Here, the sense latch circuit operates, and in the example of FIG.
Node N11 goes low and the node N12 goes high. In the example shown in FIG. 6, the node N21 remains at the high level, the node N22 remains at the low level, the node Nn1 goes to the low level, and the other sense latch circuits Nn2 in the example shown in FIG. Is at a high level. Switches SW11 to SWn1 are turned off, and sense latch circuits SL11 to SLn1 are disconnected from the bit lines. As a result, information as to which of the two sets of binary values among the possible threshold voltages of the four-valued memory cells is stored in the sense latch circuit.

In response, switches SW13, SW
24 and SWn3 are turned on, and switches SW14 and SW2 are turned on.
3, SWn4 is turned off. As a result, each pair is connected to a dummy cell capable of determining a binary threshold voltage. In the example of FIG. 6, the word line W1 is once dropped. After a bit line precharge operation (not shown) or the like, the word line W1 is turned on again, the switch SW12 is turned on, and the control signals Sr2 and Sr3 are turned on. As a result, the current signal of the memory cell and the current signal of the dummy cell are input to the sense latch circuit SL12. Note that the word line W1 may be kept up without being dropped down. Here, the sense latch circuit operates,
In the sense latch circuit SL12, the node N13 goes low and the node N14 goes high in accordance with the information of the memory cell. In the example shown in FIG. 6, the node N23
Goes low, the node N24 goes high, the node Nn3 remains high, and the node Nn4 remains low. Thereafter, the switches SW12 to SW12
n2 is turned off, and the sense latch circuits SL12 to SLn2 are disconnected from the bit lines. As a result, the information corresponding to the 2-bit data of the memory cell is stored in the two sets of sense latches per bit line. Next, the Y selection switches YS1 to YSn are sequentially activated as shown in FIG. At this time, a binary signal is output to the input / output line IO according to the voltages of the input / output lines IOU and IOD.

As described above with reference to FIGS. 4 to 6, by providing two sets of sense latch circuits, multivalued storage information can be read. Note that the sense latch circuit can be shared by a plurality of bit lines and can be switched and used by a switch.

The write / verify operation may be performed by the method shown in FIGS. 9 to 13 as in the first embodiment.

<Embodiment 3> FIG. 7 is a circuit diagram of a main part showing a third embodiment of the nonvolatile semiconductor multi-value storage device according to the present invention. In FIG. 7, Vr is a reference voltage when the information of the memory cell is amplified by the sense latch circuits SL1 to SLn. As will be described later, this reference voltage Vr is used when the information of the memory cell is binary. MA is a main amplifier circuit, and DB is an output buffer. DD
1 is a multi-level sense circuit for reading multi-level information,
SR1, SR2, and SR3 are switches that are turned on when the multi-level sense circuit DD1 is used, and SS1 is a switch that is turned on when the multi-level sense circuit DD1 is not used.

In this embodiment, the multi-valued information is read out by using the multi-valued sense circuit DD1, but this reading-out method is essentially the same as in the second embodiment. That is, the differential amplifier O
Using P1, the read current of the dummy cell DM1 having the threshold voltage of Vr1 shown in FIG. 5 is compared with the read current of the memory cell, and the possibility of four threshold voltages is first reduced to two. Switch SM2 or dummy cell DM3 connected to dummy cell DM2 using driver SK according to
Switch SM3 connected to the differential amplifier OP
In step 2, either of them is determined. The threshold voltage of the dummy cell DM2 is Vr2 shown in FIG.
The threshold voltage of M3 is Vr3 shown in FIG. Thus, the result of the differential amplifier OP1 and the differential amplifier OP
According to the result of 2, the corresponding binary data is generated in the conversion circuit CV.

The difference from the second embodiment is that, for example, the word line W1 is selected, the Y selection switch YS1 is turned on, and the multi-valued information of only the memory cell M11 connected thereto is read out bit by bit or The point is that eight sets of the multi-valued sense circuit DD1 and the input / output lines IO and the like connected to the multi-valued sense circuit DD1 are provided to perform reading for each byte. In the first and second embodiments,
All or part of the memory cell information selected by one word line is first stored in a buffer such as a sense latch circuit, and then converted into binary data and output. Therefore, it takes 1 microsecond or more to output the first data. The third
In this embodiment, since the conversion is also performed by the multi-valued sense circuit DD1, it is slower than the reading of the binary data.
When the reading speed of the value data is 100 nanoseconds, 4
The reading speed of the value (2-bit) data is about 200 nanoseconds. For this reason, for example, even if the read time of the entire data block is not different from that of the first or second embodiment,
When high-speed reading at the beginning is required by an application, the reading circuit configuration of the present embodiment is effective.

In the circuit configuration of FIG. 7, when the data in the memory cell is binary, the sense latch circuits SL1 to SL1
The circuit can also be used as a circuit for once reading out to SLn and then reading out by burst transfer. That is, as shown in FIG. 8, in the binary mode, burst reading is performed, the switch SS1 is turned on, and the switches SR1 to SR3 are turned off. As a result, for example, the word line W1 is selected, the information of the selected memory cell M11 to Mn1 is stored in the sense latch circuits SL1 to SLn, amplified in order by the main amplifier MA, and output to the output terminal Do by the output buffer DB. And outputs the readout information.

On the other hand, in the multilevel mode, as shown in FIG. 8, random bit or byte reading is performed, and the switch SS1 is turned off. Further, the switches SR2 and SR3 are turned on, the read is performed by the above-described multi-valued sense circuit DD1 using the dummy cell DM1, then the switch SR2 is turned off and the switch SR1 is turned on to turn on the dummy cell DM2.
Alternatively, the aforementioned multi-value reading is performed using DM3. This result is converted into binary data by the conversion circuit CV, amplified by the main amplifier MA, and output the read information to the output terminal Do by the output buffer DB. In FIG. 7, switching to binary burst reading is performed. However, switches SR1 to SR3 and SS1 similar to FIG. 7 are provided on the input / output lines IOU and IOD of the circuit of the second embodiment to perform multi-valued burst reading. By connecting the sense circuit DD1, the method of reading multi-valued information in this embodiment can be switched. In FIG. 7, the control signal line GM is a signal for turning on each of the dummy cells DM1, DM2, DM3,
2, the source of DM3 is connected to the ground voltage VS. Also in this embodiment, the write / verify operation may be performed by the method shown in FIGS. 9 to 13 as in the first embodiment.

Although the preferred embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and various design changes can be made without departing from the spirit of the present invention. It is.

[0073]

As is apparent from the above-described embodiment, in the present invention, a word line voltage generating circuit capable of generating a plurality of voltages used for reading and verifying, or a plurality of dummy cells and a plurality of sense latch circuits for each bit line are provided. With the provision, it is possible to realize reading and writing of multi-value storage in a flash memory in which writing and erasing are performed using Fowler-Nordheim tunnel current. Also,
By setting the Hamming distance of information for adjacent threshold voltages to 1, the configuration of a correction circuit for multi-level data write errors is facilitated.

[Brief description of the drawings]

FIG. 1 is a main part circuit diagram showing a first embodiment of a nonvolatile semiconductor multilevel storage device according to the present invention.

FIGS. 2A and 2B are explanatory diagrams showing a read operation example of the nonvolatile semiconductor multi-level storage device shown in FIG. 1, wherein FIG. 2A is a word line voltage waveform diagram, and FIG. 2B is a memory cell read by the word line voltage; FIG. 4 is a threshold voltage distribution diagram of FIG.

FIG. 3 is a timing chart showing an operation example of the first embodiment.

FIG. 4 is a main part circuit diagram showing a second embodiment of the nonvolatile semiconductor multi-level storage device according to the present invention.

5 is a diagram illustrating the principle of a read operation of the nonvolatile semiconductor multi-level storage device illustrated in FIG. 4, and is a diagram illustrating a threshold voltage of a dummy cell and a threshold voltage distribution of a memory cell;

FIG. 6 is a timing chart showing an operation example of the second embodiment.

FIG. 7 is a main part circuit diagram showing a third embodiment of the nonvolatile semiconductor multilevel storage device according to the present invention.

FIG. 8 illustrates a nonvolatile semiconductor multi-value storage device 2 shown in FIG.
FIG. 9 is a diagram showing one read operation example.

FIG. 9 is a diagram illustrating an example of a write / verify operation of the nonvolatile semiconductor multi-level storage device illustrated in FIG. 1;

FIG. 10 is an explanatory diagram showing a data writing method in which the Hamming distance of the nonvolatile semiconductor multi-level storage device shown in FIG. 1 is set to 1;

11 is a diagram showing word line timing examples at the time of three types of writing / verification of the nonvolatile semiconductor multi-level storage device shown in FIG. 1, wherein (1) is a case where the word line voltage and the writing pulse width are constant; , (2) show the case where the word line voltage is constant and the write pulse width increases, and (3) show the case where the word line voltage increases and the write pulse width is constant.

12 is a diagram showing an example of the flow of the write operation (2) shown in FIG.

13 is a diagram showing an example of the flow of the write operation (3) shown in FIG.

14 is a main part circuit diagram showing an example of a word line voltage generation circuit at the time of a read and verify operation used in the nonvolatile semiconductor multi-level storage device shown in FIG. 1;

FIG. 15 is a main part circuit diagram showing another example of the word line voltage generating circuit at the time of the read and verify operations used in the nonvolatile semiconductor multi-level storage device shown in FIG. 1;

16 is a main part circuit diagram showing an example of a variable reference voltage generation circuit used in the word line voltage generation circuit shown in FIG.

17 is a main part circuit diagram showing another example of the variable reference voltage generation circuit used in the word line voltage generation circuit shown in FIG.

FIG. 18 is a main part circuit diagram showing a conventional example of a nonvolatile semiconductor memory device.

[Explanation of symbols]

CV conversion circuit, M11-Mmn memory cell, MS1-MSn, MD1-MDn selection transistor, W1-Wm word line, B1-Bn bit line, SL1-SLn, SL11-SLn2 sense latch circuit, K1 ... Kn: an information holding and verifying circuit, VWG1, VWG2: a word line voltage generating circuit, VG: a reference voltage generating circuit, DD1: a multi-valued sense circuit, VR1-VR3 ... Multi-level read / verify reference voltage.

Claims (11)

[Claims] 1. A nonvolatile semiconductor multi-level storage device in which a memory cell has a floating gate and a control gate, and charges are taken in and out of the floating gate by using a tunnel phenomenon to store a plurality of bits of information per memory cell. A voltage generating means for generating a plurality of voltages for reading and verifying, a memory cell based on a current value flowing through the memory cell by sequentially applying the plurality of voltages of the voltage generating means to a control gate of the memory cell And a means for determining whether the threshold voltage has reached a desired threshold voltage. 2. A non-volatile semiconductor multi-level storage device in which a memory cell has a floating gate and a control gate, and charges are taken in and out of the floating gate by using a tunnel phenomenon to store a plurality of bits of information per memory cell. A plurality of dummy cells each having a different threshold voltage, and a predetermined voltage is applied to a control gate of the memory cell, and the memory cell reaches a desired threshold voltage based on a current value flowing through the memory cell at this time. Means for judging whether or not there is a failure using the plurality of dummy cells. 3. A non-volatile semiconductor multi-value storage device in which a memory cell has a floating gate and a control gate, and charges are taken in and out of the floating gate by using a tunnel phenomenon to store a plurality of bits of information per memory cell. A memory cell comprising at least a plurality of sense latch circuits provided for each bit line via a switch, and a plurality of dummy cells each having a desired different threshold voltage connected to each sense latch circuit via a switch; A predetermined voltage is applied to the control gate of the memory cell, and based on the current value flowing through the memory cell at this time, whether or not the memory cell has reached a desired threshold voltage is sequentially switched and connected to the sense latch circuit. The plurality of dummy cells are sequentially switched and connected to a latch circuit to make a determination. Nonvolatile semiconductor multilevel memory device, characterized in that form have. 4. A non-volatile semiconductor multi-level storage device in which a memory cell has a floating gate and a control gate, and charges are taken in and out of the floating gate by using a tunnel phenomenon to store a plurality of bits of information per memory cell. A sense latch circuit provided for each bit line for use in a binary read mode, a plurality of dummy cells each having a different threshold voltage, and a plurality of dummy cells each of which compares and determines each threshold voltage of a selected memory cell. And a plurality of switches for switching between the respective sense latch circuits and the multi-valued sense circuit on a data output line. It is configured to switch between multi-value mode of value mode and random reading. Nonvolatile semiconductor multi-value storage device. 5. An operation for applying a write pulse for giving a voltage necessary for taking in and out the electric charge to each memory cell, and thereafter, whether or not the memory cell has reached a desired threshold voltage is transmitted to a control gate of the memory cell. The operation of verifying based on the value of the current flowing through the memory cell at this time by applying a voltage is as follows.
The cycle according to any one of claims 1 to 4, wherein when the write / verify cycle is repeated, the write / verify cycle is advanced a predetermined number of times and the pulse width of the write pulse is increased. Non-volatile semiconductor multi-value storage device. 6. An operation for applying a write pulse for giving a voltage necessary for taking in and out the electric charge to each memory cell, and thereafter, whether or not the memory cell has reached a desired threshold voltage is sent to a control gate of the memory cell. The operation of verifying based on the value of the current flowing through the memory cell at this time by applying a voltage is as follows.
5. The cycle according to claim 1, wherein when the write / verify cycle is repeated, the write / verify cycle is advanced a predetermined number of times and the absolute value of the pulse voltage of the write pulse is increased. 3. The non-volatile semiconductor multi-value storage device according to item 1. 7. A hamming distance between information corresponding to adjacent threshold voltages among a plurality of threshold voltages that can be set in one memory cell corresponding to the plurality of bit information is set to a minimum. The nonvolatile semiconductor multi-value storage device according to claim 1. 8. A method according to claim 8, wherein the plurality of bit information is 2-bit information, and the four threshold voltages that can be set in one memory cell corresponding to the 2-bit information correspond in order from the lowest or the highest. Information "00", "01", "1"
7. The nonvolatile semiconductor multi-value storage device according to claim 1, wherein the nonvolatile semiconductor multi-value storage device is set to "1" or "10". 9. The threshold voltage of a memory cell after irradiation with ultraviolet light is the lowest threshold voltage among the four threshold voltages that can be set, and the threshold voltage adjacent thereto. 9. The non-volatile semiconductor device according to claim 8, wherein the non-volatile semiconductor device is set so as to be located between the maximum voltage of the threshold voltage or the maximum voltage of the highest threshold voltage and the minimum voltage of the adjacent threshold voltage. Multi-value storage device. 10. A threshold when the Hamming distance between information corresponding to adjacent threshold voltages is the largest among the plurality of threshold voltages that can be set in one memory cell corresponding to a plurality of bit information. 7. The nonvolatile semiconductor multilevel storage device according to claim 1, wherein a threshold voltage of the memory cell after the irradiation of the ultraviolet rays is set between the value voltages. 11. A method according to claim 1, wherein the plurality of bit information is 2-bit information, and the four threshold voltages that can be set in one memory cell corresponding to the 2-bit information correspond to the lowest or highest threshold voltage in order. Information "00", "01", "1"
In the case of “0” or “11”, the threshold voltage of the memory cell after ultraviolet irradiation is set between the threshold voltage corresponding to “01” and the threshold voltage corresponding to “10”. The nonvolatile semiconductor multi-value storage device according to claim 1, comprising: