JP4004527B2 - Multi-state EEPROM read / write circuit - Google Patents

Description

This application is a continuation of US Application No. 337,579, filed April 13, 1989.
The present invention relates generally to semiconductor electrically erasable programmable read only memories (EEPROMs), and more particularly to circuit techniques for reading or programming their states.

  EEPROM and electrically programmable read memory (EPROM) are typically used in digital circuits for storing or programming non-volatile storage data. They are erasable and have new data written or “programmed” into the memory cells.

  In the structure of the field effect transistor, one EPROM uses a floating (not connected) conductive gate, and this conductive gate is provided on the channel region of the semiconductor substrate between the source and the drain. Is insulated. The control gate is provided on the floating gate but is insulated from it. The threshold voltage characteristic of the transistor is controlled by the amount of charge held on the floating gate. That is, the minimum voltage (threshold) to be applied to the control gate before the transistor is turned “on” and the source and drain regions are conducting is controlled by the charge level on the floating gate.

  The floating gate can hold a range of charges, thereby programming one EPROM memory cell to a threshold level within any threshold window. The size of the threshold window is determined by the minimum and maximum threshold levels of the device and depends on the device characteristics, operating conditions and history. Each distinct threshold level in the window is in principle used to specify a finite storage state of the cell.

  In EPROM memory, a transistor acting as a memory cell is programmed to one of two states by accelerating electrons from the channel region of the substrate through a thin gate dielectric to a floating gate. This memory state can be erased by removing the charge on the floating gate by irradiation with ultraviolet light.

  An electrically erasable programmable read only memory (EEPROM) has a similar structure, but further includes a mechanism for removing charges by applying an appropriate voltage on the floating. Such an array of EEPROM cells is called a “flash” EEPROM array when the entire array of cells, or a significant area of cells in the array, are simultaneously erased (ie, in a flash state). Once erased, the cell can be reprogrammed.

  One particular cell in a two-dimensional array of EPROMs or EEPROM cells applies a source-drain voltage to the source and drain lines of the column containing the cell to be addressed and contains the cell to be addressed It is addressed for reading by applying a control gate voltage to the word line connected to the control gate in the row (low).

  The state of the transistor in the addressed memory cell is read by applying an operating voltage to its source and drain and its control gate and then detecting the level of current flowing between the source and drain. The current level is proportional to the threshold level of the transistor and is determined by the amount of charge on its floating gate.

  In a normal two-state EEPROM, one breakpoint threshold level is established to divide the threshold window into two regions. The source / drain current is compared to the breakpoint threshold level that was used when the cell was programmed. If the read current is greater than the threshold, the cell is determined to be in the “0” state, and if the current is less than the threshold, the cell is determined to be in another state. Is done. Thus, such a two-state cell stores one bit of digital information. Current sources that would be programmed externally are often used to generate a breakpoint threshold current as part of the memory system.

Thus, in a multi-state EEPROM memory cell, each cell stores two or more bits of data. Thus, the information that can be stored in any EEPROM array increases by a multiple of the state in which each cell can be stored.
US Patent Application No. 204,175 US Patent Application No. 323,779

Accordingly, it is a primary object of the present invention to provide an EEPROM memory cell system in which the cell can store more data than one bit of data.
Yet another object of the present invention is to provide an improved read circuit as part of an EPROM or EEPROM integrated circuit memory chip.
Still another object of the present invention is to provide a readout circuit that is simple and easy to manufacture and has excellent accuracy and reliability for long-term use.
Yet another object of the present invention is to provide an improved program circuit as part of an EPROM or EEPROM integrated circuit chip.
One of the objects of the present invention is to provide a program circuit that is simple and easy to manufacture and has excellent accuracy and reliability for long-term use.
Another object of the present invention is to provide a memory read and program technique that automatically compensates for the effects of temperature, voltage, process variations and charge retention.
Yet another object of the present invention is to provide a flash EEPROM semiconductor chip that can replace a magnetic disk storage device used in a computer system.
It is a further object of the present invention to provide a flash EEPROM structure that can increase the lifetime as measured by the number of program / read cycles that the memory can withstand.

  The above and additional objectives are to provide a multi-level threshold level that allows more than two distinct states in each memory cell to be accurately read and written over the long lifetime of the memory cell. This is accomplished by improving the read / write circuit of the EEPROM array to ensure that more bits are stored in each cell.

  In accordance with one aspect of the invention, the multi-level threshold breakpoint level is provided by a series of memory cells used as master reference cells. The master reference cell is independently and externally programmable by either the memory manufacturer or the user. This feature provides maximum flexibility and allows the breakpoint threshold to be set at any time within the device threshold window. Also, because it is the same device as the memory cell, the reference cell accurately tracks the same variations due to manufacturing processes, operating conditions and device lifetime. The ability to individually program each breakpoint threshold level allows optimization of the threshold window segmentation, which is very important for multi-state execution, and allows fine tuning. Furthermore, it is possible after manufacturing to form either a two-state or multi-state memory from the same device, depending on the current user requirements or device characteristics.

  According to yet another aspect of the present invention, a series of memory cells in each sector (where a sector is a group of memory cells that can be simultaneously erased in a flash EEPROM) is typically used for local reference cells. Is excluded from use as a memory for data storage. Each set of reference cells tracks flash cells in the same sector very closely, both of which are cycled with the same number of program / erase cycles. Thus, aging that occurs in the memory cells of a sector after a significant number of erase / reprogram cycles is also reflected in the local reference cells. Each time a sector of a flash cell is erased and reprogrammed, a series of individual breakpoint threshold levels are reprogrammed into the associated local reference cell. The threshold level read from the local reference cell is automatically adjusted to the change condition of the cell memory of the same sector. The threshold window segmentation is thus maintained optimally. This technique is also beneficial for memories with only one reference cell used to read a two-state (1 bit) memory cell.

  According to another aspect of the present invention, the threshold level rewritten to the local reference cell in each cycle is from a series of master cells that hold externally programmed (or reprogrammed) charges without cycling with the memory cells. can get. One set of master memory cells is sufficient for the entire memory integrated circuit.

  In one embodiment, the read operation directly uses the threshold level of the local reference cell previously copied from the master reference cell. In another embodiment, the read is made to the master reference cell, but the read operation indirectly uses the threshold level of the local reference cell. It is done by first reading the local reference cell for the master reference cell. The detected difference is used to offset the normal memory cell read relative to the master reference cell, so that the biased read is effectively performed relative to the local reference cell.

  According to yet another aspect of the present invention, the read operation of the memory cell is performed by comparing where the memory state is and the current flowing therethrough to a set of reference currents corresponding to a multi-stage threshold breakpoint level. It is determined.

  In one embodiment, the current through the cell being read is compared with each threshold current of the reference cell one by one.

  In another embodiment, the current through the cell being read is compared simultaneously with the current in the series of reference cells. A special current mirror format reproduces the current to be read out in multiple stages without degrading the signal, which is for comparing the threshold currents.

  According to another aspect of the invention, program and verify operations are performed on chunks (ie, multiple bytes) of cells addressed at one time. Further, the verify operation is executed by the circuit of the EEPROM chip. This avoids delays in sending data from the chip in series for verification between each programming step.

  In accordance with another aspect of the invention, if the programmed state is obtained by repeating the steps of programming and verifying from the “erased” state, the circuit may change the programmed state to the intended state after each programming step. And selectively inhibit further programming of the cells of the verified chunk to be correctly programmed. This makes it possible to effectively program data chunks in multi-state execution in parallel.

  According to yet another aspect of the present invention, if the chunks of EEPROM cells are addressed to be erased in parallel, the erased state is obtained by repeated steps of erasing and verifying from the existing state to the erased state. The circuit verifies the erase state with the “erased” state after each erase step and selectively inhibits further erasure of the cells of the verified chunk to be properly erased. As a result, it is possible to prevent excessive erasure that causes stress on the device and to effectively perform parallel erasure of a group of cells.

  According to another aspect of the invention, after a group of cells has been erased to an “erased” state, the cells are reprogrammed to a state adjacent to the “erased” state. This ensures that each erased cell starts from a better defined state and each cell can be subjected to similar program / erase stress.

  According to another aspect of the invention, the voltage supplied to the control gate of the EEPROM cell is variable over a wide range and is independent of the voltage supplied to the read circuit. This allows accurate program / erase merging and use in tests and diagnostics.

  The subject matter here is the development of the EEPROM array readout technology described in US Patent Application No. 204,175, a co-pending patent application filed by Dr. Eliyaho Harari on June 8, 1988. Among them, it relates particularly to the description relating to FIG. U.S. Patent Application No. 204,175 is hereby incorporated by reference and the disclosure relating to that embodiment is most relevant to FIGS. 11, 12, 13 and 15. FIG.

  Additional objects, features and advantages of the present invention will be understood from the following description of preferred embodiments. The description should be made with the accompanying drawings.

  There are many special EPROM and EEPROM semiconductor integrated circuit structures that can be used in making memory arrays in which the various aspects of the invention are suitably implemented.

“Isolated Channel” EEPROM Cell A preferred EEPROM structure is shown generally in FIGS. 1 and 2, which are cross-sectional views of integrated circuits. Briefly describing this preferred structure, the two memory cells 11 and 13 are formed on a thin p-doped substrate 15. A heavily n-doped buried region 17 is between cells 11 and 13 and serves as the drain of cell 11 and the source of cell 13. Similarly, another n-doped buried region 19 is the source of cell 11 and the drain of an adjacent cell, and so on for another n-doped region 21.

  Each memory cell 11 and 13 includes a conductive floating gate 23 and 25, respectively, which is typically made of a polysilicon material. Each of these floating gates is isolated from each other and from another structure of conductive elements by being surrounded by a dielectric material. The control gate 27 extends from both the cell 11 and the cell 13 so as to be insulated from the floating gate and the substrate itself. As shown in FIG. 2, conductive bands 29 and 31 are additionally provided to be insulated from each other and from other structural conductive elements and serve as erase gates. Such a pair of erase gates surrounds the floating gate of each memory cell, and they are separated by an erase dielectric layer. The cells are separated as shown in the cross-sectional view of FIG. 1 as thick field oxidation regions, eg, regions 33, 35, and 37, and as regions 39 and 41 in FIG.

  The memory cell is programmed by moving electrons from the substrate 15 to the floating gate, for example, to the floating gate 25 of the memory cell 13. The charge on the floating gate 25 is increased by moving electrons from the heavily p-doped region 43 across the dielectric to the floating gate. Charge is removed from the floating gate via the dielectric between it and the erase gates 29 and 31. The structure of this preferred EEPROM and its manufacturing process are described in co-pending US Patent Application No. 323,779 (Patent Document 2), Jack H.C. It is described in detail in the application of Ewan and Elijah Harari, filed on March 15, 1989, which is hereby incorporated by reference.

The EEPROM structure shown in FIGS. 1 and 2 is “separate channel” type. Each cell can be viewed as an independent transistor in which two transistors T1 and T2 are connected in series as shown in FIG. The T1 transistor 11a is formed along the channel length L1 of the cell 11 of FIG. It has a variable threshold voltage V _T1 . There is a T2 transistor 11b in series with the T1 transistor 11a, which is formed in the channel L2. This has a fixed threshold voltage V _T2 of about 1V. The elements of the equivalent circuit of FIG. 3 are used by adding a prime (′) to the corresponding reference numbers of FIG. 1 and FIG.

As best understood from the equivalent circuit of FIG. 3, the charge level of the T1 floating gate 23 'of the EEPROM cell affects the threshold voltage V _T1 of the T1 transistor 11a when operating with the control gate 27'. . Thus, several memory states in one cell are defined by the appropriate amount of charge on the floating gate, corresponding to a well defined threshold voltage programmed into the cell. Programming is performed by applying appropriate voltages to drain 17 'and source 19' as well as cell control gate 27 'for a certain amount of time.

Addressable Flash EEPROM Array Various aspects of the present invention are typically applied to arrays of flash EEPROM cells in an integrated circuit chip. FIG. 4 schematically shows an array of individually addressable EEPROM cells 60. Each cell is equivalent to that shown in FIG. 3 and has one control gate, source and drain, and erase gate. A plurality of individual memory cells are made up of rows and columns. Each cell is addressed by selectively energizing its row and column simultaneously. The column 62 includes, for example, a first memory cell 63 and an adjacent second memory cell 65, and so on. The second column 72 includes memory cells 73 and 75, and so on. Cells 63 and 73 are located in row 76, cells 65 and 71 are located in another adjacent row, and so on.

A word line along each row is connected to the control gates of all cells in that row. For example, row 76 has a word line 77 and the next row has a word line 79. The row decoder 81 connects all the control gate voltages V _CG on the input line 83 to the control gates along the selected word line of the row.

Along each column, all cells have a source connected by a source line, such as 91, and a drain connected by a drain line, such as 93. The cells along a row are connected in series by their source and drain, so the drain of one cell is also the source of the adjacent line. Thus, line 93 is the source line of column 72 as well as the drain line of column 62. The column decoder 101 connects the source voltage V _S on the input line 103 to all sources, and connects the drain voltage V _D of the input line 105 to all drains along the selected column.

Each cell is addressed by the row and column in which it is located. For example, if cell 75 is addressed for programming or reading, appropriate programming or reading voltages must be supplied to the cell's control gate, source and drain. One address on the internal address bus 111 is used to decode the row recorder 81 for connecting the V _CG to the word line 79 which is connected to the control gate of the cell 75. The same address is used to decode column decoder 101 for connecting V _S to source line 93 and V _D to drain line 95, which are connected to the source and drain of cell 75, respectively.

One aspect of the present invention described in detail below is the execution of parallel programming and reading of a plurality of memory cells. In order to select a plurality of columns at the same time, the column decoder controls switching between the source multiplexer 107 and the drain multiplexer 109. In this way, the selected columns have their source lines and drain lines connected to V _S and V _D , respectively.

Access to the erase gate of each cell is similar to that of the control gate. In one embodiment, an erase line, such as 113, 115, or 117, is connected to the erase gate of each cell in the row. The erase decoder 119 decodes the address on the internal address bus 111 and selectively connects the erase voltage V _EG on the input line 121 to the erase line. This allows each cell row to be individually addressed and, for example, by applying an appropriate voltage to the erase gate via erase line 113, row 76 can be simultaneously (flashed) erased. In this case, the flash cell consists of one row of memory cells. However, other flash cell embodiments are possible, and in many applications many rows of cells are simultaneously erased at one time.

Flash EEPROM System The addressable EEPROM array 60 shown in FIG. 4 forms part of the large multi-state flash EEPROM system of the present invention shown in FIG. In this large system, the EEPROM integrated circuit chip 130 is controlled by the controller 140 via the interface 150. The controller 140 itself is in communication with the central microprocessor device 160.

  The EEPROM chip 130 consists of an addressable EEPROM array 60, serial protocol logic 170, local power control circuit 180 and various programming and reading circuits 190, 200, 210, 220, 230 and 240.

  The controller 140 controls the function of the EEPROM chip 130 by supplying appropriate voltages and control signals and timing. Tables 1 and 2 show typical examples of voltage conditions for various operating modes of the EEPROM cell. Addressable EEPROM array 60 is powered directly by controller 140 or further regulated on chip by local power control 180, as shown in FIG. Control and data links between the controller 140 and the chip 130 are performed via a serial inline 251 and a serial outline 253. Clock timing is supplied from the controller via line 255.

  In normal operation of the EEPROM chip 130, the controller 140 supplies a serial signal stream to the chip 130 via the serial inline 251. The signals include control, data, address and timing information and are sorted by the serial protocol logic 170. At an appropriate time sequence, logic 170 outputs various control signals 257 to control various circuits on chip 130. It sends an address via the internal address bus 111 to connect the addressed cell to the voltage from the controller. Meanwhile, if the operation is programming, data is sent to and used by a series of read / program latches and shift register 190 via serial data line 259 to program the addressed cell.

In the operation of read circuits and technology EEPROMs using reference cells, it is very important to determine the memory state of the cells accurately and reliably. This is because all basic functions, such as read, erase verify and program verify, depend on it. The improved novel read circuit 220 and technology of the EEPROM chip 130 of the present invention enables a flexible multi-state EEPROM.

As discussed in connection with FIG. 3, the programmed charge on floating gate 23 'determines the programmed threshold voltage V _T1 for that cell. In general, V _T1 increases or decreases according to the amount of negative charge on the floating gate 23 ′. The charge can also be reduced to a positive value (depletion mode) when V _T1 decreases below V _T2 and becomes more negative. The maximum and minimum values of V _T1 are due to the dielectric strength of the device material. The spread of V _T1 defines the threshold voltage window over which the memory state will be formed.

Co-pending US Patent Application No. 204,175 discloses an EEPROM cell having a memory state defined within a maximum window of threshold voltage V _T1 . The total threshold voltage window includes a negative region of the threshold voltage, and further includes a normal positive region. The increased window further increases the memory space forming the multi-state of the EEPROM cell.

  FIGS. 6 and 7 show that the threshold window is divided into a two-state memory and a four-state memory cell, respectively. (Of course, it is possible to divide the window into a three-state memory, or an analog continuous mode window rather than a digital memory.)

First, referring initially to FIG. 6, solid line 343 shows V _T1 as a function of programming time. The threshold voltage window is determined by the minimum and maximum values of V _T1 , the maximum and minimum being defined by each of the erase state level 345 and the fully programmed level 347. Two-state memory is provided by dividing the window into two halves 346 and 348 that use the breakpoint threshold level 349. Thus, if a cell is programmed with V _T1 in each of regions 346 (or regions 348), the memory state is considered to be 0 (or state 1).

A normal erase / program cycle begins with an erase that lowers the cell's threshold voltage to its erase state level 345. Subsequent iterative programming is used to increase the threshold voltage V _T1 to the desired level. Rather than continuously applying a programming voltage to a cell that has been addressed for a period of time corresponding to the condition that the cell is about to be programmed, it applies a short, repeated programming voltage in the read operation that occurs after each pulse, and Is preferably programmed to the desired threshold voltage level and programming is terminated at that time. The connection time between the programming voltage and the pulse is sufficiently fine so that the pulse quickly advances the various regions to the voltage of V _T1 , but each pulse does not go too far in any region. This minimizes the stress applied to the cell in relation to voltage and electric field, thus improving its reliability.

FIG. 7A shows a case of four states, in which the threshold voltage window is divided into four regions 351, 353, 355, and 357 by breakpoint levels 352, 354, and 356, respectively. A cell is assumed to be in state “3”, “2”, “1” or “0” if its V _T1 is programmed to be in the corresponding region 351, 353, 355 or 357, respectively. A 4-state cell can store 2-bit data. Thus, the four states can be encoded into (1,1), (1,0), (0,1) and (0,0), respectively.

  Generally, if each EEPROM cell stores a K state, the threshold window is divided into K regions having a threshold level of at least K-1. Thus, only one breakpoint level requires a two-state memory and three breakpoint levels require a four-state cell.

In principle, the threshold voltage window is divided into a number of memory states. For example, an EEPROM with a threshold window of up to 16V could be divided into 32 at approximately 1 / 2V intervals. Indeed, conventional EEPROM devices only store one bit per two states or cells, and are not reliable and have a short lifetime. Apart from operating with a smaller threshold window, conventional devices fail to solve two other problems specific to EEPROM devices. Both problems are related to the uncertainty in the amount of charge on the floating gate, and hence the uncertainty of the threshold voltage V _T1 programmed into the cell.

The first problem relates to the stress associated with the durability that the device experiences each time it performs an erase / write cycle. The durability of a flash EEPROM device is its resistance to a predetermined number of program / erase cycles. A physical phenomenon that limits the durability of conventional flash EEPROM devices is the capture of electrons in the activated dielectric film of the device. During programming, electrons are injected from the substrate into the floating gate via a dielectric interface. Similarly, during erasure, electrons are drawn from the floating gate to the erase gate via the dielectric interface. In both cases, some electrons are captured by the dielectric interface. The trapped electrons shift the programmed V _T1 to a lower value or the erased V _T1 to a higher value by opposing the applied electric field in subsequent program / erase cycles. It can be seen that this gradually closes the voltage “window” between states “0” and “1” of the conventional device, as shown in FIG. 8A. When the program / erase cycle of about 1 × 10 ⁴ is exceeded, the narrowing of the window causes the read circuit to malfunction. If such a cycle continues, the device will eventually undergo sudden damage due to dielectric damage. This usually occurs during 1 × 10 ⁶ and 1 × 10 ⁷ cycles and is known as the inherent breakdown of the device. In conventional EEPROM devices, the narrowing of the window limits the actual endurance to about 1 × 10 ⁴ program / erase cycles. This problem becomes more important when multi-state memory is implemented because it requires that V _T1 be set more accurately.

The second problem is related to maintaining charge in the floating gate. The charge on the floating gate tends to decrease to some extent due to leakage over a period of time. As a result, the threshold voltage V _T1 is shifted to a lower value as time passes. FIG. 8B illustrates the decrease in V _T1 as a function of time. During the life of the device, V _T1 shifts by about 1V. In a multi-state device, this will shift the memory by one or two states.

  The present invention solves these problems and provides circuitry and techniques for reliably programming and reading various states, even in multi-state embodiments.

The memory state of a cell will be determined by measuring the threshold voltage V _T1 programmed therein. Alternatively, as described in co-pending U.S. Patent Application No. 204,175, the memory states are different conductances of source-drain current I _DS in different states. It may be possible to determine by measuring. As an example of four states, FIG. 7A shows a threshold voltage window segmentation. In contrast, FIG. 7B shows the normal value I _DS (solid line) in four states as a function of the control gate voltage V _CG . In V _CG of 5V, the value I _DS of the four conduction states can be distinguished by detecting in parallel with four corresponding current sensing amplifiers. Associated with each amplifier is a corresponding reference conduction state I _REF level (shown in dashed lines in FIG. 7B). The I _REF level is the same in the corresponding source-drain current window so that the breakpoint threshold level (see FIGS. 6 and 7A) is used to distinguish different regions in the threshold voltage window. Used to do By comparing with I _REF , the conduction state of the memory cell is determined. Co-pending US Patent Application No. 204,175 proposes using the same current sense amplifier and I _REF for both programming and reading. This results in excellent tracking between the reference level (dashed line in FIG. 7B) and the programming level (solid line in FIG. 7B).

In the improved scheme according to the present invention, I _REF is provided by the source-drain currents of a series of EEPROM cells residing on the same chip, which are reserved for this purpose only. Thus, they act as master reference cells with I _REF used as a reference level for reading and programming of all other EEPROM cells on the same chip. By using the same device as the EEPROM cell as a reference cell, excellent tracking of temperature, voltage and manufacturing process variations is achieved. Furthermore, the problem of charge storage that is important in multi-state embodiments is also mitigated.

  Referring to FIG. 9A, a master reference cell 400 is shown with its program and read paths. The reference cell erase and program module 4100 programs or reprograms each such reference cell 400. The module 4100 includes a program and erase circuit 4110 having a program path 4130 that is connected to the drain of the master reference cell 400. Program and erase circuit 4110 is activated by the decoded address from internal bus 111 by each of program decoder 4150 and erase decoder 417. Accordingly, the program voltage or the erase voltage is selectively supplied to each reference cell, for example, the cell 400. In this way, the reference level of each reference cell is set or reprogrammed independently. Typically, the threshold level of each reference cell is programmed in the factory to the optimum level appropriate for each batch in which chips are manufactured. This is done by comparing to an external standard reference level. Under software control, the user is also given the option to reset the reference threshold level.

When the reference threshold voltage V _T1 or the reference drain-source current I _REF is programmed into each reference cell 400, it acts as a reference for reading an addressed memory cell such as cell 420. The reference cell 400 is connected to the first leg 403 of the current sense amplifier 410 via a switch 413 to which a clock is supplied. The second leg 415 of the amplifier is substantially connected to the addressed memory cell 420 and the programmed conduction state of that cell is established. When the cell 420 is read, the control signal READ causes the switch 421 to connect the drain of the cell to the second leg 415. Current sense amplifier 410 supplies a voltage via V _{CC to} the drains of both master reference cell 400 and addressed cell 420. In the preferred embodiment, the amplifier has a current mirror circuit so that the difference in current present in the two legs 403 and 415 causes the voltage on the second leg 415 to increase in the direction of V _CC or V _s . Will go down in the direction. Thus, the second leg node 415 is HIGH (or LOW) when the source-drain current I _DS of the addressed cell 420 is less (or greater) than I _REF through the master reference cell 400, respectively. Become. At an appropriate time controlled by the switch 423 to which the clock is connected, the result detected by the second leg 415 is held by the latch 425 and made available on the output line 427. When I _DS is less than I _REF , HIGH occurs on output line 427 and addressed cell 420 is considered to be in the same conductive state as master reference cell 400.

In the preferred embodiment, a voltage clamp and fast pull-up circuit 430 is inserted between the second leg 415 and the drain 431 of the addressed cell. Circuit 430 serves to maintain drain voltage V _D at a maximum value of 1.5V to 2.0V when it is charged in the case of lower I _DS . Thereby also, V _D is prevented too low in the case of higher I _DS.

  Generally speaking, if each memory cell stores a K state, a reference level of at least K-1, or preferably K, is required. In one embodiment, the addressed cell is compared to K reference cells with k sense amplifiers in parallel. This is preferable in the case of two states from the viewpoint of speed, but the effective current can be expanded even when the number of states is too small. Thus, in the multi-state case, it is preferable to sequentially compare the addressed cells one by one with the K reference cells.

  FIG. 9B shows the multi-state read mode in more detail. K reference cells, for example 431, 433, 435, are connected to the sense amplifier 440 via the first leg 441 of the amplifier. This connection is connected in a time-sharing manner by switches to which clocks are connected, for example, 451, 453, and 455, respectively. The second leg 457 of the sense amplifier is connected to the addressed cell shown in FIG. 9A. The detection signal in the second leg 457 is time-selectively latched in the latches 471, 473, and 475 by switches to which a clock is connected, for example, 461, 463, and 465.

FIG. 9C (1) to FIG. 9C (8) show multi-state read timing. When signal READ is HIGH, switch 421 is enabled and the addressed memory cell is connected to second leg 457 of sense amplifier 440 (FIG. 9C (1)). The clock timing is shown in FIGS. 9C (2) to 9C (4). Thus, at each clock signal, the sense amplifier compares the sequentially addressed cells with each reference cell and latches each result. The latched output of the sense amplifier is shown in FIGS. 9C (5) through 9C (7). After all of the K output states of sense amplifier 440 have been latched, they are encoded into L binary bits by KL decoder 480 (2 ^L ≧ K) (FIG. 9C (8)).

  Thus, the multi-level threshold level is provided by a series of memory cells that act as master reference cells. The master reference cell can be erased and programmed independently from the outside, which can be done either by the manufacturer or the user. This feature provides maximum flexibility and allows the breakpoint thresholds to be set individually in the device threshold window at any time. Because the device is the same device as that of the memory cell, the reference cell follows approximately the same variation from the manufacturing process, operating conditions, and charge retention issues. By optionally programming each threshold level independently, the multi-state memory can be made variable by optimizing and fine-tuning the threshold window segmentation. Furthermore, it is possible to form the same device in the form of a two-state or multi-state memory after manufacture according to the user's needs and the characteristics at that time.

Another aspect of the invention is to provide an improved multi-state sensing method for addressed memory cells. Although described above with respect to multi-state memory sensing, it is preferable to compare the cell conduction current to all reference conduction current levels (threshold levels) simultaneously or in parallel. For example, a four state memory cell has three reference current levels to distinguish at least four states. Parallel detection of the cell state means comparing the cell conduction current I _CELL against each of the three reference current levels. This will be faster than sequentially comparing each of the three reference conduction levels. However, in the simpler embodiment described above, dividing the conduction current of the addressed cell into three branches for comparison of each reference level results in a weakening of the conduction current. Therefore, especially when multiple states are involved, it is prohibited from the standpoint of the need for a signal-to-noise ratio of the detection system.

  FIGS. 9D through 9I illustrate several embodiments that simultaneously perform multi-state detection without the disadvantage of reducing the sensed cell conduction current. In each embodiment, a one-to-many current mirror is used to regenerate the current into multiple copies, and each copy is used to compare simultaneously with the reference current level.

  FIG. 9D shows a first embodiment of the simultaneous multi-state detection method. The one-to-many current mirror includes a first transistor 910 on the first leg 920 and a second transistor 911, 912,... 925 in each branch 921, 922,. ., 915. When a first current flows through the first leg 920, the second transistor in each branch of the second leg acts as a current source and passes the regenerated current through that branch. The ratio of the regenerated current to the first current is determined by the relative size of the second transistors 911, 912,.

In an embodiment of the present invention, all transistors are of the same size, as indicated by the symbol “X” shown in FIG. 9D. This results in a one-to-many current mirror in which the first current of the first leg 920 is reproduced identically in all the second branches 921, 922,. Thus, when the conduction current I _CELL of the addressed memory cell 420 flows through the read enable switch 421 of the first leg 920, the same current I _CELL is supplied to the second leg branches 921, 922,. Played back to 925. This can be realized without weakening I _CELL .

As I _CELL is regenerated to each branch, it is compared to the associated reference current level. This is done by driving each branch with a first current source 911, 912,..., 915 and an in-line second current source 931, 932,. Each of the second current sources or each of the I _REF circuits 931, 932,..., 935 has a predetermined reference current level, for example, I _REF1 in the first branch line 941, I _{REF2 on} line 942..., I _REFK on line 953 of the k th branch is supplied. Thereafter, the memory state is determined by sensing the position of the I _CELL level relative to the I _REF . The detected outputs of the states shown as SA1, SA2,..., SAk in FIG. 9D are the first branch node 951, the second branch node 952,. Node 953. The node of each branch is provided between the first and second current sources. Generally, the two current sources have opposite polarities. If the second current source 931, 932,... 935 is an n-channel transistor connected to V _S at one end, the first current source is a p-channel connected to V _CC at the other end. , 915. Depending on the relative levels of I _CELL and I _REF of the two current sources, each node is either pulled above V _CC (typically 5V) or pulled down to V _s (typically 0V). For example, in the first branch, current I _CELL is regenerated on line 921 and current I _REF1 is supplied on line 941. Each node 951 is HIGH (or LOW) when I _CELL is greater (or less) than I _REF . Thus, the memory state with I _CELL between I _REF1 and I _REF2 can be obtained by keeping the node 951 only HIGH so that the multi-state output (SA1, SA2,..., SAK) = (0,1,. .., 1)

In general, each I _REF circuit 931, 932,..., 935 is a current source circuit that is pre- _tuned to provide various reference current levels I _REF1 and I _{REF2 ,.} There is a case.

FIG. 9E shows one embodiment in an EEPROM application, where each I _REF circuit 931, 932,..., 935 is provided by a respective reference cell 431, 432,. Each reference cell is itself an EEPROM cell similar to that described in connection with FIGS. 9A and 9B. Thus, the reference cell can be applied as a master reference cell or a local reference cell, where the reference conduction current level is programmed.

FIG. 9F shows a preferred embodiment in which the I _REF circuit is not provided directly by the reference cell, but is provided by its regeneration. This allows memory cell chunks (eg, 64) to share the same reference cell for simultaneous detection. Transistors 961, 962,..., 965 in I _REF circuits 931, 932,..., 935, respectively, serve as current sources for the regenerated reference currents from the respective reference cells 431, 432,. Works. Each transistor is controlled by a reference voltage REF1, REF2,..., REFk at its gate to generate the required reference current levels I _REF1, I _{REF2 ,.} Each reference voltage is supplied by a REF circuit 971,. As an alternative, each transistor 961, 962,... 965 and its associated REF circuit 971,..., 975 form a double current mirror circuit, whereby each reference cell 431. , 432,..., 435 are regenerated as conduction currents of the transistors 961, 962,. Considering I _REF1 circuit 931 as an example, it consists of transistor 961 as a current source for I _REF1 . The I _REF1 level is obtained as a regeneration of the conduction current of the reference cell 431. The reference cell 431 supplies a reference current I _REF1 to the first leg 976 of the first current mirror, which is regenerated on its second leg 977. The second leg 977 of the first current mirror is interconnected to the first leg of the second current mirror. Thus, the regenerated reference current is regenerated in the second leg 941 of the second mirror by transistor 961. In general, the two current mirrors are of opposite polarity. For example, if the REF1 cell 431 is an n-channel transistor, the first current mirror is two p-channel transistors 981 and 982 of the same size “X”, and the second current mirror is It consists of two n-channel transistors 983 and 961 of the same size “W”.

FIG. 9G shows yet another embodiment, where all the different I _REF levels supplied by the second current source of each branch are generated by one reference circuit 976. . The reference circuit 976 supplies a reference voltage applied to all the gates of the transistors 961, 962,. As in the embodiment shown in FIG. 9F, the reference voltage acts to turn on the transistor. However, different levels of I _REF at the branch can be obtained by adjusting the size of transistors 961, 962,. For example, as shown in FIG. 9G, the transistors 961, 962, and 965 have sizes of I * W, J * W,..., K * W, respectively, where I: J : ...: K has the same ratio to I _REF1 : I _REF2 : ... I _REFk , respectively. One reference circuit 976 is a constant voltage source or circuit and includes a reference cell similar to the REF circuit 971 of FIG. 9F. This is true in the normal current mirror state where the transistors in each branch, such as MB1 and 961, are biased to the saturation region.

FIG. 9H shows another embodiment, where all the second current sources are common in the branch, but I _CELL corresponds to the slope of the reference level by the first current source. Played to each branch at the rate level you want. This ratio is determined by adjusting the size of each of the second transistors 911, 912,. For example, as shown in FIG. 9H, the second transistors 911, 912,..., 915 have the sizes of I * X, J * X,. Where X is the size of the first transistor 910 in the first leg 920 and I: J:...: K is the same as I _REF1 : I _REF2:. Is the ratio. Therefore, only one REF circuit 976 is used in all branches, and all the transistors 961, 962,... 965 have the same size. One reference circuit 976 may be a constant voltage source or a circuit including a reference cell similar to the REF circuit 971 in FIG. 9F. In one embodiment, the reference circuit 976 is such that each second current source 961, 962,... 965 supplies a current equal to the highest reference current level I _REFk . The order of the outputs from the nodes is reversed for the embodiment shown in FIGS. 9D-9G.

FIG. 9I shows another embodiment of the simultaneous multi-state detection method using a circuit similar to that of FIG. 9G. The difference from FIG. 9G is that the characteristics of the address memory cell and the IREF circuit are interchanged. is there. In other words, in each branch, a second current source, eg 931, 932,... 935, is now supplying the regenerated I _CELL . This is accomplished by an addressed memory cell circuit 977 that supplies a reference voltage MC to all gates of transistors 961, 962,. The circuit 977 is similar to the REF1 circuit 971 of FIG. 9F, except that the REF1 cell 431 is now replaced by the addressed memory cell 420. Similarly, the first current source, for example, 911 and 912, ..., and supplies 915 I _REF1 in turn, I _REF2.., An I _REFk respectively. The various I _REFs are obtained by stepwise regeneration of the current of the IREF0 circuit 978. This ratio is determined by adjusting the size of each second transistor 911, 912, ..., 915 of the one-to-many current mirror. For example, as shown in FIG. 9I, the second transistors 911, 912,..., 915 have the sizes of I * X, J * X,. _Where X is the size of the first transistor 910 of the first leg 920 and a pair I: J:...: K is respectively I _{REF0: IREF1} : I _{REF2 :.} The ratio is the same. In general, the IREF0 circuit 978 may be a current source that supplies a current level of _IREF0 . In one embodiment, the IREF0 circuit is an EEPROM cell that is programmable by reference current level, which is similar to that described in connection with FIGS. 9A and 9B.

  Another important feature of the present invention is that it helps to overcome the durability stress problem. As already explained, the erase, program and read characteristics of each memory cell depend on the accumulated stress that withstands the number of program / erase cycles experienced by the cell. In general, memory cells are exposed to more program / erase cycles than master reference cells. The initial ideal reference level is gradually shifted to cause a read error. The concept that exists in the present invention is that the reference level reflects the same cycle that the memory cell undergoes. This is accomplished by configuring a local reference cell in addition to the master reference cell. The local reference cell is exposed to the same program / erase cycle as the memory cell. Each time the erase operation is finished, the reference level of the master reference cell is re-copied to the corresponding set of local reference cells. The memory cell is then read against the reference level of the local reference cell that closely tracks. In this way, errors in cell characteristics after each program / erase cycle are automatically compensated. Accordingly, the partitioning of the threshold window to be deformed is properly maintained so that the memory state can be read accurately even after many cycles.

  FIG. 10 shows a local cell reference embodiment for a flash EEPROM. In the flash EEPROM array 60 (FIG. 4), each group of memory cells is collectively erased or programmed and called a sector. The term “flash sector” is similar to the term “sector” used in magnetic disk storage devices and is used herein as well. EEPROM arrays are grouped as flash sectors, eg 501, 503 and 505. All memory cells in the flash sector undergo the same cycle, but different flash sectors undergo different cycles. In order to properly track each flash sector, a set of memory cells in each flash sector is reserved for use as a local reference cell. For example, after flash sector 503 is erased, the reference level of master reference cell 507 is reprogrammed to the local reference cell associated with flash sector 503. Until the next erase cycle, the read circuit 513 continuously reads the memory cells in the flash sector 503 with respect to the reprogrammed reference level.

  FIGS. 11 (1) to 11 (7) illustrate an algorithm for reprogramming a sector reference cell. In particular, FIGS. 11 (1) to 11 (3) relate to erasing the local reference cells of a sector to their “erased state”. Thus, in FIG. 11A, the erase voltage pulse is applied to the memory cells of all sectors including the local reference cell. Thereafter, in FIG. 11 (2), all the local reference cells are read out from the master reference cell to verify whether they are all erased in the “erased state”. If one cell is deemed to be not, an erase voltage pulse is further applied to all cells. This process is continued until it is verified that all local reference cells in the sector are in an “erased” state (FIG. 11 (3)).

  FIGS. 11 (4) to 11 (7) relate to programming the local reference cell of the sector. After verifying that all local reference cells in the sector are in an “erased” state, a program voltage pulse is applied to all local reference cells in FIG. 11 (4). Subsequently, in FIG. 11 (5), the local reference cell is read out from the master reference cell, and it is verified whether each of the local reference cells is programmed to the same state as the corresponding master reference cell. If the local reference cells are not verified as such, a program voltage is selectively applied only to them (FIG. 11 (6)). This process is repeated until it is verified that all local reference cells have been programmed to the various breakpoint threshold levels in the threshold window (FIG. 11 (7)).

  When the sector local reference cells are reprogrammed, they are used to erase, program verify or read the sector addressed memory cells either directly or indirectly.

  FIG. 12A shows an embodiment in which local reference cells are used directly to read or program / erase verify a sector's memory cells. Thus, in this operation, the parallel pair of switches 525 is enabled by the READ signal and the sense amplifier 440 reads the sector addressed memory cell 523 to the local reference cell 525 of each sector. During program / erase verify of the local reference cell (as shown in FIG. 11), another parallel pair of switches 527 allows the local reference cell 525 to be read from the master reference cell 529.

  FIG. 12B shows an algorithm for directly using a local reference cell to read or program / erase verify a sector addressed memory cell.

  FIG. 13A shows an embodiment in which a local reference cell is used indirectly to read an addressed memory cell. First, the master reference cell is erased and programmed, respectively, to one of a number of desirable breakpoint thresholds in the threshold window. Using these master reference thresholds, the local reference cells in the sector of erased cells are each programmed to one of the same desired multiple breakpoints. The sector's addressed cells are then programmed (written) with the desired data. Thereafter, the read sequence of the addressed cell of the sector includes the steps shown in FIG. 13A.

First, each local reference cell 525 is read to the corresponding master reference cell 531. This is done by a switch 533 that enables the READ1 signal connecting the local reference cell 525 to the second leg 457 of the sense amplifier 440 and a master reference cell 531 connected to the first leg 441 of the sense amplifier. Here, an auxiliary current source circuit for each master reference cell is used to optimally bias the current flowing through the first leg 441 of the sense amplifier and match the current in the second leg 457. When the bias adjustment operation is complete for all breakpoint threshold levels, the sector's addressed cell is read out against the bias adjusted master reference cell. This is done by a switch 533 that disables the READ1 signal and a switch 535 that enables the READ signal. The advantage of such an approach is that changes due to V _CC , temperature, cycle fatigue or other effects that cause a threshold deviation between the master reference cell and the addressed cell over time are removed before reading, This is because the local reference cell (which tracks the threshold deviation of the addressed cell) is used to effectively readjust the breakpoint threshold of the master reference cell. For example, this scheme allows addressed cells to be programmed when the master reference cell is operated at V _CC = 5.5V and subsequently addressed when the master reference cell is operated at V _CC = 4.5V. The read cell can be read. The one volt difference at V _CC that normally causes a change in the breakpoint threshold value is not using a local reference cell, and the master reference cell is biased to eliminate this change when reading.

FIGS. 13B and 13C show more detailed examples of current bias circuits, eg, 541, 543, 545, for master reference cells 551, 553, 555. Each bias circuit serves as a current shunt for the master reference cell. For example, circuit 541 is powered to the drain of master reference cell 551 via line 561. It modifies the current in line 562 to the sense amplifier (first leg) and is done by the source current from V _CC or the drain current to V _SS . In the former case, the current in line 562 is decreased and vice versa in the latter case. Since a bias is established in the master reference cell 551, the current imbalance of the two legs of the sense amplifier is transmitted off-chip. This is detected by a controller (see FIG. 5), which programs the bias circuit 541 via the internal address bus 111 and subtracts or adds the current on line 562 to balance the local reference cells.

FIG. 13C shows an embodiment of a bias circuit such as the circuit 541. Banks of parallel transistors, eg, 571, 573, 575, are connected to all of their sources to line 561 via their drains V _CC and switches, eg, 581, 583, 585. By selectively enabling the switch, a different number of transistors are used to subtract different amounts of current from line 562. Similarly, the banks of other parallel transistors, eg, 591,593,595, are connected to all of their drains to line 561 via their source V _SS and switches, eg, 601,603,605. Yes. By selectively enabling the switch, different numbers of transistors are used to sum the various amounts of current from line 562. The decoder 609 decodes the address from the internal address bus 111 and selectively enables the switch. The enable signal is accumulated in the latches 611 and 613. In this way, each time a sector is read, the master reference cell is rebiased with respect to the local reference cell and used to read the memory cells of the sector.

  FIGS. 13D (1) to 13D (4) illustrate an alternative embodiment read algorithm. The sector needs to program and verify the local reference cell with respect to the master reference cell in advance (FIG. 13D (1)). Therefore, each master reference cell is read with respect to the local reference cell (FIG. 13D (2)). The master reference cell is biased to equalize the current with respect to the corresponding local reference cell (FIG. 13D (3)). Subsequently, the memory cell of the sector is read out with respect to the biased master reference cell (FIG. 13D (4)).

  The read circuit and operation described above can also be used in programming and erasing memory cells, and in particular in the verify portion of the operation. As described above, programming is performed in small steps that read the programmed state while verifying that the desired state has been achieved. If the program state is verified correctly, the program ends. Similarly, erasure is performed in small steps that read the erase state while verifying that the “erased” state has been achieved. When the “erased” state is verified correctly, the erasure is finished.

  As described above, dividing the threshold window into K regions requires only K-1 breakpoint threshold levels, which allows the memory cell to store the K state. However, according to one aspect of the present invention, in the multi-state case where the threshold window is more finely divided, it is preferable to provide a K threshold level in the K state. The extra threshold level is used to distinguish the “erased” state from the state with the lowest threshold level. This eliminates undue erasure, and therefore, when the “erased” state is achieved, the erasure is terminated and the cell is not overstressed. Prohibiting the erasure of individual cells selectively is not suitable for flash EEPROMs where at least a sector must be erased each time. Suitable for those EEPROM arrays where the memory cells are individually addressed for erasure.

  According to yet another aspect of the present invention, after a memory cell is erased to an “erased” state, the cell is brought to a lowest threshold level state (ground state) proximate to the “erased” state. A few programs are made. This has two advantages. First, the ground state threshold level of all memory cells is limited between the same two breakpoint threshold levels, and is clearly limited and not widespread. This provides a constant starting point for subsequent cell programming. Second, all cells gain some programming so that cells that tend to store ground state do not lose the remaining tracks, eg, for program / erase cycles and endurance history.

On-Chip Program Verification As described above, programming the EEPROM to the desired state is preferably performed in small steps starting from the “erased” state. After each programming step, the cell being programmed is read to verify that the desired state has been achieved. If not, the program and verify are repeated until it is verified as such.

  Referring to the system diagram shown in FIG. 5, the EEPROM chip 130 is under the control of the controller 140. They are connected in series by a serial inline 251 and a serial outline 253. In a conventional EEPROM device, after each program step, the state formed in the cell being programmed is read and sent back to the controller 140 or CPU 160 to verify that it is in the desired state. This scheme has a significant penalty in speed, especially in the case of serial links.

  In the present invention, program verification is used by programming cell chunks (usually several bytes) in parallel and verifying them in parallel and on the chip. The parallel program is executed by a selection program circuit that disables the programming of the cells of the chunk that have already been verified correctly. This feature is essential in multi-state embodiments because some cells reach the desired state sooner than others, and would otherwise exceed the desired state if not stopped. Because. After all cell chunks have been verified correctly, the on-chip logic communicates this fact to the controller, thereby initiating programming of the next cell chunk. In this way, data does not need to go back and forth between the EEPROM chip and the controller between each programming step, and the program verification speed is greatly increased.

FIG. 14 illustrates a path for programming and verifying chunks of n cells in parallel. In the system diagram of FIG. 5, the same reference numerals are used for corresponding modules. The EEPROM array 60 is addressed N cells at a time. For example, N is 64 cells wide. In a 512-byte flash sector composed of 4 columns of 1024 cells, 64 chunks of 64 cells exist. Source multiplexer 107 selectively connects the N source of one addressed cell to source voltage V _S on line 103. Similarly, the drain multiplexer 109 selectively makes the N drain of the chunk accessible via the N channel data path 105. The data path 105 is accessed by a program circuit 210 having a program inhibit function and by a read circuit 220 during read, program verify or erase verify.

  Referring again to the system diagram of FIG. 5, the program is under the control of the controller 140. Data to be programmed into the sector is sent for each chunk. The controller first sends the first chunk of N * L serial data bits to the EEPROM chip 130 along with address, control and timing information. L is the number of binary bits coded for each memory cell. For example, L = 1 is a two-state cell and L = 2 is a four-state cell. Thus, if N = 64 and L = 2, the chunk of data bits will be 128 bits wide. When serial bits are converted to N * L parallel bits, N * L data bits are stored in a latch and shifted to register 190. These data are necessary for program verification together with the read circuit 220, the bit decoder 230, the comparison circuit 220, and the program circuit 210 having a prohibition function.

  The algorithm of the program for the N-cell chunk is best described with reference to both the system diagram of FIG. 5 and FIGS. 15 (1) to 15 (7) showing the algorithm itself. As already described, before programming a sector, all sectors must be erased and all sectors within them must be verified to be in an “erased” state (FIG. 15 (1)). Subsequently, as shown in FIG. 15 (2), the local reference cell of the sector is programmed (FIGS. 11 (1) to 11 (3)). In FIG. 15 (3), N * L-bit parallel data is latched by a latch 190. In FIG. 15 (4), the read circuit 220 accesses the N-channel data path 105 in order to read the state of the N chunk of the cell. The readout algorithm has already been described in connection with FIG. 12B or 13D. Reading N cells generates N * K (K = number of states per cell) output states. These are decoded by the bit decoder 230 into N * L binary bits. In FIG. 15 (5), the N * L read bit is compared with the N * L program data bit from the latch 190 by the comparison circuit 200 for each bit. In FIG. 15 (6), if any read bit cannot be compared with the program data bit, a program voltage pulse is further applied from the program circuit 210 to the cell chunk at the same time. However, the inhibit circuit 210 in the program circuit selectively blocks programming into cells having bits that are correctly verified with the programmed data bits. Thus, only the cells that have not been verified will be programmed each time. In FIG. 15 (7), programming and verification are repeated until all cells are correctly verified.

  FIG. 16 shows an embodiment of the comparison circuit 200 of FIG. 5 in more detail. The circuit 200 includes N cell comparison modules, for example, 701 and 703, and each module includes N cells in a chunk. In each cell comparison module, L read bits (L = number of coded binary bits in each cell) are compared with the corresponding program data bits for each bit. This is done by L XOR gates, eg 711, 713, 715. The outputs of these XOR gates pass through NOR gate 717, producing a "1" at the NOR gate output if all L bits are verified, and a "0" if vice versa. If the control signal VERIFY is true, this result is latched in the latch 721 and the same result as the output of the NOR gate 717 is obtained at the output 725 of the cell comparison module. The comparison circuit 200 performs L-bit comparison in parallel. The output of the N comparison module, for example, 725 and 727, is used by the N channel output line 731 to be supplied to the program circuit 210 having the prohibit function of FIG.

  At the same time, the output of N, eg, 725, 727, passes through AND gate 733 so that its signal output 735 is “1” when all N cells are verified, otherwise it is “0”. Become. Referring again to FIG. 5, one output 735 is used to inform the controller 140 that all N cells in the chunk of data have been verified correctly. The signal on output 735 is sent through serial outline 253 via AND gate 240 during VERIFY operation.

At the time of power supply or at the end of programming / verifying a chunk of data, the outputs of all cell comparison modules, eg, 725, 727, are reset to a “0” “not verified” state. This is accomplished by pulling node 726 down to V _SS (0V) by a line RESET signal 727 to the transistor.

FIG. 17 is a diagram showing the program circuit 210 having the prohibition function of FIG. 5 in more detail. The program circuit 210 includes N programs having prohibited modules such as 801 and 803. As shown in Tables 1 and 2, in order to program an N cell, the voltage of V _PD must be applied to the drain of each N cell and the voltage V _PG must be applied to the control gate. Each program module 801 or the like acts to selectively supply V _PD on line 805 to one of the drains through one of the N-channel data paths 105. Since V _PD is typically about 8 to 9 V, which is higher than V _CC , the latter cannot be used to turn on transistor switch 807. Rather, a higher voltage V _CG (about 12V) is used to enable switch 807. _VCG itself on line 801 is enabled by the AND gate when the program control signal PGM on line 813 is true and the signal on line 731 is "0". Since the signal on line 731 is from the output of cell comparison module 701 shown in FIG. 16, V _PD will be selectively supplied to cells that have not yet been verified. In this way, each time a program pulse is applied, it is supplied only to cells that have not yet reached the desired state. This selective program feature is particularly necessary for parallel program embodiments and on-chip verification in the case of multiple states.

Variable Voltage Control to Control Gate The system diagram of FIG. 5 along with Tables 1 and 2 of FIG. 18 shows how various voltages can be applied to the EEPROM array 60 to perform the basic functions of the EEPROM. In conventional EEPROM devices, the voltage supplied to the control gate V _CG can be one of two voltages, ie, V _CC or a higher programming voltage of about 12V. it can.

According to another aspect of the invention, the voltage V _CG supplied to the control gate is variable individually and continuously over a wide range of voltages. This is provided by V _PG from control 140. In particular, V _CG on line 83 is supplied from V _PG supplied by the controller from line 901. Table 2 shows V _PG assuming different voltages at different functions of the EEPROM.

Various _VCGs are particularly advantageous in program and erase margin schemes. The program margin reads in the program verification is made by a slightly higher V _CG than the standard voltage V _CC. This is suitable for placing the programmed threshold in a state that exceeds the breakpoint threshold level with a slight margin by the program. In the verification of the erase cell is verified by slightly reduced V _CG, put the cell into the "erased" state. Furthermore, a margin can be used to compensate for the charge retention problem described above (FIG. 8).

As described above, a conventional EEPROM is typically used to supply V _CC to V _CG during program or erase verify. In order to provide a margin, it is necessary to raise or lower V _CC itself. If this is done, the read circuit results will be inaccurate because they are driven by V _CC .

In the present invention, various V _CG that is independent of the voltage supplied to the read circuit is more accurate and reliable results.

In addition, a wide range of _VCG is useful during EEPROM testing and diagnosis. I programmed the entire area of the threshold of the cell (up to the maximum value limited by the failure of the bonding of the device) increases continuously the V _CG is to be easily measured by.

Although the embodiments of the present invention described above are preferred embodiments, it should be understood by those skilled in the art that variations are possible. Accordingly, the invention is to be protected within the full scope of the appended claims.

FIG. 2 is a cross-sectional view illustrating an integrated circuit structure of an EEPROM device used to carry out various aspects according to the present invention. It is the figure of the structure cut | disconnected and shown along the line 2-2 of FIG. 3 is an equivalent circuit diagram of one EEPROM cell of the form shown in FIGS. 1 and 2. FIG. 2 shows an addressable array of EEPROM cells. FIG. 2 is a block diagram of an EEPROM system in which various aspects according to the present invention may be implemented. A threshold window partition of an EEPROM cell that stores 1-bit data is shown. The threshold window segmentation of EEPROM cells that store 2-bit data is shown. FIG. 7B illustrates the threshold window segmentation of the source-drain current of the EEPROM cell of FIG. 7A. It is a curve which shows the change and characteristic of normal EEPROM after using for a fixed period. It is a curve which shows the change and characteristic of normal EEPROM after using for a fixed period. Fig. 4 shows a read and program circuit for a master reference cell and an addressed memory cell according to the present invention. 2 shows a multi-state read circuit having a reference cell according to the present invention. 9B shows the timing for multi-state reading of the circuit of FIG. 9B. FIG. 4 illustrates one embodiment of a multi-state read circuit in which the memory state of one address cell is detected simultaneously for a series of reference current levels. FIG. 9D illustrates one embodiment of the IREF circuit shown in FIG. 9D as an EEPROM cell programmed with a reference current. FIG. 9D illustrates the preferred embodiment of FIG. 9D in which each IREF circuit is supplied by a current source that reproduces a reference current programmed into an EEPROM cell. 9D shows another embodiment of the IREF circuit shown in FIG. 9D in which a reference current is supplied to each branch by conduction of a transistor of a predetermined magnitude. Fig. 4 illustrates another embodiment of a multi-state read circuit in which the memory state of one address cell is detected simultaneously for a series of reference current levels. Fig. 4 illustrates another embodiment of a multi-state read circuit in which the memory state of the address cell is detected simultaneously for a series of reference current levels. Fig. 2 shows a special memory structure according to the invention. Fig. 4 shows an algorithm for programming a series of local reference cells according to the invention. Fig. 4 illustrates one embodiment of a read circuit that directly uses a local reference cell. FIG. 12B illustrates a read algorithm for the embodiment of FIG. 12A. Fig. 6 illustrates an alternative embodiment of a read circuit that indirectly uses a local reference cell. FIG. 6 is a programmable circuit diagram for bias reading of a master reference cell according to an alternative embodiment. FIG. 13B is a detailed circuit diagram for the programmable bias circuit of FIG. 13B. FIG. 13B illustrates a read algorithm for the embodiment of FIG. 13A. A path for reading / programming one chunk of cells in parallel is shown. 2 illustrates an on-chip program / verify algorithm according to the present invention. 1 shows a circuit diagram of a comparison circuit according to the invention. It is a circuit diagram of a program circuit having a prohibition function according to the present invention. 2 shows an example of a typical operating voltage of an EEPROM cell according to the present invention.

Explanation of symbols

60 EEPROM array 130 chip (EEPROM)
140 Controller 150 Interface 160 Central microprocessor 170 Serial protocol logic 180 Local power control circuit 190, 200, 210, 220, 230, 240 Program and read circuit

Claims (11)

Electrical of multiple addressable semiconductors in the form of a source, drain, control gate, floating gate that can maintain a programmed charge level when using the memory, and an erase electrode that can remove charge from the floating gate Erasable and programmable memory cell array,
A system (420) for reading or higher of whether certain stomach lower than the programmed threshold state predetermined for the addressed cell (523),
A reference memory cell (525) ;
And reading means (440) for comparing the charge level of the addressed cell in a nonvolatile memory comprising,
At least one master reference cell (400, 531, 551, 553, 555) and a predetermined threshold of the master reference cell substantially match the threshold of the reference memory cell (525) And a means for adjusting (541, 543, 545),
Nonvolatile memory, characterized in that the read means (440) compares the adjusted threshold of the master reference cell (553) with the addressed cell (523) . The non-volatile memory according to claim 1.
The nonvolatile memory, wherein the charge level stored in the one or more master reference cells (400) is changed by a signal from a program module (4100) that receives a signal from an internal address bus (111). The non-volatile memory according to claim 2.
The program module (4100) includes a program and erase circuit (4110) having a program path (4130) connected to the drain of the master reference cell (400), and the program and erase circuit (4110) includes a program decoder (4110). 4150) and an erasure decoder (417) each being activated by a decoded address from the internal bus (111). The non-volatile memory according to claim 1.
Each memory cell stores one of the two possible memory states and is divided into at least two distinct areas according to a predetermined distinct threshold level Sex memory. The non-volatile memory according to claim 1.
The nonvolatile memory according to claim 1, wherein the charge level stored in the memory cell is determined by a threshold conduction current of the memory cell. The non-volatile memory according to claim 1.
The non-volatile memory is a part of a flash EEPROM. In the non-volatile memory (130, 140, 150, 160),
An EEPROM array having a plurality of groups (501, 503, 505, 523) of individually addressable EEPROM memory cells, each group of cells being erasable as a unit;
At least one group of reference memory cells (525) provided as part of each group (523) of memory cells for storing a threshold level of a group corresponding to the predetermined threshold level. )When,
Reading means (440) for reading the addressed cell (523) of the group of cells by comparison with a threshold level of the group;
A master reference cell (531).
The master reference cell (531) has a master threshold level corresponding to the threshold level of at least one master reference cell (551,553,555) and a group for storing the master threshold level. Means for adjusting (541, 543, 545), wherein said read means (440) compares the threshold level of the addressed cell (523) with the adjusted master threshold level. Non-volatile memory. The non-volatile memory according to claim 7.
Non-volatile memory, wherein the set of master reference cells (551, 553, 555) is associated with an EEPROM array for storing a predetermined set of threshold levels. The non-volatile memory according to claim 7.
The non-volatile memory is a part of a flash EEPROM. The non-volatile memory according to claim 7.
Each memory cell stores one of the two possible memory states and is divided into at least two distinct areas according to a predetermined distinct threshold level Sex memory. The non-volatile memory according to claim 7.
Each memory cell stores one of two or more possible memory states and is divided into at least two distinct regions according to a predetermined distinct threshold level. Non-volatile memory.

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