JPH1168565A - Delay-processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a digital data delay-processing circuit, which neither has an amplitude error not needs adjustment by constituting it of an A/D-D/A converters and a digital delay line or the like, which performed time delay of a digital output signal through a clock signal. SOLUTION: A converter 2 has both A/D and D/A conversion functions, and the switching of the conversion functions can be performed by a function switch control signal of a function switch control terminal 3. When a signal that show A/D conversion is applied to the terminal 3, a signal of an analog input 2a converts digital data, and a digital output 2b output it to a digital delay line 4. Also, when a control signal that shows D/A is applied to the terminal 3, digital data is subjected to D/A conversion and are derived from a delay output terminal 5 as a color-difference signal which is delayed from an analog output 2d. Since conversion sensitivity consists of complementary relationship in this circuit, when A/D and D/A conversions are performed in cascade, the same converter can be used and an adjusting means is not needed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a delay processing circuit suitable for use in a 1H delay line used in an L, SECAM system TV receiver.

[0002]

2. Description of the Related Art PAL and SECAM systems in addition to domestic NTSC systems are used in overseas TV broadcasting.
In these methods, the color difference signal demodulated on the receiving side is delayed by one horizontal line (1H) period to remove distortion in the transmission path, or to make color difference information of all scanning lines uniform by line interpolation. ing. As the 1H delay line used in such a receiver, an analog system using a glass delay line, a CCD, and a switched capacitor has been mainstream, but recently, with the digitization of circuits, a digital delay line system has been put into practical use. Have been.

[0003] Most of the TV receivers for overseas use are constituted by analog receiving circuits. As an example of combining such an analog circuit with a digital delay line, JP-A-59-17
No. 1291, "Chrominance Decoder and Manufacturing Method Thereof" has been proposed.

Generally, in a delay processing circuit, there is a problem of a gain difference between an original signal input to an adder and a delayed signal. SEC
This is because, in the case of the AM processing, if the amplitude difference between these two signals is large, it appears as blind horizontal stripe interference on the screen. The allowable value of this gain difference is ± 0.2 in relative gain.
It is said to be less than dB.

In the case of a conventional circuit, the digital delay line handles digital data, so that there is no change in gain. But,
Since the circuit sensitivities of the A / D conversion and the D / A conversion are different from each other, the level of the delay signal finally output from the D / A exceeds ± 0.2 dB and is at least ± 1 d.
It varies by B. Therefore, the level is such that horizontal stripe interference on the screen is detected, and some kind of amplitude adjusting means is required.

[0006]

In the conventional delay processing circuit for handling digital data, an A / D converter and a D / D converter are used.
The difference in the conversion sensitivity of the A-converter is the level at which horizontal stripe interference on the screen is detected, and some kind of amplitude adjusting means is required.

An object of the present invention is to provide a delay processing circuit for handling digital data, which has no amplitude error and requires no adjustment.

[0008]

In order to solve the above-mentioned problems, a delay processing circuit according to the present invention is provided for comparing data converted (A / D) from an analog signal into a digital signal with an input analog signal. A D / A conversion function is also provided by using means for generating a discrete voltage or current, and a digital signal input terminal and an analog signal input terminal for D / A conversion,
An A / D / D / A converter having an analog signal input terminal for / D conversion, a digital signal output terminal, and an A / D-D / A function switching control terminal, and converting the digital output signal by a clock signal A digital delay line for delaying time, connecting the output of the digital delay line to the digital signal input terminal, connecting the delayed signal to the analog signal input terminal, and extracting the delay signal from the analog signal output terminal. It is characterized by the following.

Thus, a converter for A / D converting an analog signal into digital data is provided with a function of performing D / A conversion with the same sensitivity, and A / D and D are converted by a control signal input to a function switching control terminal. / A function can be switched,
A D / A conversion period is set during the A / D conversion period and time division processing is performed, so that the functions of A / D and D / A can be shared by a common converter.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit configuration diagram for explaining a first embodiment of the present invention. A color difference signal demodulated by a color difference signal demodulation circuit (not shown) is input to an analog signal input terminal 1 and is input to an analog input 2a of a converter 2. This converter 2
Has both A / D and D / A conversion functions, and the conversion function can be switched by a function switching control signal to a function switching control terminal 3. A /
When the signal indicating the D conversion is applied, the signal of the analog input 2a is converted into digital data, and the digital output 2b
The signal is output to the digital delay line 4. There are various types of digital delay lines 4, and the digital delay line 4 used here is
Does not depend on the type, the description of the digital delay line is omitted. The digital delay line 4 is defined as having a function of delaying the A / D converted digital data for a period of 1H.

[0011] The output data of the digital delay line 4 is converted by the converter 2
To the digital input 2c. When a control signal indicating D / A is applied to the function switching control terminal 3, the digital data is D / A converted and derived from the delay output terminal 5 as a color difference signal delayed from the analog output 2d. This color difference signal is used for addition processing with the original signal.

The converter 2 has complementary conversion sensitivities A / D and D / D.
Since it has the function of A, there is no change in gain related to conversion. Therefore, the gain difference between the original signal and the delayed signal
It is determined by the roughness of the conversion at the time of / D conversion. For example, ±
In order to fall within the range of 0.2 dB (± 2.3%),
It suffices if the resolution is at least 6 bits (1.6% step).
However, this roughness is a problem that can be improved by setting the same in a conventional system, and is fundamentally different from that caused by an A / D-D / A conversion error. Therefore, if the delay processing circuit as shown in FIG. 1 is used, it can be kept within the range of ± 0.2 dB, and the adjustment of the gain can be eliminated.

A converter 2 suitable for such a delay processing circuit
Will be described with reference to FIG. In the so-called flash type A / D converter, the reference resistor group 2
1 are connected in a ladder shape to divide the reference voltage, and if the converter is an N-bit converter, 2 N powers of divided voltages are output. The divided voltage and the analog signal input to the analog input 22 are compared by 2 N comparators 23, and the output of the comparator 23 is encoded by the encoder 24 to obtain a digital output. Regarding this A / D converter, refer to the reference (CQ Publisher, Transistor Technology S
PECIALNo. 16 PP. 6-7).

At the time of A / D conversion, the reference resistance group 2
Since a reference voltage group based on 1 is prepared, this is referred to as D
By using / A, a D / A converter having exactly the same sensitivity can be created. The addition of the D / A conversion function is realized by the selector 25 and the decoder 26. Selector 2 for reference resistance group 21
5 and selects one of the reference voltage groups according to a control signal from the decoder 26 and outputs it from the selector 25. The decoder 26 receives digital data from a digital input 27 and decodes which selector 25 is turned on by the data.

With this configuration, since the A / D conversion and the D / A conversion can be realized with the physically same reference voltage, the conversion sensitivities become completely complementary, and the reference resistance group of the reference resistance group referred at the time of the A / D conversion can be realized. A voltage exactly the same as the discrete voltage is output from the D / A, and the amplitude difference in A / D-D / A disappears.

The operation of the converter 2 of FIG. 2 will be described with reference to the timing chart of FIG. It is assumed that CK is supplied as a system clock. The digital delay line 4 updates data at the fall of the system clock CK, and the converter 2 samples one pixel in one cycle of the system clock CK. This one cycle is divided into an A / D conversion period and a D / A conversion period and used for function switching control. For example, the Ta period in which the system clock CK is Lo is assigned to D / A conversion, and the Hi period Tb is assigned to A / D conversion operation. In the circuit of FIG. 2, since the circuits for performing A / D and D / A conversion are independent except for the reference voltage generator, both circuits can be kept in operation.

As a practical means, the system clock C
If data from the digital delay line 4 is separately provided and held at the rising timing of K, the output of the D / A for one sample period can be held, and the output of the selector 25 is changed to the falling of the system clock CK. If the means for activating is provided, the timing of analog output can be synchronized with the system clock CK.

In the case of A / D conversion, although not shown in FIG. 2, a sample and hold circuit is provided before the A / D conversion.
It is common to avoid changing the input analog signal during A / D conversion. When a sample and hold circuit is provided, the sample timing may be Ta. The data A / D converted during the Tb period may be taken into a latch or the like at the falling edge of the system clock CK, or may be directly output to a digital delay line. Usually, the flash A / D converter operates at high speed,
A / D directly during Hi / Lo period of system clock CK
Modifications such as shortening the Tb period and lengthening Ta without performing the function switching control of the conversion or the D / A conversion can be performed according to the actual operation speed.

Unlike the converter 2 shown in FIG. 2, A / D conversion and D
A second embodiment of the present invention that can realize switching of A / D-D / A conversion having the same sensitivity even in a circuit in which / A conversion cannot operate in parallel will be described with reference to FIGS.

This embodiment is different from FIG. 1 in that the analog output 2d of the converter 2 shown in FIG. 1 is led to the delay output terminal 5 via the sample hold circuit 6. An analog signal from the analog output 2d of the converter 2 is input to the sample hold circuit 6, and a signal held for one pixel sample period is output. If the conversion sensitivity of the converter 2 is the same in both the A / D and D / A conversion operations, no amplitude error occurs between the converters 2 and there is no need for adjustment.

The converter 2 used in the embodiment of FIG.
Is based on the successive approximation type A / D converter shown in FIG. For the successive approximation type A / D conversion operation,
The PP. 8 to 10 and will be briefly described here.

The successive approximation type A / D converter converts the analog signal input to the analog input 2a and the output signal of the D / A converter 41 into a comparator 42 in a conversion method in which the A / D converter is determined in order from the most significant bit. To compare the voltage. The comparison result is sent to the bit control circuit 43. The bit control circuit 43 determines 1/0 of the bit, and checks the D / A to check the next bit.
Update the value of the transformation.

To make the D / A converter 42 have an A / D function, switches SW1 and SW2 and digital input 2
c, a digital output 2d may be added. Switch SW
1, SW2 may be switched to the contact D side by inputting a function switching control signal from the function switching control terminal 3.

In a state where the switches SW1 and SW2 are switched to the contact D side, the digital data input from the digital input 2c is transferred to the D / A converter 42 via the switch SW2.
And outputs the output of the D / A converter 42 from the switch SW1 to an analog signal output terminal. Since the converter 42 used for the A / D conversion is directly used for the D / A function,
The same conversion gain as at the time of / D conversion can be obtained. However, in this method, D / A is required for A / D conversion at the time of A / D conversion operation, so that it is separated from the D / A conversion function. If the A / D and D / A functions are switched in a time-division manner, no signal can be taken out from the analog signal output terminal at the time of the A / D function. Therefore, the sample / hold circuit 6 samples the output signal at the time of the D / A function. Hold at the time of A / D function. By doing so, the output of the D / A function can be obtained even during the A / D function, and the addition operation can be achieved.

The state of the time division operation will be described with reference to FIG. It is assumed that the system clock is CK and the D / A conversion function is switched to the A / D conversion function during the Lo period and the A / D conversion function is switched during the Hi period as in the description of FIG.

In the Ta period in which the system clock CK is Lo, the switches SW1 and SW2 are turned to the contact D side in the D / A operation, and the data from the digital delay line 4 updated at the fall of the system clock CK is D / A. It is introduced into the converter 41. The output of the D / A is output to the sample and hold circuit 6, and the sample is made active when Ps is Hi.
The hold operation is performed while Ps is Lo.

In the Tb period, A / D operation is performed and the switch SW
1, SW2 is moved to the contact A side. At this time, a pulse having a frequency higher than the system clock CK is required for the bit control circuit 43. For example, when an 8-bit A / D operation is performed, the cycle changes by eight cycles within the Tb period like Pa, as in Pa. You need to give a signal. At the rise of Pa, 1
Judgment is made bit by bit, and the result is output to the digital delay line 4. When data is passed to the digital delay line 4, holding means such as a latch may be provided to align the data output timing with all bits.

In the D / A operation, when Ps rises, the D / A operation has just started, and the D / A output is not stabilized, so that the output of the sample and hold circuit 6 may fluctuate. For this reason, it is actually more stable to slightly delay the rising phase of Ps. In addition, the successive approximation type requires a clock cycle for the number of bits within the Tb period, and therefore operates at a lower speed than the flash type shown in FIG. Therefore, in an actual application, a modification in which the Tb period is made longer and the frequency of Pa is made lower is also possible.

The circuits shown in FIG. 2 and FIG.
4 and a specific example of the converter shown in FIG. 4, and if a D / A function having a conversion gain completely complementary to the conversion gain of the A / D converter is basically added, the same effect can be obtained.

An example in which the present invention is applied to a TV receiver for receiving PAL or SECAM will be described with reference to FIG. FIG. 7 shows Japanese Patent Application Laid-Open No. Sho 59-17 described as prior art.
The A / D converter, the digital delay line, and the D / A converter of the system shown in FIG. 5 of No. 1291 are replaced with the embodiment of FIG. 1 or FIG. 4 of the present invention, which is A / D-D / A. It is shown as a converter 70.

The color difference signals BY and RY demodulated by the preceding-stage chroma demodulation circuit, which are delayed signals input to the input terminals 71 and 72, respectively, are input. This color difference signal BY
And RY are alternately selected and mixed by the switch SW3 and input to the A / D / D / A converter 70, where A / D-
The delayed analog output signal is alternately separated and output to the original color difference signal path by the switch SW4 from the output of the D / A converter 70. The original signal and the delayed signal are added by adders 73 and 74, and an added color difference signal is obtained from output terminals 75 and 76.

At this time, the switching frequency for switching the switches SW3 and SW4 is twice the sampling frequency of one pixel. An A / D-D / A converter 70 via a sample-and-hold circuit 77 for temporarily capturing the delayed signal and A / D converting the analog signal so as not to fluctuate.
And convert at twice the sample frequency. A / D-
The number of memories of the digital delay line 2 in the D / A converter 70 is
Two lines become one. The delayed analog output signal is alternately separated and output to the original color difference signal path by the switch SW4, and the adder 71 and 72 add the original signal and the delayed signal to obtain an added color difference signal.

As described above, when the present invention is applied to a TV receiver, the scale of the adder and the digital delay line does not change, but the number of converters can be one. Not only does the number of elements need not be reduced and the amplitude adjustment is unnecessary, but also the cost can be reduced.

[0034]

As described above, in the circuit according to the present invention, since the conversion sensitivities when A / D and D / A conversion are performed in tandem are complementary, the same converter can be used, and adjustment can be performed. Since no means is required, it is suitable for a 1H delay line of a TV receiver or the like, and can simultaneously improve image quality and reduce costs.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram for explaining a first embodiment of the present invention.

FIG. 2 is a view for explaining a specific example of the converter of FIG. 1;

FIG. 3 is a characteristic diagram used for explaining the operation of FIG. 2;

FIG. 4 is a circuit configuration diagram for explaining a second embodiment of the present invention.

FIG. 5 is a diagram illustrating a specific example of the converter of FIG. 4;

FIG. 6 is a characteristic diagram used for explaining the operation of FIG. 5;

FIG. 7 is a circuit configuration diagram for describing an application example of the present invention.

[Explanation of symbols]

1 input terminal, 2 converter, 2a analog input, 2b
... Digital output, 2c ... Digital input, 2d ... Analog output, 3 ... Function switching control terminal, 4 ... Digital delay line, 5
... delay output terminal, 6 ... sample and hold circuit.

Claims (5)

[Claims] 1. An analog signal is converted to a digital signal (A /
D) D / A using means for generating a discrete voltage or current for comparing the converted data with the input analog signal
A digital signal input terminal and an analog signal input terminal for D / A conversion, an analog signal input terminal and a digital signal output terminal for A / D conversion, and an A / D-D /
An A / D-D / A converter having a function switching control terminal of A; and a digital delay line for time-delaying the digital output signal by a clock signal, wherein an output of the digital delay line is input to the digital signal input. A delay processing circuit connected to a terminal, a delayed signal is connected to the analog signal input terminal, and a delayed signal is extracted from an analog signal output terminal. 2. An A / D-D / A converter comprising: means for dividing a reference voltage by a reference resistor group to generate a reference voltage group; and an analog signal input from the reference voltage group and an analog signal input terminal. A comparator group for comparing input signals; an encoder circuit for encoding digital data from an output of the comparator group; a decoder circuit for decoding a digital input signal input from a digital signal input terminal; and a control signal from the decoder circuit. A selector circuit for inputting the reference voltage group and selecting one reference voltage, wherein an output of the selector circuit is an analog signal output terminal;
2. The delay processing circuit according to claim 1, wherein an output of said encoder is used as a digital signal output terminal. 3. The delay according to claim 1, further comprising a first sample and hold circuit for sampling and holding an analog signal output from the analog signal output terminal, and extracting a delay signal from the sample and hold output. Processing circuit. 4. The A / D-D / A converter, a D / A converter, a comparator circuit for comparing an output of the D / A converter with a signal from an analog signal input terminal, and the comparator circuit. A bit control circuit for determining a bit and controlling the data of the D / A converter based on the output of the first and second circuits; and a first circuit for connecting the output of the D / A converter to one of the comparator circuit and the analog signal output terminal. A switch, a second switch for selecting one of data from a digital signal input terminal and data from the bit control circuit and connecting to the input terminal of the D / A converter, and the first and second switches 4. The delay processing device according to claim 3, further comprising a function switching control terminal for controlling the switches in conjunction with each other, wherein an output of the bit control circuit is used as a digital signal output terminal. Circuit. 5. A method of receiving two color difference signals of BY and RY as delayed signals, inputting the two color difference signals, and selecting and outputting one of the color difference signals by an external control signal. 3, a second sample and hold circuit that samples and holds the output of the third switch circuit, first and second adders for the BY and RY, and an analog output. A fourth switch circuit that inputs a signal and outputs the signal to one of the first and second adders; and an output of the second sample and hold circuit connected to an analog signal input terminal. 4. The delay processing circuit according to claim 1, wherein a signal to be delayed and a signal from the fourth switch circuit are added by a second adder.