JPH1168553A - Sequencer acceleration circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high speed as well as also surely perform state transition of a sequencer main body by providing a sampling circuit or the like, which samples a counter output in a timing that is asynchronous with a counter output timing and outputs a control signal that transits the state of the sequencer main body. SOLUTION: A gray code counter part 1 performs count processing by an input of a trigger signal 'a' and outputs gray code count data 'b' to a sampling circuit 2. The circuit 2 samples the data 'b' from the part 1 by an input a sampling clock 'c' of a timing, that is asynchronous with the signal 'a' and outputs a control signal 'd' to transits the state of a sequencer body. As for the clock 'c' that is used by the circuit 2, a fast clock signal can be used without having to be conscious of the working of a gray code counter in the preceding stage, and fast state transition to a desired state becomes possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a sequencer speed-up circuit suitable for use in a sequencer.

[0002]

2. Description of the Related Art A circuit that changes the internal state one after another by an external input signal is called a state machine. In particular, those that perform a series of defined tasks in this state machine are called sequencers. A counter for state transition is used in the sequencer.

[0003]

The conventional sequencer described above has a problem that when a binary counter is used as a counter for performing state transition, the state transition cannot be performed at high speed. Was. That is, since the counter output of the binary counter is not always equal to the hamming distance “1”, the sampling circuit in the subsequent stage is a value indicating a state where it is not expected to sample a change point of the counter output when the hamming distance is “2” or more. Will be sampled. Therefore, the sampling circuit performs sampling in anticipation of the timing at which the counter output of the binary counter stabilizes, so that the speed of the state transition cannot be increased.

Accordingly, an object of the present invention is to provide a sequencer high-speed circuit capable of performing a state transition of a sequencer main body at high speed and reliably.

[0005]

To achieve this object, a sequencer speed-up circuit according to the present invention comprises a counter having a Hamming distance of 1 in which only one counter output changes at the same time;
A sampling circuit that samples a counter output of the counter at a timing asynchronous with the counter output timing of the counter and outputs a control signal for transitioning a state of the sequencer body.

According to this configuration, the Hamming distance is always 1
By using this counter, the sequencer main body can be shifted to an expected state even when the sampling timing in the sampling circuit is asynchronous with the count output timing of the counter. A gray code counter is suitable as a counter whose Hamming distance is always 1.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. (A) Configuration of Sequencer Speed-Up Circuit FIG. 1 is a block diagram showing the configuration of a sequencer speed-up circuit according to the present invention. In the figure, a gray code counter unit 1 has a gray code counter of a Hamming distance 1 in which only one counter output changes at the same time, performs a counting process in response to an external trigger signal a, and performs gray code counting data b. Is output. Sampling circuit 2
Is obtained by inputting an external sampling clock c.
A gray code count data b output from the gray code counter unit 1 is sampled, and a control signal d for transitioning a state of a sequencer body (not shown) is output.

(B) Operation of the sequencer speed-up circuit The gray code counter 1
Performs a counting process and outputs gray code counting data b to the sampling circuit 2. The sampling circuit 2 samples gray code count data b from the gray code counter unit 1 in response to the input of a sampling clock c at a timing asynchronous with the trigger signal a, and outputs a control signal d for transitioning the state in the sequencer body. Output.

Here, when the sampling clock c coincides with the changing point of the gray code count data b output from the gray code counter unit 1, the data sampled by the sampling circuit 2 before or after the counting by the sampling clock c. Becomes However, no matter which value is sampled, the output of the gray code counter always transitions to the original state or to the state to be transited because the Hamming distance is always 1.

[0010] The value before the count is sampled, and the state shifts to the state to be shifted by the next sampling clock c even when the original state is maintained. Therefore, a high-speed clock signal can be used as the sampling clock c used in the sampling circuit 2 without being conscious of the function of the gray code counter in the preceding stage, thereby enabling a high-speed state transition to an expected state.

When a binary counter is used instead of the gray code counter of the gray code counter unit 1, the count data by the input of the trigger signal a can take a value with a Hamming distance of 1 or more. For example, if the Hamming distance is 2
If the asynchronous sampling clock c is input at the output timing of the binary counter, there is a possibility that a transition to an unexpected state may occur, and the sampling clock c must be input at a timing at which the output data of the binary counter stabilizes. Therefore, high-speed state transition cannot be performed.

As described above, in this embodiment, the gray code counter whose Hamming distance is always 1 is used, so that the sampling clock c used in the sampling circuit 2 functions as the gray code counter of the gray code counter unit 1. A high-speed clock signal can be used without being conscious, thereby enabling a high-speed state transition to an expected state.

[0013]

According to the present invention, the hamming distance of the count data output from the record counter is always 1, so that the sequencer main body does not expect the count data before or after counting. Since there is no transition, a sequencer with high speed and high reliability can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a sequencer speed-up circuit according to the present invention.

[Explanation of symbols]

 1 Gray code counter 2 Sampling circuit

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor ▲ Taka ▼ Hideaki Hashi 5-7-1 Shiba, Minato-ku, Tokyo Inside NEC Corporation

Claims (2)

[Claims] 1. A counter having a Hamming distance of 1 in which only one counter output changes at the same time. A counter output of the counter is sampled at a timing asynchronous with the counter output timing of the counter, and the state of the sequencer main body is changed. And a sampling circuit for outputting a control signal of the sequencer. 2. The sequencer speed-up circuit according to claim 1, wherein said counter is a gray code counter.