JPH1168053A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent generation of punch through or latch up by forming an MOS transistor of second conductivity type channel in a first conductivity type well at a part of a second conductivity type semiconductor layer formed on a first conductivity type semiconductor substrate and an MOS transistor of first conductivity type channel on the outside of the well. SOLUTION: A second conductivity type semiconductor layer 2 is formed on a first conductivity type semiconductor substrate 1 and a first conductivity type well 3 is formed in a partial region of semiconductor layer 2. A drain 4D and a source 4S comprising a second conductivity type diffusion region are formed in the well 3 and an MOS transistor 4 of second conductivity type channel is constituted of the drain 4D, the source 4S, and a gate 4G formed between them. A drain 5D and a source 5S comprising a first conductivity type diffusion region are formed in the semiconductor layer 2 other than the well 3 and an MOS transistor 5 of first conductivity type channel is constituted of the drain 5D, the source 5S, and a gate 5G formed between them.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a CMOS structure and a method for manufacturing the same. More particularly, the present invention relates to a semiconductor device that hardly causes punch-through and latch-up, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as a CMOS structure of a semiconductor device, a structure as shown in FIG. 8 has been known.

In this CMOS structure, an n-type semiconductor substrate 7
A p-type well 72 is formed in one partial region. This p
In the mold well 72, an NMOS transistor 73 including a source 73S, a drain 73D, and a gate 73G is formed. In addition, a part of the p-type well 72 has an NMO
Ap + region 73K for applying a substrate potential to S transistor 73 is formed.

On the other hand, a p-type well 7 of an n-type semiconductor substrate 71
Outside the area 2, a PMOS transistor 74 including a source 74S, a drain 74D, and a gate 74G is formed. In the vicinity of the PMOS transistor 74, PM
An n + region 74K for applying a substrate potential to OS transistor 74 is formed.

[0005]

In such a CMOS structure, a punch-through phenomenon occurs as the driving voltage of the circuit increases.

FIG. 9 is a diagram for explaining this kind of punch-through phenomenon. In FIG. 9, a voltage of about +15 V is applied to the n-type semiconductor substrate 71. A voltage of about −15 V is applied to the p-type well 72 via the p + region 73K. With such a large driving voltage, n
A thick depletion layer 80 is generated at the boundary between the semiconductor substrate 71 and the p-type well 72.

In this state, when a voltage is applied to the drain 73D, a depletion layer immediately below the drain 73D grows and comes into contact with the depletion layer 80. At this time, the punch-through current Ip rapidly flows through the junction of the depletion layer. In order to prevent this kind of punch-through phenomenon, the following two measures (1) and (2) can be considered.

(1) The impurity concentration of the p-type well 72 is increased, and the width of the depletion layer generated in the p-type well 72 is reduced. (2) The diffusion depth Xj of the p-type well 72 is increased, and a sufficient space is provided between the depletion layers.

However, as in the measure (1), p
When the impurity concentration of the mold well 72 is increased, there is an adverse effect that the breakdown voltage of the PN junction in the p-type well 72 decreases. In particular, when the drive voltage is designed to be large, both conditions of "withstand voltage of PN junction" and "prevention of punch-through" are contradictory. Therefore, in some cases, an appropriate design value cannot be found in the measure (1). . Further, in the measure (1), the gate capacitance of the NMOS transistor 73 increases as the impurity concentration of the p-type well 72 increases. Therefore, the countermeasure (1) has a disadvantage that the operation speed of the NMOS transistor 73 is significantly reduced.

On the other hand, in the measure (2), the p-type well 72
Is deepened. Since the p-type well 72 is a low-concentration diffusion layer, a high-temperature and long-time drive-in is required to sufficiently increase the diffusion depth Xj. The table below shows the relationship between the drive-in condition of the p-type well 72 and the punch-through breakdown voltage.

Drive-In Conditions Punch-through Withstand Voltage (1150 ° C., 1200 minutes) 15V (1150 ° C., 3000 minutes) 30V As can be seen from this table, a long drive-in requires a long punch-in withstand voltage. Required. For these reasons, the countermeasure (2) requires the CMO
There is a problem that productivity of the S structure is reduced.

In addition to the punch-through phenomenon described above, the conventional CMOS structure has another problem called a latch-up phenomenon. FIG. 10 illustrates this latch-up phenomenon. In FIG. 10, the parasitic PNPN thyristor occurs along the following path. (Source 74S) → (N-type semiconductor substrate 71) → (P-type well 72) → (Source 73S) The equivalent circuit of this parasitic PNPN thyristor is expressed by two transistors Q1 and Q2 shown in FIG.

Once the transistors Q1 and Q2 enter the ON state due to noise current or the like, the ON state continues. As a result, the source 74S changes to the source 73.
Overcurrent continues to flow toward S, and eventually the element is destroyed.
In order to prevent such a latch-up phenomenon, the following three measures (A) to (C) can be considered.

(A) The impurity resistance of the p-type well 72 is increased to lower the well resistance Rw. Then, the collector current of Q2 flows more to p + region 73K, so that the base current of Q1 decreases accordingly. As a result, the ON state of Q1 is prevented, and the latch-up phenomenon is prevented. (B) If the diffusion depth Xj of the p-type well 72 is increased, Q1
To increase the base width. Then, the current amplification factor β of Q1 decreases, the on-states of Q1 and Q2 are prevented, and the latch-up phenomenon is prevented. (C) The impurity concentration of the n-type semiconductor substrate 71 is increased to lower the substrate resistance Rsub. Then, since the collector current of Q1 is supplied more from n + region 74K, the base current of Q2 decreases accordingly. As a result, the ON state of Q2 is prevented, and the latch-up phenomenon is prevented.

However, the measures (A) and (B) are as follows.
Since the contents are the same as (1) and (2) above,
The same problem as (2) occurs. On the other hand, in the measure (C), since the impurity concentration of the n-type semiconductor substrate 71 is increased,
The depletion layer 80 shown in FIG. 9 becomes thick. As a result, there is a problem that the punch-through phenomenon is likely to occur.

Therefore, an object of the present invention is to provide a semiconductor device having a CMOS structure in which punch-through and latch-up hardly occur. It is another object of the present invention to provide a method for reliably manufacturing the semiconductor device according to the first aspect.

[0017]

According to a first aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate, and a part of the semiconductor layer. , A second conductivity type MOS transistor formed in the well, and a first conductivity type MOS formed outside the well of the semiconductor layer.
It is characterized by having a transistor and a first conductivity type isolation region provided through the semiconductor layer in the thickness direction and separating the two types of MOS transistors.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the first aspect, wherein a semiconductor layer of the second conductivity type is formed on a semiconductor substrate of the first conductivity type by an epitaxial method. Forming a first conductive type impurity in the semiconductor layer to form a “first conductive type well” and a “first conductive type isolation region penetrating the semiconductor layer”; Forming a MOS transistor of the second conductivity type channel, and forming a MOS transistor of the first conductivity type channel in a region of the semiconductor layer separated from the well via the isolation region. I do.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. (Structure of Embodiment) FIG. 1 is a sectional view showing a CMOS structure in a semiconductor device of this embodiment. In FIG. 1, a semiconductor layer 2 of a second conductivity type is formed on a semiconductor substrate 1 of a first conductivity type. A first conductivity type well 3 is formed in a partial region of the semiconductor layer 2.

In the well 3, a drain 4D and a source 4S formed of a diffusion region of the second conductivity type are formed. An insulating film 2z is located between the drain 4D and the source 4S.
, A gate 4G is formed. These drains 4
D, source 4S and gate 4G form MOS transistor 4 of the second conductivity type channel. In the well 3, a diffusion region 4K for applying a substrate potential to the MOS transistor 4 is also formed.

On the other hand, in the semiconductor layer 2 other than the well 3, a drain 5D and a source 5S formed of a diffusion region of the first conductivity type are provided.
Are formed. A gate 5G is formed between the drain 5D and the source 5S via the insulating film 2z. These drain 5D, source 5S and gate 5
G, MOS transistor 5 of the first conductivity type channel
Is configured. Further, near the MOS transistor 5, a diffusion region 5K for applying a substrate potential to the MOS transistor 5 is also formed.

A first conductivity type isolation region 6 is formed so as to separate these two types of MOS transistors 4 and 5. This isolation region 6 is formed penetrating the semiconductor layer 2 in the thickness direction.

Next, a method of manufacturing the above CMOS structure will be described. (Manufacturing Method of Embodiment) FIGS. 2A to 2C are diagrams schematically illustrating a manufacturing method of a CMOS structure in this embodiment.
First, using the epitaxial method and other thin film forming methods,
A semiconductor layer 2 is formed on a semiconductor substrate 1 (FIG. 2A).

An impurity of the first conductivity type is diffused into the semiconductor layer 2 according to an ion implantation method to form a well 3 and an isolation region 6 (FIG. 2B). In particular, in the isolation region 6, ions of the first conductivity type are diffused deeply until they reach the semiconductor substrate 1 through the semiconductor layer 2.

Subsequently, using a known MOS forming technique,
A MOS transistor 4 of the second conductivity type channel is formed in the well 3. The MOS transistor 5 of the first conductivity type channel is also formed in the region of the semiconductor layer 2 separated from the well 3 via the separation region 6 (FIG. 2C). Through these steps, the CMOS structure of the present embodiment is formed.

Next, the effect of preventing punch-through in this embodiment will be described. (Effect of Preventing Punch Through) FIG. 3 is a diagram illustrating the effect of preventing punch through. In the present embodiment, the well 3
A MOS transistor 4 is formed therein. This well 3
Are of the same conductivity type as the semiconductor substrate 1 and are given substantially the same potential. Therefore, no depletion layer is generated between the well 3 and the semiconductor substrate 1.

The semiconductor layer 2 in contact with the well 3 is in a floating state because it is electrically isolated from the surrounding semiconductor layer 2 by the isolation region 6. Therefore, even if the potential of the well 3 rises and falls, the potential difference between the well 3 and the semiconductor layer 2 hardly changes. Therefore, the depletion layer formed at the junction between well 3 and semiconductor layer 2 does not become so thick.

For the above reasons, there is little possibility that the depletion layers will contact each other inside the well 3. Therefore, no special countermeasure against the punch-through phenomenon is required for the well 3.

On the other hand, the substrate potential of MOS transistor 5 is applied to semiconductor layer 2 on which MOS transistor 5 is formed. Therefore, a large driving voltage is applied to the boundary between the semiconductor layer 2 and the semiconductor substrate 1 so that the thick depletion layer 2
a occurs. On the other hand, when a voltage is applied to the drain 5D (or the source 5S) of the MOS transistor 5, the depletion layer 2b grows immediately below the drain 5D (or the source 5S). These two depletion layers 2
The contact between a and 2b causes a punch-through phenomenon.

However, this kind of punch-through phenomenon can be prevented by setting the thickness of the semiconductor layer 2 to be large in advance and widening the interval between the two depletion layers 2a and 2b. In addition, since the semiconductor layer 2 is formed by a film forming method, such a thick film can be easily realized within a normal range of the film thickness setting.

As the thickness of the semiconductor layer 2 is increased, the diffusion depth of the isolation region 6 needs to be increased by that amount. However, the isolation region 6 is a high concentration layer, and the time required for drive-in is much shorter than the case where the diffusion depth of the p-type well 72 (FIG. 8) is increased.
As described above, in the semiconductor device according to the present embodiment, it is possible to reliably prevent the punch-through phenomenon without significantly reducing the productivity.

Next, the effect of preventing latch-up in this embodiment will be described. (Latch-up Prevention Effect) FIG. 4 is a diagram for explaining the latch-up prevention effect. In FIG. 4, for the sake of explanation, the first conductivity type is set to n-type and the second conductivity type is set to p-type, and the polarity of the transistor is displayed.

As shown in FIG. 4, in the semiconductor device of this embodiment, a parasitic PNPN thyristor is generated along the following path. (Source 4S) → (well 3, isolation region 6, semiconductor substrate 1) → (semiconductor layer 2) → (source 5S) The equivalent circuit of this parasitic PNPN thyristor is represented by transistors Q3 and Q4 shown in FIG. .

Here, by lowering the substrate resistance Rsub of the semiconductor substrate 1 or increasing the well resistance Rw of the well 3, the base current of Q4 can be reduced. Thus, by suppressing the base current of Q4 small, the collector current of Q4 (base current of Q3) can be suppressed small. Then, the collector current of Q3 becomes small, and the base current of Q4 is suppressed to be small again. By repeating these series of operations, Q3 and Q3
The parasitic PNPN thyristor made of No. 4 does not easily conduct.

For the reasons described above, in the semiconductor device of the present embodiment, the latch-up phenomenon is reliably and easily prevented by lowering the substrate resistance Rsub of the semiconductor substrate 1 or increasing the well resistance Rw of the well 3. It is possible to do. In particular, when the impurity concentration of the well 3 is reduced to increase the well resistance Rw, a secondary effect can be obtained.

That is, the breakdown voltage of the PN junction in the well 3 can be increased by lowering the impurity concentration of the well 3. Also, by lowering the impurity concentration of the well 3, the gate capacitance of the MOS transistor 4 is reduced, and M
The operating speed of the OS transistor 4 can be increased.

As described above, the semiconductor device of the present embodiment has a particularly preferable structure for preventing both the punch-through phenomenon and the latch-up phenomenon.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present applicant has filed an application for a solid-state imaging device in Japanese Patent Application No. 9-16399. In this specification, a solid-state imaging device equipped with a CMOS drive circuit is described as an embodiment of the invention.

Hereinafter, a case in which the CMOS structure of the present invention is mounted on this type of solid-state imaging device will be described. FIG. 5 is a partial cross-sectional view of the solid-state imaging device. In FIG. 5, a p-type semiconductor layer 12 is formed on an upper surface of an n-type semiconductor substrate 11.
Is formed. The inside of the p-type semiconductor layer 12 is partitioned by an n-type isolation region 13 reaching the n-type semiconductor substrate 11,
It is divided into a plurality of areas.

Each of these areas includes a PMOS transistor 20, an NMOS transistor 21, an image area 3
0 and the like are respectively formed. In the region where the PMOS transistor 20 is formed, the p-type semiconductor layer 12 has n
A mold well 20w is formed. Inside the n-type well 20w, a drain 20D and a source 20S, which are p + -type diffusion regions, are formed. Impurity ions are implanted into a channel region between the drain 20D and the source 20S, and the threshold voltage Vth of the PMOS transistor 20 is increased.
Is appropriately adjusted. A gate 20 made of polysilicon is formed on this channel region via an Si oxide film 15.
G is formed. Also, the PMO is provided in the n-type well 20w.
An n + type diffusion region 20K for applying a substrate potential to S transistor 20 is also provided.

In a region where the NMOS transistor 21 is formed, a drain 21D and a source 21S, which are n + type diffusion regions, are formed in a part of the p-type semiconductor layer 12. Impurity ions are implanted into a channel region between the drain 21D and the source 21S, and the threshold voltage Vth of the NMOS transistor 21 is appropriately adjusted. On this channel region, a gate 21G made of polysilicon is formed via an Si oxide film 15. Also,
The p-type semiconductor layer 12 is also provided with ap + -type diffusion region 21K for applying a substrate potential to the NMOS transistor 21.

On the other hand, a buried photodiode is formed in a part of the p-type semiconductor layer 12 in a region where the image area 30 is formed. That is, the photoelectric conversion p-type layer 31 and the photoelectric conversion type n-type layer 32 are formed in two layers. The junction between the photoelectric conversion type n-type layer 32 and the p-type semiconductor layer 12 forms a photodiode. Therefore, the signal charges induced by the irradiation light are converted into the photoelectric conversion type n in a floating state.
It is accumulated in the mold layer 32.

A long n-type CCD diffusion layer 33 is provided next to the photoelectric conversion type n-type layer 32. Impurity ions are implanted into the channel region 34 between the photoelectric conversion type n-type layer 32 and the n-type CCD diffusion layer 33, and the threshold voltage Vth at the time of reading out signal charges is appropriately adjusted. Such n
On the type CCD diffusion layer 33 and the channel region 34,
A transfer gate 35 made of polysilicon is formed via the silicon oxide film 15.

The semiconductor substrate 1 corresponds to the n-type semiconductor substrate 11, the semiconductor layer 2 corresponds to the p-type semiconductor layer 12, and the well corresponds to the embodiment of the present invention. 3 corresponds to the n-type well 20w, MOS transistor 4 corresponds to the PMOS transistor 20, and
S transistor 5 corresponds to NMOS transistor 21, and isolation region 6 corresponds to n-type isolation region 13.

Next, the manufacturing method of this embodiment will be described. 6 and 7 are diagrams illustrating the manufacturing method of the example. In the drawings, steps such as a known photolithography process are omitted. First, as shown in FIG. 6A, a p-type semiconductor layer 12 of about 10 μm is grown on the upper surface of an n-type semiconductor substrate 11 by using an epitaxial method. The impurity concentration of the p-type semiconductor layer 12 is (2 × 10
It is set to ¹⁵ cm ^-3 ).

On the surface of this p-type semiconductor layer 12, an Si oxide film 15 for protecting the surface from ion implantation is formed. Next, ions are implanted in a state where a photoresist is selectively applied to the surface of the p-type semiconductor layer 12, and impurities serving as sources of the n-type isolation region 13 and the n-type well 20 w are respectively added to the p-type semiconductor layer 12. Drive in.

At this time, if necessary, ions may be implanted into other p-type semiconductor layers 12 to adjust the impurity concentration of the p-type semiconductor layers 12. In this state, drive-in is performed under conditions of (1150 ° C., 1200 minutes) in order to perform an annealing process. Through such a drive-in process, the diffusion depth of the n-type isolation region 13 reaches the n-type semiconductor substrate 11, as shown in FIG. At the same time, in this drive-in step, the n-type well 20w is also completed.

Next, using a known selective oxidation method, the oxidized S
The i-film 15 is partially thickened to form the element isolation region 15a. Thereafter, drive-in is performed by implanting n-type ions to form an n-type CCD diffusion layer 33, as shown in FIG. 6c. Further, the PMOS transistor 20 and the NMO
Ion implantation is performed on the S transistor 21 and the channel region of the image area 30 to adjust the threshold voltage Vth.

Next, the oxidation S of the active region 40 shown in FIG.
After the i-film 15 is once removed by etching, a new clean thin oxide silicon film 15 is formed by using an oxidation method. The gate 21G, the gate 20G, and the transfer gate 35 are formed on the new Si oxide film 15 by using the CVD method. Then, the drain 20D and the source 2
Ions of the OSS and the p + type diffusion region 21K are selectively ion-implanted. In addition, an impurity serving as a source of the drain 21D, the source 21S, and the n + type diffusion region 20K is selectively ion-implanted.

At this point, an annealing process is performed on the whole, so that the PMOS transistor 20 shown in FIG.
And the NMOS transistor 21 is completed. Next, the image area 30 is annealed by ion-implanting an impurity that is a source of the photoelectric conversion type n-type layer 32 to form the photoelectric conversion type n-type layer 32. Further, the photoelectric conversion type n
The mold layer 32 is ion-implanted with an impurity serving as a source of the p-type layer 31 for photoelectric conversion, and annealed to form the p-type layer 31 for photoelectric conversion.

By the steps described above, a structure as shown in FIG. 7F is obtained. In addition, about the subsequent process,
After an interlayer insulating film is formed by a CVD method (planarization step), a hole such as a contact hole or a via hole is formed to perform an AL wiring (wiring step). Further, after a passivation film is formed on the surface, holes are formed in the bonding pads to complete the process.

Next, the effect of the present embodiment will be described. In this embodiment, the impurity concentration of the p-type semiconductor layer 12 is set to (2 × 1
0 ¹⁵ cm ⁻³ ), and the film thickness is 10 μm. With such a setting, a punch-through withstand voltage of 30 V could be easily secured. At this time, the drive-in time of the n-type isolation region 13 is 1200 minutes. Therefore, the drive time can be significantly reduced as compared with the drive-in time (3000 minutes) of the p-type well 72 in the conventional example (FIG. 8).

Furthermore, in the present embodiment, by increasing the impurity concentration of the n-type semiconductor substrate 11, the latch-up phenomenon is very unlikely to occur. With the effects described above, even in a semiconductor device having a large driving voltage (for example, a solid-state imaging device), it is possible to reliably and easily prevent a punch-through phenomenon and a latch-up phenomenon in a CMOS portion.

In the above-described embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the present invention is not limited to this. The first conductivity type may be p-type and the second conductivity type may be n-type.

In the above-described embodiment, the n-type isolation region 13 and the n-type well 20w are in contact with each other, but the present invention is not limited to this. If the configuration is such that a potential is independently applied to the n-type well 20w, the n-type isolation region 13 and the n-type well 20w may be separated. Further, in the above-described embodiment, the n-type isolation region 13 is formed by the ion implantation method. However, the present invention is not limited to this. Since the n-type isolation region 13 is a high concentration diffusion layer, it can be formed by, for example, a diffusion method.

In the above embodiment, a one-well type CMOS structure is formed, but the present invention is not limited to this. For example, a p-type well may be formed by implanting p-type ions in advance into a region where the NMOS transistor 21 is to be formed. With such a structure, it is possible to obtain the effects of the double well type CMOS structure.

[0057]

As described above, according to the first aspect of the present invention, the punch-through breakdown voltage can be reliably increased by increasing the thickness of the semiconductor layer. In addition, such an increase in the film thickness can be easily realized by setting the film thickness at the time of film formation without requiring any special processing technique.

Therefore, in the semiconductor device of the first aspect,
It is possible to reliably and easily increase the punch-through withstand voltage without significantly reducing the productivity. Claim 1
In the semiconductor device, the substrate resistance of the semiconductor substrate is reduced or
Alternatively, the latch-up phenomenon can be reliably prevented by increasing the well resistance of the well.

In particular, when the impurity concentration in the well is reduced to increase the well resistance, a secondary effect can be obtained. That is, the breakdown voltage of the PN junction in the well can be increased by lowering the impurity concentration of the well.

Further, by lowering the impurity concentration of the well, the gate capacitance of the MOS transistor in the well is reduced, and the operating speed of the MOS transistor can be increased. For the reasons described above, the semiconductor device of claim 1 has a particularly preferable structure for preventing both the punch-through phenomenon and the latch-up phenomenon.

According to the second aspect of the present invention, the semiconductor layer is formed by an epitaxial method. Therefore, a thick semiconductor layer can be accurately formed without defects.
Therefore, the possibility that a punch-through phenomenon occurs in a thin portion of the semiconductor layer by chance is reduced, and the reliability of the semiconductor device can be further improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a CMOS structure in a semiconductor device according to an embodiment.

FIG. 2 is a diagram illustrating a method for manufacturing a semiconductor device according to the embodiment.

FIG. 3 is a diagram illustrating an effect of preventing punch-through.

FIG. 4 is a diagram illustrating an effect of preventing latch-up.

FIG. 5 is a partial cross-sectional view of the solid-state imaging device.

FIG. 6 is a diagram illustrating a manufacturing method according to an example.

FIG. 7 is a diagram illustrating a manufacturing method according to an example.

FIG. 8 is a diagram illustrating a conventional CMOS structure.

FIG. 9 is a diagram illustrating a punch-through phenomenon.

FIG. 10 is a diagram illustrating a latch-up phenomenon.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 semiconductor layer 2a depletion layer 2b depletion layer 2z insulating film 3 well 4 MOS transistor of second conductivity type channel 4D drain 4G gate 4K diffusion region 4S source 5 MOS transistor of first conductivity type channel 5D drain 5G gate 5K diffusion Region 5S source 6 isolation region 11 n-type semiconductor substrate 12 p-type semiconductor layer 13 n-type isolation region 15 oxide silicon film 15a element isolation region 20 PMOS transistor 20D drain 20G gate 20K n + type diffusion region 20S source 20w n-type well 21 NMOS transistor Reference Signs List 21D Drain 21G Gate 21K P + type diffusion region 21S Source 30 Image area 31 Photoelectric conversion p-type layer 32 Photoelectric conversion type n-type layer 33 n-type CCD diffusion layer 34 Channel region 35 Transfergage 71 n-type semiconductor substrate 72 p-type well 73 NMOS transistor 73D drain 73G gate 73K p + region 73S source 74 PMOS transistor 74D drain 74G gate 74K n + region 74S source

Claims (2)

[Claims] A first conductivity type semiconductor substrate; a second conductivity type semiconductor layer formed on the semiconductor substrate; a first conductivity type well formed in a part of the semiconductor layer; MOS of second conductivity type channel formed in the well
A transistor; a MOS transistor of a first conductivity type channel formed outside the well of the semiconductor layer; and a first conductive layer provided through the semiconductor layer in a thickness direction and separating two types of the MOS transistors. A semiconductor device having a mold separation region. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a semiconductor layer of a second conductivity type is formed on a semiconductor substrate of the first conductivity type by an epitaxial method. Diffusing a first conductivity type impurity into the semiconductor layer to form a first conductivity type well and a first conductivity type isolation region penetrating the semiconductor layer; and a second conductivity type channel in the well. Forming a MOS transistor of a first conductivity type channel in a region of the semiconductor layer separated from the well via the separation region. Manufacturing method.