JPH1167692A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, in which a Ti film is easily and securely formed into desired film thickness only at the base of an opening, safe and low contact resistance is obtained without being concerned about the removal of the Ti film, development to the fine opening is made easy, even if a semiconductor element is made fine and highly integrated and a stable characteristic is provided. SOLUTION: This Ti film is formed by a CVD method only for prescribed time within delay time, where the Ti film is not grown on an interlayer insulting film 8 by using a mix gas of TiCl4 and H2 . Reaction gas is switched from a mix gas to a fluorocarbon system gas of CF4 and the like, the surface of the interlayer insulating film 8 is etched, and a growth core 22 on the interlayer insulating film 8 is removed. Then, the Ti film 21 is stacked on the base in a contact hole 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a T
The present invention relates to a method for manufacturing a semiconductor device having an i-film formation process.

[0002]

2. Description of the Related Art In recent years, miniaturization and high integration of semiconductor devices have been progressing. Accordingly, it is necessary to promote the reduction of the resistance in the contact hole and the via hole. Then, the process by the Ti-CVD method is regarded as a promising next-generation technology candidate, but has not yet been put to practical use because of various problems. One of the problems of the Ti-CVD method is peeling of a formed Ti film. This is because the Ti film formed by the Ti-CVD method is a thin film having a considerably high stress. When a TiN film as an upper layer film is formed in a subsequent step, the Ti film on the silicon oxide film is formed. There was also a problem in that the risk of peeling of the film was high and the damage to the production line was large. Conventionally, therefore, this problem has been dealt with by imposing process restrictions such as limiting the film thickness during film formation.

[0003]

The thickness limit of the Ti film formed by the Ti-CVD method must be set to a very small value of about 5 nm. However, on the other hand, in order to stably obtain a low contact resistance, it is necessary to deposit a Ti film having a sufficient thickness at the bottom of the contact hole. Therefore, some ingenuity has been devised as described below.

For example, JP-A-6-326052 discloses that an Al film is selectively grown at the bottom of a contact hole by a CVD method, and the Ti film is formed by replacing the Al film with a Ti film using TiCl ₄ gas. Techniques are disclosed. However, mass production of the Al-CVD method is not expected at present, and it is considered that realization of this technique is extremely difficult.

Japanese Patent Application Laid-Open No. 7-106282 discloses that a Ti film is formed on an interlayer insulating film including an inner wall surface of a contact hole by a sputtering method, and that a sidewall surface of the contact hole is formed on the interlayer insulating film by ion milling. A technique for selectively removing the upper Ti film is disclosed. However, the contact hole is extremely fine, and it is difficult to leave the Ti film only at the bottom of the contact hole by ion milling, and there is a major problem in controllability.

Japanese Patent Application Laid-Open No. 7-283309 discloses that a contact hole is formed by lithography and dry etching in an interlayer insulating film deposited on an AL wiring film, and a Ti film is formed by a sputtering method before removing the resist film. A technique is disclosed in which a Ti film is removed together with a resist film after the Ti film is deposited, and the Ti film is left only in the bottom of the contact hole. However, the resist film has poor heat resistance, and may be dissolved at a high temperature during the formation of the Ti film. In addition, it is extremely difficult to control the thickness of the Ti film in the contact hole by sputtering, and it is inevitable that the splash from the resist film causes contamination in the sputtering apparatus.

Therefore, an object of the present invention is to enable a Ti film to be easily and reliably formed at a desired thickness only at the bottom of an opening, and to provide a stable and low contact resistance without fear of peeling of the Ti film. And manufacturing of a semiconductor device capable of realizing a semiconductor device having stable characteristics by facilitating development into finer openings even if further miniaturization and higher integration of a semiconductor element progresses. Is to provide a way.

[0008]

According to a method of manufacturing a semiconductor device of the present invention, an opening is formed in an interlayer insulating film having a semiconductor substrate or a high-melting-point conductive film as a lower layer so that a part of the surface of the lower layer is exposed. A first step of forming, a second step of performing chemical vapor deposition on a surface of the interlayer insulating film including the inside of the opening using a first reaction gas containing Ti, and Switching from the reaction gas to the second reaction gas for etching,
A third step of etching the surface of the interlayer insulating film, and forming a Ti film on the lower layer substantially exposed at the bottom of the opening.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the second step, the first reaction gas is supplied to the first reaction gas in the second step.
The chemical vapor deposition is performed in a plasma of the mixed gas of iCl ₄ and H ₂ .

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the third step, the etching is performed by T
This is performed immediately before the completion of the film formation delay on the interlayer insulating film i.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the third step, the second reaction gas is a fluorocarbon-based gas and used in plasma.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the third step, the second reaction gas is gas-phase HF.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the high melting point conductive film is a tungsten wiring or a polycrystalline silicon wiring.

In the method of manufacturing a semiconductor device according to the present invention, the interlayer insulating film is a silicon oxide film.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, after the first step, a process including the second step and the subsequent third step is repeatedly performed a plurality of times.

In one embodiment of the method for manufacturing a semiconductor device according to the present invention, a fourth step of forming a base film made of TiN on the interlayer insulating film including the inside of the opening after the third step. Forming a metal wiring layer that fills the opening and extends over the interlayer insulating film via the Ti film and the base film.

In the method of manufacturing a semiconductor device according to the present invention, a first step of forming an opening in an interlayer insulating film having a semiconductor substrate or a high-melting-point conductive film as a lower layer so that a part of the surface of the lower layer is exposed. And a mixed reaction gas obtained by adding a second reaction gas for etching to a first reaction gas containing Ti,
A second step of performing chemical vapor deposition and etching on the surface of the interlayer insulating film including the inside of the opening, and forming Ti on the lower layer exposed substantially at the bottom of the opening.
Form a film.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the second step, the first reaction gas is supplied to
A mixed gas of iCl ₄ and H ₂ is used.

In one embodiment of the method for manufacturing a semiconductor device according to the present invention, in the second step, the second reaction gas is a fluorocarbon-based gas.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the second step, the second reaction gas is gaseous HF.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the high melting point conductive film is a tungsten film or a polycrystalline silicon film.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the interlayer insulating film is a silicon oxide film.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, a third step of forming a base film made of TiN on the interlayer insulating film including the inside of the opening after the second step. Forming a metal wiring layer that fills the opening and extends over the interlayer insulating film through the Ti film and the base film.

A method of manufacturing a semiconductor device according to the present invention is a method of forming a Ti film by chemical vapor deposition on the bottom of an opening formed in an interlayer insulating film, wherein the Ti film is formed during the formation of the Ti film. The surface of the interlayer insulating film is etched.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, a mixed gas of TiCl ₄ and H ₂ is used as a reaction source gas, and the chemical vapor deposition is performed in a plasma of the mixed gas.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the etching process is performed immediately before the end of the film formation delay of Ti on the interlayer insulating film.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the etching gas used for the etching process is a fluorocarbon-based gas and used in plasma.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the etching gas used for the etching process is gas phase HF.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, a mixed gas obtained by adding a fluorocarbon-based gas to TiCl ₄ and H ₂ is used.
The etching process is performed simultaneously with the formation of the i-film.

[0030]

When a Ti film is formed by a chemical vapor deposition method (CVD method), on a semiconductor substrate or a high-melting-point conductive film, for example, a silicon layer or a tungsten film, the film thickness is longer than the film formation time of the Ti film. Although it shows an almost linear increasing tendency, on an interlayer insulating film represented by a silicon oxide film, T
A delay time (incubation time) occurs in which i-film growth does not occur. In the method of manufacturing a semiconductor device according to the present invention, the surface of the interlayer insulating film is etched before the formation of the film on the interlayer insulating film after the delay time has elapsed, and the surface of the interlayer insulating film is etched during the delay time. By removing the growth nuclei formed in step (1), the surface of the interlayer insulating film is always maintained in a delayed state in which the growth of the Ti film does not occur. So in this case,
The Ti film grows almost continuously on the surface of the semiconductor substrate or the high melting point conductive film exposed at the bottom of the opening, but is hardly formed on the interlayer insulating film. It is possible to selectively form only the bottom of the opening while controlling the thickness.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Some specific embodiments of the method of manufacturing a semiconductor device according to the present invention will be described below in detail with reference to the drawings.

(First Embodiment) First, a first embodiment will be described. In the first embodiment,
A MOS transistor will be exemplified as a semiconductor device, and a manufacturing method thereof will be described. 1 to 3 are schematic sectional views showing a method for manufacturing the MOS transistor according to the first embodiment in the order of steps.

First, as shown in FIG.
A field oxide film 3 is formed as a device isolation structure on a silicon semiconductor substrate 1 of a mold by a so-called LOCOS method to define a device formation region 2. Instead of the field oxide film 3, a conductive film is buried in the insulating film by a field shield element isolation method, and a portion of the silicon semiconductor substrate immediately below is fixed at a predetermined potential by the conductive film to perform element isolation. May be formed.

Subsequently, the surface of the silicon semiconductor substrate 1 in the element forming region 2 which is separated from each other by the field oxide film 3 and is relatively defined is thermally oxidized to form a silicon oxide film. A polycrystalline silicon film doped with impurities and a silicon oxide film are sequentially deposited on the polycrystalline silicon film.

Subsequently, the silicon oxide film, the polycrystalline silicon film and the silicon oxide film are patterned by photolithography and subsequent dry etching, and the silicon oxide film, the polycrystalline silicon film and the silicon oxide film are The gate oxide film 4, the gate electrode 5, and the cap insulating film 9 are formed while keeping the shape.

Subsequently, the photoresist used for patterning is removed by ashing, and then a silicon oxide film is deposited and formed on the entire surface including the upper surface of the cap insulating film 9 by a CVD method. Isotropic etching is performed to form sidewalls 6 while leaving the silicon oxide film only on the side surfaces of the gate oxide film 4, the gate electrode 5, and the cap insulating film 9.

Subsequently, impurities are implanted into the surface region of the silicon semiconductor substrate 1 on both sides of the gate electrode 5 by ion implantation using the cap insulating film 10 and the sidewalls 6 as a mask.
For example, an n-type impurity such as phosphorus (P) or arsenic (As) is introduced to form a pair of impurity diffusion layers 7 serving as a source / drain.

Next, as shown in FIG. 1B, CVD is performed on the entire surface of the silicon semiconductor substrate 1 including the field oxide film 3.
A silicon oxide film is deposited and formed by a method, and an interlayer insulating film 8 burying the gate oxide film 4, the gate electrode 5, and the cap insulating film 9 is formed.

Subsequently, the interlayer insulating film 8 is patterned,
A contact hole 11 exposing a part of the surface of the impurity diffusion layer 7 is formed.

Then, as shown in FIG. 1C, a Ti film 12 having a thickness of about 20 nm is formed at the bottom of the contact hole 11. Each step at this time is shown in FIGS. 2 (a) and 2 (b).
Shown in Note that the film types, film thicknesses, film forming conditions, etching conditions, and the like shown here are typical, and appropriate changes may be made according to the convenience of the production line. FIG.
2 (a) and FIG. 2 (b), an area around one contact hole 11 is enlarged.

First, using a parallel plate type plasma CVD chamber, TiCl ₄ gas (flow rate 5 s) was used as a reaction gas.
ccm) and H ₂ gas (flow rate 5 slm) using a supplied RF power of 400 W, a pressure of 3 Torr,
A film is formed for 10 seconds at each temperature of 650 ° C. (step 1). When the Ti film is formed by the CVD method, the film thickness on the silicon semiconductor substrate 1 tends to increase substantially linearly with respect to the film formation time of the Ti film, but on the interlayer insulating film 8 made of the silicon oxide film, A delay time (incubation time) occurs in which the growth of the Ti film does not occur in the initial stage of film formation. In this case, under the above-described film forming conditions, the delay time on the interlayer insulating film 8 is about 15 seconds.
As shown in FIG. 3, a Ti film 21 of about 2 nm is formed on the surface of the silicon semiconductor substrate 1 exposed at the bottom in the contact hole 11.
On the other hand, the growth nuclei 22 of the Ti film are slightly formed on the interlayer insulating film 8, but are not formed as a film.

Next, as shown in FIG. 2B, the reaction gas is switched from the mixed gas to a fluorocarbon gas such as CF _{4 and} the surface of the interlayer insulating film 8 is etched (step 2). At this time, since the Ti film 21 formed at the bottom in the contact hole 11 has a certain thickness, it is hardly affected by etching, and only the growth nucleus 22 on the interlayer insulating film 8 is etched. It is selectively removed.

Then, a series of processes including the step 1 and the subsequent step 2 is repeated 10 times. Thus, the Ti film 1 having a thickness of about 20 nm is formed only in the bottom of the contact hole 11.
2 will be formed. On the other hand, the Ti film is hardly formed on the interlayer insulating film 8 and the thickness is almost 0 nm.
It is.

Next, as shown in FIG. 3A, a TiN film 13 serving as a barrier metal layer is formed on the interlayer insulating film 8 by a CVD method so as to cover the inside of the contact hole 11 via the Ti film 12. .

Next, as shown in FIG. 3B, a W (tungsten) film is formed on the TiN film 13 by the CVD method so as to fill the contact holes 11, and the W film is patterned. , Ti film 12 and TiN film 1
Then, a wiring layer 14 electrically connected to the impurity diffusion layer 7 via 3 is formed.

Thereafter, a MOS transistor is completed through a post-process of forming a further upper interlayer insulating film, a wiring layer, and the like. The interface between the Ti film 12 and the impurity diffusion layer 7 is silicided by various heat treatments after the formation of the Ti film 12, and the TiSi ₂ (titanium silicide) layer 1 is formed.
5 will be formed.

As described above, in the first embodiment,
Before the film formation on the interlayer insulating film 8 is started after the delay time has elapsed, the surface of the interlayer insulating film 8 is etched to remove the growth nuclei 22 formed on the surface of the interlayer insulating film 8 during the delay time. By doing so, the surface of the interlayer insulating film 8 is always maintained in a delay state in which the growth of the Ti film does not occur. So in this case,
While the growth of the Ti film 21 proceeds almost continuously on the surface of the silicon semiconductor substrate 1 exposed at the bottom in the contact hole 11, the Ti film 12 is hardly formed on the interlayer insulating film 8. Contact hole 11 while controlling film thickness
Can be selectively formed only on the bottom portion of the substrate.

Therefore, according to the first embodiment, it is possible to easily and surely form the Ti film 12 to a desired thickness only at the bottom of the contact hole 11, and there is a concern that the Ti film 12 may be peeled off. Thus, a stable low contact resistance can be obtained, and even if further miniaturization and high integration of the MOS transistor progress, it is possible to easily develop the finer contact hole 11 and realize a MOS transistor having stable characteristics. it can.

-Modification- Here, a modification of the first embodiment will be described. In this modified example, a method for manufacturing a MOS transistor is illustrated as in the first embodiment described above.
The difference is that the i-CVD method is used not only for forming contact holes but also for forming via holes. 4 to 6 are schematic cross-sectional views showing a method of manufacturing a MOS transistor according to a modification in the order of steps.

First, as shown in FIGS. 1 to 3, the same steps as in the first embodiment are performed. Subsequently, as shown in FIG. 4A, an interlayer insulating film 31 made of a silicon oxide film is formed by a CVD method so as to cover the wiring layer 14 made of the W film. Note that the wiring layer 14 may be formed from a polycrystalline silicon film or a polycide film instead of being formed from the W film.

Next, the interlayer insulating film 31 is patterned,
A via hole 32 exposing a part of the surface of the wiring layer 14 is formed.

Then, as shown in FIG. 4B, a Ti film 33 is formed at the bottom of the via hole 32. Each step at this time is shown in FIGS. 5 (a) and 5 (b). Note that the film types, film thicknesses, film forming conditions, etching conditions, and the like shown here are typical, and appropriate changes may be made according to the convenience of the production line. 5 (a) and 5 (b),
The periphery of one via hole 32 is shown in an enlarged manner.

First, using a parallel plate type plasma CVD chamber, the same conditions as in the first embodiment were used, that is, a mixed gas of TiCl ₄ gas (flow rate 5 sccm) and H ₂ gas (flow rate 5 slm) was used as a reaction gas. Then, a film is formed for 10 seconds under the conditions of the input RF power of 400 W, the pressure of 3 Torr, and the temperature of 650 ° C. (Step 1). When the Ti film is formed by the CVD method, the film thickness on the wiring layer 14 shows an almost linear increasing tendency with respect to the film forming time of the Ti film.
On the interlayer insulating film 31 made of a silicon oxide film, a delay time (incubation time) occurs in which the growth of the Ti film does not occur in the initial stage of film formation. In this case, the delay time on the interlayer insulating film 31 is about 15
Seconds, as shown in FIG.
While a Ti film 41 of about 2 nm is deposited on the surface of the wiring layer 14 exposed at the bottom of the inside, only a small growth nucleus 42 of the Ti film is formed on the interlayer insulating film 31 and the Is not formed.

Next, as shown in FIG. 5B, the reaction gas is switched from the mixed gas to a fluorocarbon-based gas such as CF _{4 and} the surface of the interlayer insulating film 31 is etched (step 2). At this time, since the Ti film 41 formed at the bottom in the via hole 32 has a certain thickness, it is hardly affected by the etching, and the interlayer insulating film 3 is formed.
Only the growth nuclei 42 on 1 are selectively removed by etching.

Then, a series of processes including the step 1 and the subsequent step 2 is repeated 10 times. As a result, a Ti film 33 of about 20 nm is formed only at the bottom in the via hole 32. On the other hand, Ti
The film is hardly formed, and the film thickness is almost 0 nm.

Next, as shown in FIG. 6A, a TiN film 34 serving as a barrier metal layer is formed on the interlayer insulating film 31 so as to cover the inside of the via hole 33 via the Ti film 33 by the CVD method.
To form

Next, as shown in FIG. 6B, a TiN film 34 is buried in the via hole 32 by sputtering.
A W (tungsten) film is formed thereon, and the W film is patterned to form a wiring layer 35 electrically connected to the wiring layer 14 via the Ti film 33 and the TiN film 34.

Thereafter, through various post-processes, the MOS transistor is completed.

As described above, in the modification of the first embodiment, the surface of the interlayer insulating film 31 is etched before the formation of the film on the interlayer insulating film 31 is started after the delay time has elapsed. By removing the growth nuclei 42 formed on the surface of the interlayer insulating film 31 during the time, the surface of the interlayer insulating film 31 is always maintained in a delay state in which the growth of the Ti film does not occur. Therefore, in this case, the Ti film 4 is almost continuously formed on the surface of the silicon semiconductor substrate 1 exposed at the bottom in the via hole 32.
While the growth of No. 1 proceeds, the Ti film 33 is hardly formed on the interlayer insulating film 31, so that the Ti film 33 can be selectively formed only at the bottom of the via hole 32 while controlling the film thickness. .

Therefore, according to the modification of the first embodiment, in addition to the effect of the first embodiment, the Ti film 33 is formed
2 can be easily and reliably formed to a desired film thickness only, and a stable low contact resistance can be obtained without concern about peeling of the Ti film 33. Further miniaturization and high integration of MOS transistors Even if the formation of the MOS transistor progresses, it is possible to easily develop the finer via hole 32 and realize a MOS transistor having more stable characteristics.

In this modification, the contact holes 11
At the same time, the case where the Ti-CVD method is applied to the via hole 32 and the Ti film is formed only on the bottoms thereof has been described. However, it is naturally possible to apply the Ti film only to the via hole.

(Second Embodiment) Next, a second embodiment of the present invention will be described. In the second embodiment, as in the case of the first embodiment, a method for manufacturing a MOS transistor is exemplified, but it is different in that there is a slight difference in a wiring forming process. FIG. 7 is a schematic sectional view showing main steps of a method for manufacturing a MOS transistor according to the second embodiment. Note that the same components as those of the MOS transistor of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

First, as shown in FIGS. 1A and 1B,
The gate electrode 5 and the pair of impurity diffusion layers 7 and the contact holes 11 of the MOS transistor are formed through the same steps as in the first embodiment. Subsequently, a Ti film 12 is formed at the bottom of the contact hole 11 as shown in FIG. FIG. 7 shows the process at this time. Note that the film types, film thicknesses, film forming conditions, etching conditions, and the like shown here are typical, and appropriate changes may be made according to the convenience of the production line. In FIG. 7, one contact hole 11 is formed.
Is shown in an enlarged manner.

Next, using a parallel plate type plasma CVD chamber, TiCl ₄ gas (flow rate 5 s) was used as a reaction gas.
ccm) and H ₂ gas (flow rate 5 slm) while further adding a fluorocarbon-based gas such as CF ₄
Film formation is performed for 200 seconds under the conditions of an input RF power of 400 W, a pressure of 3 Torr, and a temperature of 650 ° C.

When the Ti film is formed by the CVD method, the thickness of the Ti film on the silicon semiconductor substrate 1 tends to increase substantially linearly with respect to the film formation time of the Ti film, but the interlayer insulating film 8 made of a silicon oxide film Above, a delay time (incubation time) occurs in which the growth of the Ti film does not occur in the initial stage of film formation. In this case, a Ti film is deposited on the surface of the silicon semiconductor substrate 1 exposed at the bottom in the contact hole 11 by the mixed gas of the TiCl ₄ gas and the H ₂ gas, whereas the fluorocarbon-based gas added to the mixed gas is Since the film formation proceeds while etching and removing the growth nucleus 22 of the Ti film on the interlayer insulating film 8, the film is not formed.

That is, as shown in FIG.
1, a Ti film 12 having a thickness of about 20 nm is formed only on the bottom portion. On the other hand, a Ti film is hardly formed on the interlayer insulating film 8, and the film thickness is almost 0 nm.

Thereafter, as in the first embodiment, FIG.
3 (b), a wiring layer 14 electrically connected to the impurity diffusion layer 7 via the Ti film 12 and the TiN film 13 is formed to complete the MOS transistor.

As described above, in the second embodiment,
At the same time as the formation of the Ti film using the mixed gas of TiCl ₄ gas and H ₂ gas as the reaction source, the etching of the growth nucleus 22 of the Ti film using the fluorocarbon-based gas added to the mixed gas as the etching gas is performed simultaneously. At this time, the Ti film grows almost continuously in proportion to the film formation time on the surface of the silicon semiconductor substrate 1 exposed at the bottom in the contact hole 11, while the Ti film grows almost continuously. Above, the growth nucleus 22 is etched and removed at the stage of forming or not and almost no film is formed. Therefore, it is necessary to selectively form the Ti film 12 only on the bottom of the contact hole 11 while controlling the film thickness. it can.

Therefore, according to the second embodiment, it is possible to easily and surely form the Ti film 12 to a desired thickness only at the bottom of the contact hole 11, and to worry about peeling of the Ti film 12. Thus, a stable low contact resistance can be obtained, and even if further miniaturization and high integration of the MOS transistor progress, it is possible to easily develop the finer contact hole 11 and realize a MOS transistor having stable characteristics. It becomes possible.

In the second embodiment, similarly to the first embodiment, as a modification, the Ti-CVD method is used not only for forming the contact holes but also for forming the via holes, and the TiCl ₄ gas is used. In addition to the formation of a Ti film using a mixed gas of H ₂ gas and H ₂ gas as a reaction source, etching of a growth nucleus of the Ti film using a fluorocarbon-based gas added to the mixed gas as an etching gas is performed at the same time.
Similarly to the above, the Ti film may be formed only on the bottom in the via hole.

In the first and second embodiments, the MO
Although the S-transistor has been described, the present invention is not limited to this, and is applicable to all semiconductor device manufacturing methods that require high integration such as a semiconductor memory such as an EEPROM or a DRAM or a CMOS inverter.

[0072]

According to the method of manufacturing a semiconductor device of the present invention, it is possible to easily and surely form a Ti film only at the bottom of an opening to a desired thickness, and to worry about peeling of the Ti film. And a stable low contact resistance can be obtained, and even if further miniaturization and high integration of the semiconductor element progress, development into finer holes can be facilitated to realize a semiconductor device having stable characteristics. .

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a method of manufacturing a MOS transistor according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a schematic cross-sectional view for explaining the step of FIG. 1C in further detail.

FIG. 3 is a schematic cross-sectional view showing a method of manufacturing the MOS transistor according to the first embodiment of the present invention in the order of steps.

FIG. 4 shows an MO according to a modification of the first embodiment of the present invention.
FIG. 4 is a schematic cross-sectional view showing a method for manufacturing an S transistor in the order of steps.

FIG. 5 is a schematic cross-sectional view for explaining the step of FIG. 4C in further detail.

FIG. 6 shows an MO according to a modification of the first embodiment of the present invention.
FIG. 4 is a schematic cross-sectional view showing a method for manufacturing an S transistor in the order of steps.

FIG. 7 is a schematic sectional view showing main steps of a method for manufacturing a MOS transistor according to a second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon semiconductor substrate 2 Element formation area 3 Field oxide film 4 Gate oxide film 5 Gate electrode 6 Side wall 7 Impurity diffusion layer 8, 31 Interlayer insulating film 11 Contact hole 12, 33 Ti film (of about 20 nm thickness) 13, 34 TiN film 14, 35 Wiring layer 21, 41 Ti film (with a thickness of about 2 nm) 22, 42 Growth nucleus 32 Via hole

Claims (22)

[Claims] A first step of forming an opening in an interlayer insulating film in which a semiconductor substrate or a high-melting-point conductive film exists in a lower layer so that a part of the surface of the lower layer is exposed; With respect to the surface of the interlayer insulating film, Ti
A second chemical vapor deposition using a first reaction gas containing
And a third step of etching the surface of the interlayer insulating film by switching from the first reaction gas to the second reaction gas for etching, and substantially exposing the bottom of the opening. A method of manufacturing a semiconductor device, comprising forming a Ti film on the lower layer. 2. The method according to claim 1, wherein in the second step, the first reaction gas is a mixed gas of TiCl ₄ and H ₂ , and the chemical vapor deposition is performed in a plasma of the mixed gas. The manufacturing method of the semiconductor device described in the above. 3. The semiconductor device according to claim 1, wherein, in the third step, the etching process is performed immediately before a delay in forming a film of Ti on the interlayer insulating film is completed. Production method. 4. The semiconductor device according to claim 1, wherein, in the third step, the second reaction gas is a fluorocarbon-based gas and is used in a plasma. Method. 5. The method according to claim 1, wherein in the third step, the second reaction gas is a gas phase HF.
13. The method for manufacturing a semiconductor device according to claim 1. 6. The method according to claim 1, wherein the high melting point conductive film is a tungsten wiring or a polycrystalline silicon wiring.
6. The method for manufacturing a semiconductor device according to any one of items 5 to 5. 7. The method according to claim 1, wherein the interlayer insulating film is a silicon oxide film. 8. The method according to claim 1, wherein after the first step, a process including the second step and the subsequent third step is repeatedly performed a plurality of times. 13. The method for manufacturing a semiconductor device according to item 5. 9. A fourth step of forming a base film made of TiN on the interlayer insulating film including the inside of the opening after the third step, and through the Ti film and the base film, A fifth step of forming a metal wiring layer that fills the opening and extends on the interlayer insulating film.
13. The method for manufacturing a semiconductor device according to claim 1. 10. A first step of forming an opening in an interlayer insulating film in which a semiconductor substrate or a high-melting-point conductive film exists in a lower layer so that a part of the surface of the lower layer is exposed; A second step of performing chemical vapor deposition and etching on the surface of the interlayer insulating film including the inside of the opening using a mixed reaction gas obtained by adding a second reaction gas for etching to the reaction gas of A method of manufacturing a semiconductor device, comprising: forming a Ti film on the lower layer substantially exposed at the bottom of the opening. 11. The method according to claim 10, wherein in the second step, the first reaction gas is a mixed gas of TiCl ₄ and H ₂ . 12. The method according to claim 10, wherein in the second step, the second reaction gas is a fluorocarbon-based gas. 13. The method of manufacturing a semiconductor device according to claim 10, wherein in the second step, the second reaction gas is gas phase HF. 14. The high-melting-point conductive film is a tungsten film or a polycrystalline silicon film.
14. The method of manufacturing a semiconductor device according to any one of items 13 to 13. 15. The method according to claim 10, wherein said interlayer insulating film is a silicon oxide film. 16. After the second step, a third step of forming a base film made of TiN on the interlayer insulating film including the inside of the opening, via the Ti film and the base film, Forming a metal wiring layer that fills the opening and extends over the interlayer insulating film.
16. The method for manufacturing a semiconductor device according to any one of items 15 to 15. 17. A method for manufacturing a semiconductor device, wherein a Ti film is formed by chemical vapor deposition on a bottom of an opening formed in an interlayer insulating film, wherein the surface of the interlayer insulating film is formed during the formation of the Ti film. A method of manufacturing a semiconductor device, characterized by etching a semiconductor device. 18. A reaction source gas comprising TiCl ₄ and H
18. The method for manufacturing a semiconductor device according to claim 17, wherein the chemical vapor deposition is performed in a plasma of the mixed gas using the mixed gas of ( ₂ ). 19. The method of manufacturing a semiconductor device according to claim 17, wherein the etching process is performed immediately before the end of the film formation delay of Ti on the interlayer insulating film. 20. The method of manufacturing a semiconductor device according to claim 17, wherein an etching gas used for the etching process is a fluorocarbon-based gas and used in plasma. 21. An etching gas used for the etching process is gaseous phase HF.
20. The method of manufacturing a semiconductor device according to claim 19. 22. The etching method according to claim 17, wherein the etching process is performed simultaneously with the formation of the Ti film by the chemical vapor deposition using a mixed gas obtained by adding a fluorocarbon-based gas to TiCl ₄ and H ₂ . A method for manufacturing a semiconductor device.