JPH1165838A - Arithmetic and logic unit and setting method for wait time of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the arithmetic and logic unit which can easily and accurately set a wait time with a small program quantity by inserting a certain wait instruction between an instruction and a next instruction. SOLUTION: A control ROM 1b is stored with control information of a data bus part 7. A sequence ROM 1a is stored with the storage address of a microcode to be executed next. Output signals S0 to SJ from the control ROM 1b are temporarily latched by a latch circuit 2 and then outputted to a data path part 7. Output signals A0 to AI from the sequence ROM 1a are temporarily latched and then outputted to a microaddress generating circuit 3. An instruction register 6 is stored with the instruction code of a wait instruction and the data path part 7 is stored with a value specifying how many cycles a wait is made for. The signals S0 to SJ control the data path part 7 to insert a certain wait instruction between an instruction and a next instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit capable of inserting wait cycles by a designated number of machine cycles, and a method of setting a waiting time in the arithmetic unit.

[0002]

2. Description of the Related Art FIG.
A flowchart showing a method of setting a waiting time by an instruction,
FIG. 11 is a flowchart showing a method of setting a waiting time by another NOP instruction in a conventional arithmetic device, and FIG. 12 is a flowchart showing a method of setting a waiting time using a timer in a conventional arithmetic device. FIG. 10 shows a program flow when the waiting time is short, in which a plurality of NOP instructions are inserted between the instruction A and the instruction B.
If two cycles are required to execute one NOP instruction, a wait time of 20 cycles can be set by inserting ten NOP instructions.

FIG. 11 shows the flow of a program in the case where the waiting time is long, in which a time waiting loop is inserted between the instruction A and the instruction B. For example, '8' is set in the A register. After that, the contents of the A register are decremented. If the contents of the A register are "0", the processing shifts to the next instruction. If not, the processing returns to DECA. FIG. 12 shows a program flow when the waiting time is long.
The waiting time can be set by using a general-purpose timer built in the microcomputer. An interrupt is generated between the instruction A and the instruction B when an instruction for starting the timer and an initially set cycle are counted. This is to end the timer.

[0004]

The conventional arithmetic unit and the method of setting the waiting time in this arithmetic unit are configured as described above. Therefore, in the method of setting the waiting time using the NOP instruction, the programmer needs to execute each instruction. It is necessary to perform programming while adding the number of execution cycles of a (NOP instruction or an instruction constituting a loop), which requires a lot of work and makes it difficult to set an accurate time.
In particular, recent high-performance microcomputers incorporating pipeline processing and instruction prefetching functions have had a problem that it is difficult to accurately calculate the number of execution cycles of each instruction.

The setting of a waiting time using a general-purpose timer requires a lot of extra programming such as initial setting of a timer and preparation of an interrupt processing routine, and is not suitable for setting a short waiting time. was there.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an arithmetic unit and a computer which can easily and accurately set a waiting time and can set the waiting time with a small program amount. An object of the present invention is to obtain a method of setting a waiting time in an arithmetic device.

[0007]

An arithmetic unit according to the present invention decodes an instruction code input by a microaddress generation circuit, sets an address where a microcode to be executed is stored, and sets an address. The control information corresponding to each address stored in the address input from the micro address generation circuit is output by the micro code ROM, and the micro address generation address is stored in the micro code ROM. When the control information is input by the data path unit and the control information is input, a wait time value specifying how long to wait between instructions after completion of execution of the instruction is input via the data bus. Subtracts the value by the specified value, and inputs the storage address of the microcode to be executed next when the subtraction result becomes 0 The variable signal is obtained so as to output to the micro address generation circuit.

According to a second aspect of the present invention, there is provided a method for setting a waiting time in an arithmetic unit, which decodes an input instruction code, sets an address at which a microcode to be executed is stored, and outputs the address. The control information corresponding to each address stored in the address is output, and the storage address of the microcode to be executed next is output.
When the control information is input, a wait time value specifying how long to wait between instructions after completion of execution of the instruction is input via the data bus, and the wait time value is subtracted by the specified value, When the result of the subtraction becomes 0, an input permission signal for the storage address of the microcode to be executed next is output.

According to the third aspect of the present invention, when an arbitrary value is set in the down counter, the content is decremented every cycle of the basic clock independently of the other circuits of the CPU section. The contents of the value of the down counter are checked by the zero detection circuit, and if it is zero, a zero detection signal is output to the micro address generation circuit. This is to input the storage address of the microcode to be executed.

According to a fourth aspect of the present invention, there is provided a method for setting a waiting time in an arithmetic unit, the method comprising the steps of:
After decrementing the content of each cycle of the basic clock independently of the other circuits of the U section, the content of this value is checked. If the value is zero, a zero detection signal is output to the microaddress generation circuit. The micro-address generation circuit to which the detection signal is input is configured to input the storage address of the micro-code to be executed next from the micro-code ROM.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram showing an arithmetic unit according to Embodiment 1 of the present invention. In FIG. 1, reference numeral 1 denotes a microcode ROM comprising an output I-bit sequence ROM 1a and an output J-bit control ROM 1b; This is a latch circuit for latching an output signal output from the ROM 1. Output signals S0 to SJ from the control ROM 1b are output to the data path unit 7 based on timing determined once after being latched. on the other hand,
The output signals A0 to AI from the sequence ROM 1a are output to the micro-address generation circuit 3 based on the timing determined once after being latched.

Reference numeral 3 denotes a micro address generating circuit for determining a storage address of a microcode to be executed next based on output signals A0 to AI from the sequence ROM 1a and outputting it to the address decoder 4, and 4 a micro address generating circuit 3.
Is an address decoder that decodes an address input from the microcode ROM 1 and outputs the decoded signal to the microcode ROM 1 as a decode signal 5. In the first machine cycle of the instruction execution, the micro address generation circuit 3 sets the instruction register 6
An instruction code is received and decoded to determine a microcode address.

Next, the operation will be described. FIG. 2 is a flowchart schematically showing an instruction mounting method according to the first embodiment of the present invention. As shown in FIG. 2, a NOP instruction capable of arbitrarily specifying an instruction execution cycle number n is set as one of basic instructions. Implemented on a computer and placed between instruction A and instruction B. The value of n is arbitrarily set by the programmer. In general, the execution of instructions of a microcomputer is performed by sequentially executing a plurality of microcodes (microinstructions). For example, if an instruction is in the A.D. B. This is executed by executing the microcode stored in the three addresses of C in this order. In this case, first, the instruction code of this instruction is decoded in the micro-address generation circuit 3, and the storage address A of the micro-code to be executed is obtained first, and this is output to the microcode ROM 1 via the address decoder 4.

The control ROM 1b stores control information of the data path unit 7 corresponding to each address. on the other hand,
The storage address (B in this case) of the microcode to be executed next is stored in the sequence ROM 1a, and the signals S0 to SJ and A0 to AI are passed through the latch circuit 2.
Is output as S0 to SJ are sent to the data path unit 7 to cause the data path unit 7 to perform work corresponding to the address A. On the other hand, A0 to AI are returned to the microaddress generation circuit 3, which is normally input to the microcode ROM 1 through the address decoder 4 in the next cycle as it is,
The microcode stored at address B is executed next.
According to this principle, the microcodes stored in the three addresses A, B, and C are sequentially executed, and the execution of one instruction is completed.

Next, the instruction execution sequence will be described in more detail with reference to the timing chart of FIG. FIG. 3 is a timing chart showing an execution sequence of the arithmetic unit according to the first embodiment of the present invention.
This is a basic clock of the PU unit, and one cycle corresponds to one machine cycle. First, Ф in cycle (8)
The instruction register 6 outputs the instruction code to the micro address generation circuit 3 during the period of “L”. Next, the micro address generation circuit 3 determines the address A where the micro code to be executed first is stored when the instruction code is decoded and this instruction is executed.
To the address decoder 4. The address decoder 4 immediately decodes the input address and outputs a decode signal 5 to the microcode ROM 1.

As a result, the contents stored in the address A of the control ROM 1b and the sequence ROM 1b are output during the period of Ф = “L” in the cycle (9). Control RO
After the output from M1b is once latched by the latch circuit 2, the signals S0 to SJ are output at predetermined timings.
Is output to the data path unit 7 and controlled. On the other hand, the output of the sequence ROM 1a indicates the storage address B of the microcode to be executed next, and is similarly held by the latch circuit 2 until the period of Ф = 'H' shown in the next cycle (10). .

Then, the micro address generating circuit 3 receives the output from the sequence ROM 1a and uses it as the next micro code address in the cycle (10).
To the address decoder 4 during the period. By repeating the above operation for each machine cycle, the microcode stored at each of the addresses A, B, and C is sequentially shifted to execution, and the instruction is completed. At the same time, the next instruction code is sent from the instruction register to the microaddress generation circuit 3 during the period of Ф = “L” in the cycle indicated by the cycle (11), and the execution of the next instruction is started.

Next, a method of realizing an n-cycle NOP instruction will be described. 4 is a configuration diagram showing a specific configuration of the arithmetic unit according to Embodiment 1 of the present invention, FIG. 5 is a flowchart showing an instruction execution sequence of a wait instruction of the arithmetic unit of FIG. 4, and FIG. 6 is an arithmetic unit of FIG. 6 is a timing chart showing the wait instruction of FIG. First, cycle (12)
The instruction code of this instruction is stored in the instruction register 6 during the period of Ф = “L”, and at the same time, the value of n designating how many cycles to wait is stored in the operand register 18. Next, the contents of the instruction register 6 are immediately transferred to the micro-address generation circuit 3, and the micro-address generation circuit 3 decodes the instruction code to determine the address A where the micro code to be executed first is stored. .

It is assumed that the micro address has a length of 8 bits, and the address A is "00H". Therefore, in the cycle (13), the address '00H' is output to the microcode ROM 1 via the address decoder 4, and
The contents of the address '00H' are read during the period of Ф = 'L'. A part of the read signal is supplied to the latch circuit 2
, And are output to the data path unit 7 as S0 to SJ signals in the next cycle (14) at a timing determined for each signal.

The S0 to SJ signals cause the data path unit 7 to execute the following work in the cycle (14). Ф =
During the period of “H”, the content (n) of the operand register 18 is read out to the I bus, and “1” is output to the D bus. I
The contents read to the bus and the D bus are output by the latch 19
= 'L' and output to the I 'and D' buses, respectively. Next, in the ALU, the content of the D 'bus is subtracted from the content of the I' bus (n-1 is executed), and the result is stored in the temporary register 20 during the period of Ф = 'H'. This content is checked by the zero detection circuit 21. If it is zero, the zero detection signal Z0 = 'H'
If not zero, the zero detection signal Z0 = 'L'. That is, if the operation result of n-1 is zero, Z0 =
'H', otherwise Z0 = 'L'.

On the other hand, in the cycle (13), Ф =
The next micro address read from the address "00H" of the sequence ROM 1a during the period "L" is B, and here it is assumed that B = address "03H". The read content passes through the latch circuit 2 and Ф = “L” in cycle (13).
Are output to the microaddress generation circuit 3 as A0 to A7 signals = `03H` from the period of the period to the period of Ф =` H` in the next cycle (14). However, among these signals, the A0 signal is ANDed with the inverted signal of the previous zero detection signal Z0.
After that, it is output to the micro address generation circuit 3. Therefore, the result of n-1 executed by the data path unit 7 in the cycle (14) is not zero (Z0 =
'L') is output to the micro address generation circuit 3, and the micro address to be executed next remains '03H'.

However, if the result of n-1 executed by the data path unit 7 in cycle (14) is zero (Z0
= 'H'), and is changed to '02H' (here, this '02H' address is C). Therefore, the address output to the microcode ROM 1 in the cycle (14) is B = '03H', and the operation of the data path unit 7 based on the control information of the address is changed to the next cycle (15).
Executed in That is, in this cycle (15),
When the content (n-1) of the temporary register 20 is transferred to the I bus,
'1' is read out to the D bus, and in the ALU (n-1)-
1 is executed, and the result n-2 is stored in the temporary register 2 again.
0 is stored. Here, zero detection is performed again to determine the value of Z0.

On the other hand, a sequence ROM at address '03H'
The content of 1a indicates the address '03H' which is itself.
Subsequent operations are repeated until the value of the temporary register 20 is decremented to zero. When zero is detected, the microaddress becomes C = '02H' and the instruction is terminated. Although the number of execution cycles of this instruction is n + 1, it can be solved by correcting -1 when converting a value specified by the programmer into a machine language by a compiler.

As described above, according to the first embodiment, by inserting a constant wait instruction between an instruction and the next instruction, the waiting time can be easily and accurately set, and the waiting time can be easily set. The advantage is that the time can be set with a small program amount.

Embodiment 2 FIG. 7 is a configuration diagram showing an arithmetic unit according to Embodiment 2 of the present invention.
The same reference numerals as those in the first embodiment denote the same or corresponding parts, and a description thereof will not be repeated. Reference numeral 22 denotes a down counter for setting an arbitrary value n. After the value n is set, the content of the down counter is decremented every cycle of Ф independently of other circuits of the CPU section. 23 is a down counter 2
The content of the value n of 2 is checked. If it is zero, the zero detection signal Z0 is set to "H".
= 'L'.

Next, the operation will be described. FIG. 8 is a flowchart showing a flow of instruction execution of the arithmetic unit according to the second embodiment of the present invention, and FIG. 9 is a flowchart showing an instruction execution sequence of the arithmetic unit according to the second embodiment of the present invention. First, a zero detection signal Z0 which is an output from the zero detection circuit 23 attached to the down counter 22
As in the first embodiment, the inverted signal is ANDed with the A0 signal of the output of the latch circuit 2 of the microcode ROM 1 and output to the microaddress generation circuit 3. After the value is set in the down counter by the instruction a, the CP
U sequentially executes the following instruction C. When the instruction "b" is executed, the process waits until the value of the down counter previously set becomes zero, and then proceeds to the execution of the instruction "B".

The execution sequence of the instruction b is as shown in FIG. Using the same principle as that of the control of the n-cycle wait instruction shown in the first embodiment, the contents of address A (NOP) are repeatedly executed until the contents of the down counter become zero, and the zero detection signal Z0 becomes '0'. When it becomes H ', it moves to address B and ends the instruction. According to this embodiment, even if another process enters between the instruction A and the instruction B, the waiting time between the instruction A and the instruction B is accurately set without calculating the number of cycles required for this process. it can.

As described above, according to the second embodiment, in addition to the effect of the first embodiment, there is an effect that other processing can be executed during a waiting time between instructions. can get.

[0029]

As described above, according to the present invention, by inserting a constant wait instruction between an instruction and the next instruction, the wait time can be easily and accurately set, and the wait time can be easily set. Can be set with a small program amount.

According to the present invention, there is an effect that other processing can be executed during a waiting time between instructions.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an arithmetic unit according to Embodiment 1 of the present invention.

FIG. 2 is a flowchart schematically illustrating a method of mounting instructions according to the first embodiment of the present invention.

FIG. 3 is a timing chart showing an execution sequence of the arithmetic unit according to the first embodiment of the present invention.

FIG. 4 is a configuration diagram showing a specific configuration of an arithmetic unit according to Embodiment 1 of the present invention;

FIG. 5 is a flowchart showing an instruction execution sequence of a wait instruction of the arithmetic unit in FIG. 4;

6 is a timing chart showing a wait instruction of the arithmetic unit in FIG.

FIG. 7 is a configuration diagram showing an arithmetic unit according to Embodiment 2 of the present invention.

FIG. 8 is a flowchart showing a flow of instruction execution of an arithmetic unit according to Embodiment 2 of the present invention;

FIG. 9 is a flowchart showing an execution sequence of an instruction of an arithmetic unit according to Embodiment 2 of the present invention;

FIG. 10 is a flowchart showing a method of setting a waiting time by a NOP instruction in a conventional arithmetic device.

FIG. 11 is a flowchart illustrating a method of setting a waiting time by another NOP instruction in a conventional arithmetic device.

FIG. 12 is a flowchart illustrating a waiting time setting method using a timer in a conventional arithmetic device.

[Explanation of symbols]

1 microcode ROM, 3 micro address generation circuit, 4 address decoder, 7 data path section, 22
Down counter, 23 Zero detection circuit.

Claims (4)

[Claims] 1. A microcode ROM for storing control information corresponding to each address and storing a storage address of a microcode to be executed next, and an operation corresponding to an address stored in the microcode ROM. An arithmetic device comprising: a data path unit to be executed; and a micro address generation circuit that inputs a storage address of a microcode stored in the microcode ROM and outputs the input address to the microcode ROM via an address decoder. The micro address generation circuit decodes the input instruction code, sets the address where the micro code to be executed is stored, and outputs the address via the address decoder. The micro code ROM reads the micro code ROM from the micro address generation circuit. Corresponding to each address stored in the entered address In addition to outputting the control information, the storage address of the microcode to be executed next is output to the microaddress generation circuit.When the control information is input, the data path unit switches between the instructions after the execution of the instruction is completed. A wait time value specifying how long to wait is input via the data bus, the wait time value is subtracted by the specified value, and when the result of the subtraction becomes 0, the microcode to be executed next is stored. An arithmetic unit for outputting an address input enable signal to the micro address generation circuit. 2. Control information corresponding to each address is stored, a storage address of a microcode to be executed next is stored, an operation corresponding to the stored address is executed, and the stored address is stored. In a method of setting a waiting time in an arithmetic unit that inputs a storage address of a microcode and outputs the address through an address decoder, the input instruction code is decoded, and output after setting an address where a microcode to be executed is stored. Then, while outputting the control information corresponding to each address stored in the input address, outputting the storage address of the microcode to be executed next, and inputting the control information, the instruction and the instruction are executed after the execution of the instruction is completed. Enter a wait time value over the data bus that specifies how long to wait between and the wait time value. A method for setting a waiting time in an arithmetic device, wherein an input permission signal of a storage address of a microcode to be executed next is output when the result of the subtraction becomes 0. 3. When an arbitrary value is set, a down counter for decrementing the content every cycle of the basic clock independently of other circuits of the CPU unit, and checking the content of the value of the down counter, A micro address generation circuit that outputs a zero detection signal to the micro address generation circuit if it is zero, and the micro address generation circuit that receives the zero detection signal inputs the storage address of the next micro code to be executed from the micro code ROM The arithmetic device according to claim 1, wherein: 4. When an arbitrary value is set, the content is decremented every cycle of the basic clock independently of other circuits of the CPU unit, and the content of this value is checked. 3. The micro-address generation circuit according to claim 2, wherein the detection signal is output to a micro-address generation circuit, and the micro-address generation circuit to which the zero detection signal is input inputs a storage address of a microcode to be executed next from a microcode ROM. A method for setting a waiting time in an arithmetic unit.