JPH1165530A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption by changing over the frequency of a clock signal generated in a clock-generating part, in accordance with a resolving power displayed in a liquid crystal display part. SOLUTION: A vertical shift register 3 successively outputs a pulse signal, corresponding to one line to plural scanning lines x1-x3 and makes a transister Tr of each pixel an ON-state in a line unit. A horizontal shift register 4 successively outputs a gate signal to plural gate lines (a)-(f), corresponding to plural signal lines y1-y6. A display signal corresponding to each pixel is sent from a display signal line S, and a signal charge is charged in a capacitor Co. Such output signals in the vertical shift resister 3 and the horizontal shift register 4 are outputted, being synchronized with a clock signal generated in a clock- generating part. The frequency of the clock signal given to the vertical shift resister 3 and the horizontal shift register 4 from the clock-generating part is changed, in accordance with the resolving power displayed in a liquid crystal display part 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device for displaying images at a predetermined resolution.

[0002]

2. Description of the Related Art A liquid crystal display device used as a display device of a computer or the like is widely used in recent years because it is thinner and lighter than a CRT display.

In this liquid crystal display device, liquid crystal is filled between two substrates, and a predetermined signal is applied to a plurality of scanning lines and a plurality of signal lines provided in a matrix on the substrates. The display is performed by controlling the arrangement state of the liquid crystal material.

[0004] Such a liquid crystal display device is widely used particularly in portable devices such as computers. Therefore, it is necessary to drive each unit using a power supply built in the device. In order to perform long-time driving, it is necessary to reduce the power consumption of a liquid crystal display device driven by this built-in power supply (for example, a storage battery). Is desired.

On the other hand, the display performance of a liquid crystal display device is as follows.
As the display area becomes larger and the definition becomes higher, there is a demand for a device that can be applied to a device such as a high-performance computer even if it has portability.

[0006]

However, an increase in the size and definition of a liquid crystal display device requires a large amount of power consumption.
This hinders lower power consumption. In addition, since constant driving is performed irrespective of information to be displayed, there is a problem that power is unnecessarily wasted.

[0007]

SUMMARY OF THE INVENTION The present invention is a liquid crystal display device for solving such a problem. That is, the liquid crystal display device of the present invention provides liquid crystal display means for performing a predetermined display based on signals supplied to a plurality of scanning lines and a plurality of signal lines arranged in a matrix, and for supplying the signals. Clock signal generating means for generating the clock signal of the above, and switching means for switching the frequency of the clock signal generated by the clock signal generating means in accordance with the resolution displayed by the liquid crystal display means.

In the present invention, since the frequency of the clock signal generated by the clock generating means is switched by the switching means in accordance with the resolution displayed by the liquid crystal display means, a clock signal having a frequency matching the display resolution is generated. Thus, power consumption can be reduced.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a liquid crystal display device according to an embodiment of the present invention. FIG. 1 is a configuration diagram illustrating a liquid crystal display device according to the present embodiment.
The liquid crystal display device 1 includes a liquid crystal display unit 2 that performs display with a plurality of display pixels arranged in a matrix, and a vertical shift register 3 that sequentially supplies a clock signal corresponding to a plurality of scanning lines shown in a horizontal direction in the drawing. And a horizontal shift register 4 for sequentially supplying clock signals corresponding to a plurality of signal lines shown in the vertical direction in the figure.

Each pixel constituting the liquid crystal display section 2 has a transistor (for example, TFT: Thin Filtration) for driving the liquid crystal LC.
m Transistor) Tr and a capacitor Co for storing signal charges.

The vertical shift register 3 sequentially outputs pulse signals corresponding to one line to a plurality of scanning lines (x1 to x3 in FIG. 1), and turns on the transistor Tr of each pixel in line units. I have to.

The horizontal shift register 4 sequentially outputs gate signals to a plurality of gate lines (a to f in FIG. 1) corresponding to a plurality of signal lines (y1 to y6 in FIG. 1). A display signal corresponding to each pixel is transmitted from the display signal line S in synchronization with the gate signal output from the horizontal shift register 4, and signal charges are accumulated in the capacitor Co via the transistor Tr of the pixel. It has become.

Output signals from the vertical shift register 3 and the horizontal shift register 4 are output in synchronization with a clock signal generated by a clock generator (not shown).

The present embodiment is characterized in that the frequency of the clock signal supplied from the clock generation unit to the vertical shift register 3 and the horizontal shift register 4 is changed according to the resolution displayed on the liquid crystal display unit 2.

That is, in the case where display is performed in units of one pixel of the liquid crystal display unit 2 (hereinafter referred to as “high resolution mode”), one scanning line is sent from the clock generation unit to the vertical shift register 3 and the horizontal shift register 4. And a clock signal having a frequency corresponding to each signal line.

On the other hand, when the display is performed in units of a plurality of pixels of the liquid crystal display unit 2 (hereinafter referred to as “low resolution mode”), the clock generation unit transfers the plurality of pixels to the vertical shift register 3 and the horizontal shift register 4. A clock signal having a frequency corresponding to each of the corresponding scanning lines and signal lines is provided.

FIG. 2 is a diagram showing a configuration of a horizontal shift register corresponding to the high resolution mode and the low resolution mode.
The horizontal shift register 4 includes a horizontal shift register 41 for high resolution and a horizontal shift register 42 for low resolution.
And a multiplexer 43 for making these selections.

This high resolution horizontal shift register 41
A clock signal MCL from a clock generator (not shown)
K is input and the horizontal shift register 42 for low resolution
Is supplied with a clock signal MCLK from a clock generator.

A mode switching signal is input to the multiplexer 43, and the mode switching signal causes a pulse signal (a 'to j' in FIG. 2) output from the horizontal shift register 41 for high resolution or a pulse signal for low resolution to be output. Of the pulse signals (A to E in FIG. 2) output from the horizontal shift register 42 of FIG.

FIG. 3 is a partially enlarged view for explaining the internal circuit of the multiplexer. In this figure, the pulse signals a ′ and b ′ output from the horizontal shift register 41 for high resolution (see FIG. 2) and the horizontal shift register 4 for low resolution are shown.
2 shows a portion that switches the pulse signal A output from the switch 2 (see FIG. 2) by the switches SW1 to SW4 and outputs the gate signals a and b. Note that other combinations of pulse signals have the same circuit configuration.

For example, when a mode switching signal indicating the low resolution mode is input to the multiplexer 43, the internal switches SW1 and SW2 are closed and the switches SW3 and S
W4 opens.

As a result, the pulse signal A output from the horizontal shift register 42 for low resolution shown in FIG. 2 is selected as the gate signals a and b output from the multiplexer 43.

On the other hand, when a mode switching signal indicating the high resolution mode is input to the multiplexer 43, the internal switches SW1, SW2 are opened, and the switches SW3, SW
4 closes.

As a result, the pulse signal a 'output from the horizontal shift register 41 for high resolution shown in FIG. 2 is selected as the gate signal a output from the multiplexer 43, and the gate signal a shown in FIG. The pulse signal b 'output from the horizontal shift register 41 for high resolution is selected.

FIGS. 4 and 5 are timing charts of the gate signal selected by such a mode switching signal. FIG. 4 shows the case of the high resolution mode, and FIG. 5 shows the case of the low resolution mode. In these figures,
Only a to d are shown as gate signals.

That is, in the case of the high resolution mode shown in FIG. 4, the pulse signals a 'and b output from the high resolution horizontal shift register 41 (see FIG. 2) as the gate signals a, b, c and d. ', C', d 'are the multiplexers 43
(See FIG. 2). That is, the gate signals a, b, c, and d are sequentially shifted by one pixel at a time in synchronization with the clock signal MCLK output from the clock generation unit (not shown).

In the low-resolution mode shown in FIG. 5, A output from the low-resolution horizontal shift register 42 (see FIG. 2) as the gate signals a and b is output by the multiplexer 43 (see FIG. 2). The selected signal B is output from the low-resolution horizontal shift register 42 (see FIG. 2) as the gate signals c and d.
Reference). That is, the gate signals a, b, c, and d correspond to the clock signal M in the high-resolution mode.
Clock signal MCLK whose frequency is 1/2 of that of CLK
In synchronism with this, a signal sequentially shifted by two pixels at a time is obtained.

The gate signals a, b,
The gate signals c, d correspond to the gate signals a, b, c, d output from the horizontal shift register 4 shown in FIG. 1, and the gate signals e, f,. , D
Is output following

That is, in the high resolution mode shown in FIG.
A gate signal a from the horizontal shift register 4 shown in FIG.
, b, c, d, e, f,... are sequentially output, and a display signal is output from the display signal line S in synchronization with the output. As a result, each display signal is applied to each pixel along the horizontal direction, and a high-resolution display is performed.

On the other hand, in the low resolution mode shown in FIG. 5, the horizontal shift register 4 shown in FIG. 1 outputs gate signals a and b corresponding to two pixels, gate signals c and d corresponding to the next two pixels. Gate signals e, f,... Corresponding to the two pixels
, The same gate signal is output in order, and the display signal is output from the display signal line S in synchronization with this. As a result, the same display signal is given to each of two pixels along the horizontal direction, and display at low resolution is performed.

As described above, in the present embodiment, by controlling the frequency of the clock signal supplied to the horizontal shift register by the mode switching signal input to the multiplexer 43, the clock having the frequency required for the resolution is used in the low resolution mode. Power consumption can be reduced by using a signal.

For example, when the frequency of the clock signal MCLK applied in the low resolution mode is １ ／ of the frequency of the clock signal MCLK applied in the high resolution mode, if the capacitance C and the voltage V are constant, the power consumption P = CV ²
The power consumption becomes 1/2 in proportion to the frequency f from f.

In the above description, the frequency of the clock signal MCLK applied in the low resolution mode is set to を of the frequency of the clock signal MCLK applied in the high resolution mode.
, But may be 1/3, 1/4,..., 1/3, 3 pixels, 1/4, 4 pixels, etc. The same display signal is displayed by a plurality of pixels. This reduces power consumption by 1 /
3, 1/4,...

In the above description, the case where the frequency of the clock signal in the horizontal shift register 4 is controlled is mainly taken as an example, but the same applies to the case where the frequency of the clock signal in the vertical shift register 3 is controlled.

That is, if necessary, only the frequency of the clock signal in the horizontal shift register 4 may be controlled, only the frequency of the clock signal in the vertical shift register 3 may be controlled, and the frequency of both clock signals may be controlled. You may make it.

Further, the example has been described in which the frequency of the clock signal is switched between the high resolution mode and the low resolution mode as the resolution switching. However, the switching may be performed in more modes.

As an actual example of use, for example, when the information displayed on the liquid crystal display unit 2 includes a photograph or the like, the operator selects the high resolution mode. This allows
Display information such as a photograph is displayed on the liquid crystal display unit 2 with high definition.

On the other hand, when the information displayed on the liquid crystal display unit 2 is composed of characters and the like, the operator selects the low resolution mode. As a result, characters and the like are displayed on the liquid crystal display unit 2 with coarse display contents corresponding to the frequency of the clock signal in the low resolution mode as compared with the high resolution mode. In addition, in the case of characters, etc., there is no problem in use since it can be recognized even if the display is somewhat coarse,
Power consumption can be reduced by selecting the low resolution mode.

[0039]

As described above, the liquid crystal display of the present invention has the following effects. That is, since the frequency of the clock signal generated by the clock generating means is switched according to the resolution displayed by the liquid crystal display means, a clock signal having a frequency matching the display resolution can be generated, and particularly high resolution is not required. In this case, it is possible to reduce wasteful power consumption by using a clock signal having a frequency matching the resolution. By applying the liquid crystal display device of the present invention particularly to a portable computer (portable terminal or the like), it is possible to reduce power consumption according to display contents and extend the driving time by a built-in power supply. .

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a liquid crystal display device according to an embodiment.

FIG. 2 is a diagram illustrating a configuration of a horizontal shift register.

FIG. 3 is a partially enlarged view illustrating an internal circuit of a multiplexer.

FIG. 4 is a timing chart of a gate signal in a high resolution mode.

FIG. 5 is a timing chart of a gate signal in a low resolution mode.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device, 2 ... Liquid crystal display part, 3 ... Vertical shift register, 4 ... Horizontal shift register, 41 ... High resolution horizontal shift register, 42 ... Low resolution horizontal shift register, 43 ... Multiplexer

Claims (2)

[Claims] 1. A liquid crystal display for performing a predetermined display based on signals supplied to a plurality of scanning lines and a plurality of signal lines arranged in a matrix, and generating a clock signal for supplying the signals. A liquid crystal display device comprising: a clock generating means for generating a clock signal; and a switching means for switching a frequency of a clock signal generated by the clock generating means in accordance with a resolution displayed by the liquid crystal display means. 2. The apparatus according to claim 1, wherein the switching unit switches a frequency of a clock signal in a signal supplied to one of the plurality of scanning lines or the plurality of signal lines according to the resolution. The liquid crystal display device as described in the above.