JP2003330430A - Signal line drive circuit and image display device using the circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a signal line drive circuit which gives instructions on timing corresponding to input signals to its signal line drive sections for driving signal lines even though either one of input signals having mutually different signal line resolution is inputted, and has small electric power consumption. <P>SOLUTION: A first data signal line drive circuit 3 is provided with a shift register SRA whose stages correspond to sampling units SU1, SU3, ... that drive odd numbered data lines SL1, SL3, ... and a shift register SRB that is a separate system with respect to the register SRA and whose stages correspond to sampling units SU2, SU4, ... that drive even numbered data lines SL2, SL4, .... During a low resolution mode, only the shift register SRA is operated and timing signals are generated based on the outputs of the stages of the shift register SRA for both the sampling units corresponding to the outputs and the next sampling units. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is capable of driving a plurality of signal lines at operation timings corresponding to respective input signals having different signal line resolutions. The present invention relates to a signal line drive circuit with low power consumption, and an image display device using the signal line drive circuit.

[0002]

2. Description of the Related Art For example, as shown in FIG. 16, a pixel array 10 of an active matrix type image display device 101.
2 are provided for each combination of the plurality of data signal lines SL1, ..., The plurality of scanning signal lines GL1, ..., And the data signal lines SL1 ... And the scanning signal lines GL1. , 1) ... and are provided.

The control circuit 106 controls a video signal D representing an image.
Output AT. Here, the video signal DAT transmits the video data D ... Indicating the display state of each pixel of the image in a time division manner, and the control circuit 106 has a timing for correctly displaying the video signal DAT on the pixel array 102. As a signal, a clock signal SCK and a start pulse signal S
The SP is output to the data signal line drive circuit 103, and the clock signal GCK and the start pulse signal GSP are output to the scan signal line drive circuit 104.

Further, the scanning signal line drive circuit 104 is
The scanning signal lines GL1 ... Of the pixel array 102 are sequentially selected in synchronization with the timing signal such as the clock signal GCK.

Further, the data signal line drive circuit 103 is
It operates in synchronization with a timing signal such as the clock signal SCK to specify the timing corresponding to each data signal line SL1 ... And at each timing the video signal DA.
Sample T. Further, the data signal line drive circuit 103 amplifies each sampling result as necessary and writes it to each data signal line SL1 ....

On the other hand, each pixel PIX (i, j) ... Writes data to the corresponding data signal line SLi while the corresponding scanning signal line GLj is selected (horizontal period). The brightness of each is controlled accordingly. As a result, the pixel array 102 has the video signal DA
The image indicated by T is displayed. Note that i is an arbitrary integer equal to or less than the number of data signal lines SL1, ..., and j is an arbitrary integer equal to or less than the number of scanning signal lines GL1.

For example, as shown in FIG. 17, the first stage L1 of the shift register SR of the data signal line drive circuit 103 is described.
When the start pulse signal SSP is input to the shift register SR, the shift register SR shifts the output of each stage L1 to the next stage L2 at the shift cycle indicated by the clock signal SCK. As a result, as shown in FIG. 18, the output signal waveforms of the latch circuits L1 ... Forming each stage of the shift register SR become waveforms O1 ...

As shown in FIG. 17, the pulse widths of the output signals O1 ... Are adjusted by the waveform shaping circuits WE1.
Buffered by F1 ... And output as timing signals T1 ...

On the other hand, in the data signal line drive circuit 103,
A sampling unit 111 including sampling units SU1 provided corresponding to each of the data signal lines SL1 is provided. Each sampling unit SU
i is the data signal line S during the period indicated by the timing signal Ti.
The video signal DAT is output to Li. As a result, at the timing when the timing signal Ti indicates the output stop,
The sampling result of the video signal DAT is the pixel PIX (i,
j).

Here, the control circuit 106 outputs a clock signal SCK instructing a shift cycle that matches the sampling cycle of the video signal DAT. Therefore,
The data signal line drive circuit 103 can correctly sample the video signal DAT, and the image display device 101 can display the image indicated by the video signal DAT.

By the way, in the video signals DAT having different resolutions, the number of pixels in the vertical and horizontal directions forming one screen is different from each other. Therefore, the number of scanning periods to be provided when displaying one screen of the video signal DAT and the number of sampling timings per scanning period are also different from each other.

Further, in order to display the image of each video signal DAT in the same size, it is necessary to change the distance between adjacent pixels (distance between the centers of pixels). However, in the image display device 101, a CRT (Cathode-Ray Tub) is used.
Unlike e), the distance between the pixels PIX ... Is fixed at the distance between the data signal lines SL ... Or the distance between the scanning signal lines GL. Therefore, the actual signal line resolution can be changed. Can not.

Therefore, the video signal DA whose signal line resolution is lower than the actual signal line resolution of the image display device 101.
When T is input, a plurality of adjacent pixels PIX ...
An image display device 101a is also used in which the apparent signal line resolution can be matched with the signal line resolution of the video signal DAT by writing the same value data.

The case of adjusting the horizontal resolution will be described as an example. For example, as shown in FIG. 19, in the data signal line drive circuit 103a of the image display device 101a,
In the low resolution mode in which the low resolution video signal DAT is input to the shift register SR, each odd number stage (for example, L
Switches AS1 ... Which connect the output of 1) and the input of the next odd-numbered stage (for example, L3) are provided. In addition, before and after each even stage (for example, L2), in the low resolution mode, the previous stage (for example, L1) and the next stage (for example, L3)
Therefore, switches AS2 ... Which disconnect the even-numbered stages are provided. In addition, odd-numbered waveform shaping circuits WE1 and W
The outputs of E3 ... Are provided with switches AS3 ... Which are connected to the next waveform shaping circuits WE2 ... In the low resolution mode.

The data signal line drive circuit 103a having the above structure
Operates in the same manner as the data signal line drive circuit 103 shown in FIG. 17 in the high resolution mode to operate the data signal lines SL.
The video signal DAT sampled at different timings is written in i. Thereby, the image display device 1
01a displays the video signal DAT with a horizontal resolution corresponding to the number of data signal lines SLi.

On the other hand, the horizontal resolution is 1 in the high resolution mode.
In the low resolution mode in which the / 2 video signal DAT is input, the control circuit 106 outputs a clock signal SCK instructing a shift cycle that matches the sampling cycle of the low resolution video signal DAT. Further, in the data signal line drive circuit 103a, every other latch circuit L1 ... Of the shift register SR is used.

As a result, the output waveforms O1, O3, ... Of the odd-numbered stages of the shift register SR are waveforms with timings shifted by the sampling period, as shown in FIG.
Further, since the switch AS3 is conducting in the low resolution mode, the odd-numbered waveform shaping circuits WE1 and WE3 are
... are the sampling units SU corresponding to each
1, SU3 ..., and the next sampling unit SU2, S
U4 ... And connected. Therefore, the adjacent sampling units (for example, SU1 and SU2) have timing signals (for example, T1 and T2) at the same timing.
2) is given, and both of them receive the video signal D at the same timing.
Sample AT. As a result, the data signal line drive circuit 103a can drive the data signal lines (for example, SL1 and SL2) adjacent to each other as one set, and write the data of the same value to each.

As a result, the apparent signal line resolution (horizontal resolution) of the image display device 101a becomes 1/2 of the actual signal line resolution, and can be matched with the signal line resolution of the video signal DAT. Therefore, even when the video signal DAT having a signal line resolution lower than the actual signal line resolution is input, an image can be displayed with high quality.

[0019]

However, in the above conventional configuration, the output signal O1 from the same shift register SR is used in both the high resolution mode and the low resolution mode.
Since the timing signals T1 ... Are generated based on ..., There is a problem that it is difficult to sufficiently reduce power consumption.

Further, for example, in addition to image data (video data) of high-quality image display such as multi-gradation, color display, high frame frequency, etc., binary data is displayed, and signal line drive for high-quality image display is performed. The circuit alone may cause an unnecessary increase in power consumption.

The present invention has been made in view of the above problems, and an object thereof is, for example, a sampling unit SU or the like regardless of which of input signals having a plurality of signal line resolutions is input. In order to realize a signal line drive circuit that consumes less power, and an image display device that uses the signal line drive unit that drives each signal line, even if the timing according to an input signal can be instructed. is there.

[0022]

In order to solve the above-mentioned problems, a signal line drive circuit according to the present invention applies an input signal to a signal line drive section provided corresponding to each of a plurality of signal lines. A first signal line drive circuit provided with a scanning unit that outputs a timing signal indicating a timing for operating in accordance with the above; the scanning unit includes first and second shift registers of different systems, The control means operates the first and second shift registers in the high resolution mode, and suspends the first shift register in the low resolution mode in which an input signal having a signal line resolution lower than that of the high resolution mode is applied. And a second signal line drive circuit that shares at least a part of the plurality of signal lines with the first signal line drive circuit. There. The first and second shift registers may be single-system shift registers or plural-system shift registers.

In the above structure, in the high resolution mode, the control means operates both the first and second shift registers, so that the total number of stages of the operating shift registers is larger than that in the low resolution mode. ing. Therefore, the signal line resolution of the input signal is higher than that in the low resolution mode. For example, the timing for sampling each data included in the input signal or switching the line corresponding to the data included in the input signal may be changed. Although the number of timings to instruct each signal line driving unit when the signal line driving unit driving each signal line operates according to the input signal, such as the timing for It is possible to output a timing signal indicating the operation timing of the signal line driving unit without any trouble.

On the other hand, in the low resolution mode, the control means suspends the first shift register and operates the second shift register. In this case, the total number of stages of the shift register in operation is smaller than that in the high resolution mode. However, since the signal line resolution of the input signal is also lower than that in the high resolution mode, the number of timings to be instructed to each signal line driving section is also small. Therefore, the scanning unit can output the timing signal indicating the above-mentioned timing to each signal line driving unit without any trouble, even though the first shift register is at rest.

With the above arrangement, in the low resolution mode, the first
The shift register is not operating. Further, since the first and second shift registers are shift registers of different systems from each other, a configuration of the conventional technique, that is, a shift register of a single system is provided, and in the low resolution mode, some stages are skipped to generate a pulse. The operation speed required for the second shift register can be suppressed more than that of the configuration in which the shift is performed. Therefore, the second shift register can be configured by a circuit with lower power consumption.

As a result, even if an input signal with a high signal line resolution or an input signal with a low signal line resolution is input, power consumption is reduced despite the fact that the signal line drive section can be instructed to operate correctly. A low signal line drive circuit can be realized.

The number of stages of the second shift register may be any number as long as each operation timing corresponding to the low resolution input signal can be specified by each stage output of the second shift register. The number of stages of the first shift register is
Any number of stages may be used as long as each operation timing corresponding to the high-resolution input signal can be specified by each stage output of the first and second shift registers. However, when it is desired to reduce the number of stages, the total number of stages of the second shift register is set to be the same as the signal line resolution of the low-resolution input signal, and the total number of stages of the first shift register is set to the high resolution. It is desirable that the value is set to a value obtained by subtracting the low resolution signal line resolution from the signal line resolution of the input signal.

Further, by driving the signal lines by the second signal line drive circuit having at least a part of the plurality of signal lines in common, for example, an image display different in display quality from the display image by the first signal line drive circuit is displayed. It can be carried out.

In addition to the above configuration, the signal line drive section is a sampling circuit that samples the input signal at the timing indicated by the timing signal, and the signal line drive circuit operates as a data signal line drive circuit. It may be configured to.

According to this structure, it is possible to realize a data signal line drive circuit with low power consumption, although both an input signal with a high signal line resolution and an input signal with a low signal line resolution can be correctly sampled.

In addition to the above structure, the scanning section is
In the high resolution mode, a signal is transmitted from each stage of the second shift register to a corresponding sampling circuit, and a signal is transmitted from each stage of the first shift register to a corresponding sampling circuit. At the same time, in the low resolution mode, a signal path is provided so that a signal is transmitted from each stage of the second shift register to the corresponding sampling circuit and the sampling circuit corresponding to each stage of the first shift register. It may have a switching means for switching.

According to this structure, in the low resolution mode, a signal path is formed from each stage of the second shift register to the sampling circuit corresponding to each stage of the first and second shift registers, and the second shift register is formed. A plurality of sampling circuits sample the input signal based on the timing signal from the first stage. As a result, in the low resolution mode, it is possible to write the same value data to the data signal lines corresponding to these sampling circuits. Therefore, the apparent signal line resolution of the data signal line driven by the data signal line drive circuit can be adjusted according to the resolution of the input signal.

In addition to the above-mentioned constitutions, the first and second shift registers operate in synchronization with clock signals transmitted by different clock signal lines, and
In the low resolution mode, the clock signal supply to the first shift register is stopped, and in the high resolution mode, the first shift register is stopped.
Further, it is desirable to include clock signal control means for supplying clock signals indicating different shift timings to the second shift register and the second shift register, respectively.

In the structure, in the high resolution mode, clock signals indicating different shift timings are supplied to the first and second shift registers, respectively. As a result, each stage of the first and second shift registers can output signals at different timings.

On the other hand, in the low resolution mode, the first shift register is deactivated and the clock signal supply to the first shift register is stopped. Therefore, in the low resolution mode, it is possible to reduce the power consumption in the circuit that generates the clock signal to the first shift register and reduce the power consumption of the entire system including the signal line drive circuit and the clock signal control means.

Even in the low resolution mode, the second
Since the clock signal to the shift register is supplied by a clock signal line different from the clock signal to the first shift register, the signal line driving circuit does not cause any trouble and each signal is operated at the operation timing corresponding to the input signal. Can drive lines.

In order to solve the above-mentioned problems, an image display device according to the present invention is an image display device using any one of the above signal line drive circuits, wherein a plurality of data signal lines and Arranged to intersect the data signal line,
A plurality of scanning signal lines, pixels arranged in a matrix corresponding to the combination of the data signal lines and the scanning signal lines, a scanning signal line driving circuit for driving the scanning signal lines, and each of the data signal lines. A signal according to the sampling result of the sampling circuit provided correspondingly, and a data signal line drive circuit for outputting to each of the data signal lines,
The data signal line drive circuit is the first signal line drive circuit, and the second signal line drive circuit shares at least a part of the plurality of data signal lines with the first signal line drive circuit. Is characterized by.

In the signal line drive circuit having the above configuration, each signal line drive section drives each signal line at the correct operation timing regardless of whether an input signal of high signal line resolution or an input signal of low signal line resolution is input. Despite being able to drive
Low power consumption. Therefore, by using the signal line drive circuit as the data signal line drive circuit, it is possible to correctly display both a high-resolution video signal and a low-resolution video signal, but an image display device with low power consumption. Can be realized.

Further, by driving the signal line by the second signal line drive circuit having at least a part of the plurality of signal lines in common, for example, an image display different in display quality from the display image by the first signal line drive circuit is displayed. By doing so, an image display device with lower power consumption can be realized.

Further, when reduction in manufacturing cost is required, it is desirable that the pixel, the data signal line drive circuit and the scanning signal line drive circuit are formed on the same substrate in addition to the above configuration.

According to this structure, since the data signal line drive circuit and the scanning signal line drive circuit are formed on the same substrate as the pixel, after forming each on a different substrate,
The manufacturing cost and the mounting cost of each drive circuit can be reduced as compared with the case where each board is connected.

Further, in addition to the above structure, the active elements forming the pixels, the data signal line drive circuit and the scanning signal line drive circuit may be polycrystalline silicon thin film transistors.

According to this structure, the size of the substrate can be increased as compared with the case where the active element is formed of a single crystal silicon transistor. As a result, it is possible to manufacture an image display device having a wide screen as well as low power consumption at low cost.

In addition to the above structure, the active element may be formed on the glass substrate by a process at 600 ° C. or lower. According to this configuration, the active element is 600
Since it is manufactured by a process of ℃ or less, the active element can be formed on the glass substrate. As a result, it is possible to manufacture an image display device having a wide screen as well as low power consumption at low cost.

[0045]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] The following will describe one embodiment of the present invention with reference to FIGS. 1 to 10. That is, the image display device 1 according to the present embodiment is an image display device compatible with video sources having various resolutions, and the first image display device according to each resolution mode.
By controlling the drive section of the data signal line drive circuit,
The image display device is capable of reducing power consumption, although it has a variable resolution function and is capable of high-quality display.

Furthermore, such multi-gradation, color display,
Power consumption required for displaying binary data is reduced by providing a second data signal line drive circuit for displaying binary data in addition to a first data signal line drive circuit for displaying high quality images such as high frame frequencies. In addition, the image synthesizing unit for synthesizing the high-quality image data and the binary data in advance is unnecessary.

As shown in FIG. 2, the image display device 1 has pixels PIX (1,1) to PIX arranged in a matrix.
a pixel array 2 having (n, m), a first data signal line driving circuit 3 for driving the data signal lines SL1 to SLn of the pixel array 2, and a scanning signal for driving the scanning signal lines GL1 to GLm of the pixel array 2. A line drive circuit 4, a power supply circuit 5 for supplying electric power to both drive circuits 3 and 4, and a control circuit (clock signal control means) 6 for supplying a control signal to both drive circuits 3 and 4 are provided. The first data signal line drive circuit 3
Corresponds to the first signal line drive circuit described in the claims, and each of the data signal lines SL1 to SLn corresponds to a signal line.

Further, the image display device 1 is provided with a second data signal line drive circuit 3 '. The second data signal line drive circuit 3 ′ is the data signal line SL of the pixel array 2.
1 to SLn, and data signal line SL1
To SLn are commonly connected to the first data signal line drive circuit 3 and the second data signal line drive circuit 3 '. In addition,
The second data signal line drive circuit 3'corresponds to the second signal line drive circuit described in the claims. Further, in FIG. 2, all of the data signal lines SL1 to SLn are connected to the second data signal line drive circuit 3 ', but if display is not performed in the entire display area, the data signal lines S
A part of L1 to SLn may be connected to the second data signal line drive circuit 3 ′.

Before describing the detailed structure of the first data signal line drive circuit 3, the general structure and operation of the image display device 1 will be described below. Also, for convenience of explanation,
For example, like the i-th data signal line SLi, when a position is required to be specified, reference is made by attaching a numeral or an alphabetic character indicating the position. Refers by omitting the character indicating the position.

A plurality of pixel arrays 2 (in this case,
(n lines) data signal lines SL1 to SLn and a plurality of (in this case, m) scanning signal lines GL1 to GLm intersecting the respective data signal lines SL1 to SLn, and 1 to n. , And a random integer from 1 to m are j, a pixel PIX (i, j) is provided for each combination of the data signal line SLi and the scanning signal line GLj.

In the case of this embodiment, each pixel PIX (i, j)
Is two adjacent data signal lines SL (i-1) .SLi
And the adjacent two scanning signal lines GL (j-1) .GLj.

As an example, when the image display device 1 is a liquid crystal display device, the pixel PIX (i, j) is used.
Is a field effect transistor SW (i, whose gate is connected to the scanning signal line GLj and whose drain is connected to the data signal line SLi, as a switching element, for example, as shown in FIG.
j) and a pixel capacitance Cp (i, j) whose one electrode is connected to the source of the field effect transistor SW (i, j). The other end of the pixel capacitance Cp (i, j) is
It is connected to a common electrode line common to IX .... The pixel capacitance Cp (i, j) is composed of a liquid crystal capacitance CL (i, j) and an auxiliary capacitance Cs (i, j) added as needed.

In the pixel PIX (i, j), when the scanning signal line GLj is selected, the field effect transistor SW
(i, j) becomes conductive, and the voltage applied to the data signal line SLi is applied to the pixel capacitance Cp (i, j). On the other hand, while the selection period of the scanning signal line GLj ends and the field effect transistor SW (i, j) is cut off, the pixel capacitance Cp (i, j)
Keeps the voltage at the time of interruption. Here, the transmittance or reflectance of the liquid crystal changes depending on the voltage applied to the liquid crystal capacitance CL (i, j). Therefore, the scanning signal line GLj
Is selected and a voltage corresponding to the video data D to the pixel PIX (i, j) is applied to the data signal line SLi, the display state of the pixel PIX (i, j) is adjusted to the video data D. Can be changed.

Although the liquid crystal has been described above as an example, the pixel PIX (i, j) has the data signal line SL while the signal indicating selection is applied to the scanning signal line GLj.
If the brightness of the pixel PIX (i, j) can be adjusted according to the value of the signal applied to i, it is possible to use a pixel having another configuration regardless of whether or not it is self-luminous.

In the above structure, the scanning signal line drive circuit 4 shown in FIG. 2 outputs a signal such as a voltage signal indicating whether or not it is in the selection period to each of the scanning signal lines GL1 to GLm. Further, the scanning signal line drive circuit 4 changes the scanning signal line GLj that outputs a signal indicating the selection period based on a timing signal such as a clock signal GCK or a start pulse signal GSP provided from the control circuit 6, for example. There is. Thereby, the scanning signal lines GL1 to GLm are sequentially selected at a predetermined timing.

Further, the first data signal line drive circuit 3 is
Each pixel PI input in time division as the video signal DAT
The video data D ... to X ... are extracted by sampling at a predetermined timing. Further, the first data signal line drive circuit 3 includes pixels PIX (1, j) to PIX (1, j) corresponding to the scan signal line GLj selected by the scan signal line drive circuit 4.
An output signal corresponding to the video data D ... Is output to PIX (n, j) via each of the data signal lines SL1 to SLn.

The video signal DAT has one of a plurality of predetermined resolutions, and in this embodiment,
Resolution switching signal MC indicating which resolution
At the same time, it is input from the control circuit 6. Further, the first data signal line drive circuit 3 is inputted from the control circuit 6,
The sampling timing and the output timing of the output signal are determined based on timing signals such as the clock signal SCK and the start pulse signal SSP.

On the other hand, each pixel PIX (1, j) to PIX (n, j)
Adjusts the luminance and the transmittance at the time of light emission according to the output signals given to the data signal lines SL1 to SLn corresponding to itself while the scanning signal line GLj corresponding to itself is selected. Determine the brightness of yourself.

Here, the scanning signal line drive circuit 4 sequentially selects the scanning signal lines GL1 to GLm. Therefore,
All pixels PIX (1,1) to PIX (n, m) of the pixel array 2 are
The brightness indicated by the video data D for each can be set, and the image displayed on the pixel array 2 can be updated.

In the following, as an example of a plurality of resolutions, one of high resolution and low resolution is supplied to the first data signal line drive circuit 3, and when the resolution is low, when the signal line resolution is high resolution. A case where half of the video signal DAT is input will be described.

In this case, the first data signal line drive circuit 3
Is 1 when a high resolution video signal DAT is applied.
An output signal corresponding to one video data D is output to one data signal line SLi. In the case of low resolution, an output signal corresponding to one video data D is output to two adjacent data signal lines SLi.SL (i Output to (+1). As a result, the apparent horizontal resolution (signal line resolution) can be matched with the horizontal resolution of the video signal DAT. So, for example,
The maximum physical display resolution is, for example, UXGA (Ultra-
eXtended Graphics Array) image display device 1,
When the horizontal resolution of the input video signal DAT is smaller than the maximum physical display resolution in the horizontal direction of the image display device 1, such as when displaying the video represented by the SVGA (SuperVideo Graphics Array) video signal DAT. Even if it is, the image can be displayed in high definition.

The first data signal line drive circuit 3 shown in FIG.
, The timing signals T1 to Tn corresponding to the respective data signal lines SL1 to SLn
, Sampling units (signal line drive unit; sampling circuit) SU1 to S for sampling the video signal DAT
The sampling unit 11 made of Un is provided. In the present embodiment, each sampling unit SUi is provided between the signal line that transmits the video signal DAT and the corresponding data signal line SLi, and the timing signal Ti
It is realized as an analog switch that opens and closes according to i.

Further, in order to reduce power consumption, the first data signal line drive circuit 3 according to the present embodiment includes a scanning circuit section (scanning section) 12 including shift registers SRA and SRB of independent systems. And a switching unit (switching means) 13 for generating the timing signals T1 to Tn based on the output signals O1 to On of the scanning circuit unit 12 and the resolution switching signal MC, and the resolution switching signal MC. The operation of the shift register SRB /
And a register control unit (control means) 14 for controlling non-operation. In the case of FIG. 1, the shift register SRA corresponds to the second shift register described in the claims and the shift register SRB corresponds to the first shift register.

The shift register SRA is a shift register in which p latch circuits LA1 to LAp are connected in series, and the output signal is output as an output of each latch circuit LA1 to LAp (each stage output of the shift register SRA). O1
.. of the output signals O1, O3, ... Note that p is n / 2 when n is even and (n + 1) / 2 when n is odd.

Further, the shift register SRB is a shift register in which q latch circuits LB1 to LBq are connected in cascade, and the above-mentioned outputs are output as the outputs of the latch circuits LB1 to LBq (each stage output of the shift register SRB). Signal O
Even-numbered output signals O2, O4, ... Of 1 to On can be output. Note that q is n / 2 when n is even and (n-1) / 2 when odd.

Further, the clock signal SCKA is applied from the control circuit 6 shown in FIG. 2 to each stage (latch circuits LA1 to LAp) of the shift register SRA, and each stage of the shift register SRB (latch circuit LB1). ~ LB
The clock signal SCKB is applied from q to the control circuit 6.

The control circuit 6 applies start pulse signals SSPA and SSPB to the first stage (latch circuit LA1) of the shift register SRA and the first stage (latch circuit LB1) of the shift register SRB, respectively.

Here, in the above configuration, two systems of shift registers SRA and SRB are provided.
Each data signal line SL ... Can be shared. Therefore,
Compared with the conventional technique in which the scanning circuit unit 112 is composed of a single-system shift register SR, the clock signal SCKA
・ The maximum drive frequency of SCKB is halved. Along with this, each shift register SRA / SRB is realized by a circuit whose operation speed is slower than that of the prior art. In addition,
In this embodiment, two systems of shift registers SRA and SR
Although B is provided, the total number of both stages is the number of data signal lines SL ... (N stages) as in the case of a single system. Therefore, two systems of shift registers SRA / S
Despite the provision of the RB, the circuit scale does not increase due to the increase in the number of stages. As a result, the circuit scale of the scanning circuit unit 12 can be reduced and the power required for driving can be reduced.

On the other hand, when the resolution switching signal MC indicates high resolution, the switching section 13 outputs the timing signals T1 to Tn at the timings indicated by the respective outputs O1 to On of the scanning circuit section 12. In the case of low resolution, if k is an integer less than or equal to p, timing signals T (2 * k-1) and T (2 * k) at the timing indicated by the output O (2 * k-1)
By generating the output O of each stage of the shift register SRA.
.. can output the timing signals T1 to Tn.

Specifically, the switching unit 13 is divided into p blocks B1 to Bp, and each block B is divided into blocks B1 to Bp.
k is the kth stage of the shift register SRA (latch circuit L
Signal path from Ak) to the sampling unit SU (2 * k-1) and the kth stage of the shift register SRB (latch circuit L
A signal path from Bk) to the sampling unit SU (2 * k). Further, each block Bk has the following features when the resolution switching signal MC indicates a low resolution.
From the latch circuit LBk to the sampling unit SU (2
A switch ASOk that cuts off the signal path to * k), and a switch ASNk that connects the signal path from the latch circuit LAk to the sampling unit SU (2 * k) when low resolution is indicated. Is equipped with. In addition,
When n is an odd number, in the final block Bp, the signal path from the shift register SRB to the sampling unit 11 and the switches ASNp and ASOp are unnecessary.

Further, in this embodiment, in order to improve the accuracy of sampling timing by each sampling unit SU (2 * k-1) .multidot.SU (2 * k), each block Bk
And sampling units SU (2 * k
-1) ・ Wave shaping that adjusts the pulse width of the signal from the block Bk to each sampling unit SU (2 * k-1) ・ SU (2 * k) between it and SU (2 * k). Circuit WE (2 * k
-1) ・ WE (2 * k) and each waveform shaping circuit WE (2 * k-1) ・ W
Buffer circuits BF (2 * k-1) and BF (2 * k) for buffering the output signals of E (2 * k) are provided.

In this case, the switch ASOk is provided between the latch circuit LBk and the waveform shaping circuit WE (2 * k). Also, one end of the switch ASNk is
It is connected to the latch circuit LAk and the other end is connected to the switch A.
It is connected to the connection point between SOk and the waveform shaping circuit WE (2 * k).

Both switches ASNk and ASOk
Can be realized, for example, as a CMOS type analog switch composed of n-ch and pch transistors as shown in FIGS. For example, when the resolution switching signal MC is at a low level when indicating a low resolution, the positive-phase signal MC is input to the gate of the p-ch transistor forming the switch ASNk, and n-
A signal / MC having a reverse phase of the signal MC is input to the gate of the ch transistor. Similarly, switch ASOk
The signal MS in the positive phase is input to the gate of the n-ch transistor constituting the above, and the opposite phase signal / MC is input to the gate of the p-ch transistor. The signal / MC having the opposite phase is generated, for example, by inverting the signal MC with an inverter.

In the above structure, a high resolution video signal D
When AT is input, the control circuit 6 controls the resolution switching signal MC (for example,
High level) to the first data signal line drive circuit 3.

In response to this, in the switching section 13 of the first data signal line drive circuit 3, the switches ASO1 to AS are
The switch ASN1 to ASNp is cut off while Op is conducted. In this state, k of the shift register SRA
From the second stage (latch circuit LAk) to the sampling unit S
Signal path to U (2 * k-1) and k of shift register SRB
From the second stage (latch circuit LBk) to the sampling unit S
The signal path to U (2 * k) is enabled, and the data signal lines SL ... Are alternately assigned to the output of the shift register SRA and the output of the shift register SRB.

When the resolution switching signal MC indicates high resolution, the register control section 14 operates the shift register SRB by, for example, supplying power to the shift register SRB. On the other hand, the control circuit 6
In order to drive both shift registers SRA and SRB, clock signals SCKA and SCKB whose shift timing frequency is half the applied frequency of the video data D are output. At this time, the control circuit 6 controls the data signal lines SL ...
In order to write individual data (video data D to each pixel PIX) temporally, the phase of the clock signal SCKA and the phase of the clock signal SCKB are the shift timing that the clock signal SCKA instructs the shift register SRA. In the meantime, the clock signal SCKB is set so that the shift timing instructing the shift register SRB is entered.

In this embodiment, both shift registers SRA are
The SRB is configured to shift on both edges of the clock signals SCKA and SRB. Therefore, the frequency of both clock signals SCKA / SRB is
Is 1/4 of the applied frequency and the phase difference between the clock signals SCKA and SCKB is set to 90 degrees.

Further, the control circuit 6 includes a shift register S
The phase of the first-stage output O1 of RA is advanced by a phase difference (90 degrees of the clock signal SCKA in this example) from the first-stage output O2 of the shift register SRB. Both start pulse signals SSPA and SSPB are sent to the first data signal line drive circuit 3
To enter.

As a result, as shown by O1 in FIG. 6, the waveform of each output Oi of the scanning circuit section 12 is the same as the previous output Oi.
The waveform has a timing that is delayed from the phase difference (i-1) by the phase difference (90 degrees of the clock signal SCKA in this example). Further, as described above, the resolution switching signal MC
Indicates a high resolution, each block Bk has a signal path from the k-th stage (latch circuit LAk) of the shift register SRA to the sampling unit SU (2 * k-1) and the k-th stage of the shift register SRB. The signal path from the eye (latch circuit LBk) to the sampling unit SU (2 * k) is valid. Therefore, each of the outputs Oi has its pulse width adjusted by the corresponding waveform shaping circuit WEi, is buffered by the buffer circuit BFi, and is output to the sampling unit SUi.

Here, the waveform shaping circuit WEi and the buffer circuit BFi only adjust the pulse width and buffer. Therefore, the buffer circuit B
The phase difference between the output signal Ti of Fi and the output signal T (i-1) of the previous buffer circuit BF (i-1) is the same as the phase difference of the scanning circuit unit 12 (in this example, the clock Signal SCK
The timing is delayed by 90 degrees of A). As a result, the buffer circuits BF1 to BFn are connected to the sampling unit 1
1 can output timing signals T1 to Tn indicating different sampling timings.

Therefore, the apparent signal line resolution of the sampling section 11 is n as in the actual signal line resolution.
Therefore, the sampling units SU1 to SUn of the sampling unit 11 can sample the video signal DAT at different timings. Accordingly, from the video signal DAT having the signal line resolution n, the video data D (1, j) to D
(n, j) is sampled, and while the scanning signal line GLj is selected, each data signal line SL1 to SLn is selected.
The sampling result (D (1, j) to D (n, j)) can be output. In this case, since each sampling unit SU is individually driven temporally, the horizontal resolution of the image displayed on the image display device 1 is the same as the actual signal line resolution of the first data signal line drive circuit 3. The number of signal lines SL, that is, n.

In the present embodiment, the case of dot-sequential driving is taken as an example, and each sampling unit SUi of the sampling section 11 is turned on during the period indicated by the timing signal Ti. Therefore, the time when the timing signal Ti changes to a value indicating interruption is the sampling timing, and the value of the video signal DAT (video data D) at that time is the sampling result, which is the data signal line S.
It is output to Li.

On the other hand, when the low-resolution video signal DAT is input, the control circuit 6, as shown in FIG. 7, the resolution switching signal MC indicating the low resolution (for example, low level).
Is output to the first data signal line drive circuit 3.

In response to this, in the switching unit 13,
The switches ASO1 to ASOp are cut off, and the switches ASN1 to ASNp are turned on. In this state, the sampling units SU (2 * k-1) and SU (2 *) are transferred from the k-th stage (latch circuit LAk) of the shift register SRA.
The signal path to k) becomes effective, and the adjacent data signal lines SL and SL are assigned to the shift register SRA as one set.

Further, the control circuit 6 includes a shift register S
The start pulse signal SSPB to the RB is fixed to the low level, and the shift register SRB is made inoperative. In addition, the register control unit 14 controls the resolution switching signal MC
Indicates a low resolution, the operation of the shift register SRB is stopped by, for example, cutting off the power supply to the shift register SRB. As a result, the power consumption of the shift register SRB in the non-operating state can be reduced.

Further, the control circuit 6 uses the shift register SR
The clock signal SCKB to B is fixed at a constant potential.
Thereby, for example, the clock signal S such as the control circuit 6 is generated.
The power consumption of the circuit that generates CK can also be reduced.

On the other hand, the control circuit 6 uses the shift register SR
To drive A, the clock signal SCKA having the same shift timing frequency as the applied frequency of the video data D is output, and the start pulse signal SSPA is output. In this embodiment, since the shift is performed at both edges, the frequency of the clock signal SCKA is 1/2 of the applied frequency of the video data D.

As a result, as shown by O1 in FIG. 7, the waveform of each output signal O (2 * k-1) output by each latch circuit LAk of the shift register SRA of the scanning circuit section 12 is as follows.
The waveform of the timing delayed by the shift interval of the shift register SRA (in this example, 180 degrees each in the clock signal SCKA) from the output O signal (2 * k-3) of the latch circuit LA (k-1) in the previous stage. Become. The shift register SRB is
Since the operation is stopped, the outputs O2, O4 ... Of each stage of the shift register SRB are fixed values (low level in the example of FIG. 7).

Further, as described above, when the resolution switching signal MC indicates low resolution, each block Bk includes the kth stage (latch circuit LA) of the shift register SRA.
k) to sampling units SU (2 * k-1) and SU
The signal path to (2 * k) is valid. Each output O above
(2 * k-1) is a sampling unit SU (as a timing signal T (2 * k-1) via a waveform shaping circuit WE (2 * k-1) and a buffer circuit BF (2 * k-1). 2 * k-1), the waveform shaping circuit WE (2 * k) and the buffer circuit B
It is given to the sampling unit SU (2 * k) as a timing signal T (2 * k) via F (2 * k).

Here, also in this case, each waveform shaping circuit WE
i and the buffer circuit BFi adjust the pulse width,
It is only buffering. Therefore, the phase difference between the output signal T (2 * k-1) of the buffer circuit BF (2 * k-1) and the output signal T (2 * k-3) of the buffer circuit BF (2 * k-3). Is the output signal O (2 * k-1) of the shift register SRA
Like the phase difference with (2 * k-3), the shift interval of the shift register SRA (in this example, 1 of the clock signal SCKA
80 degrees). In addition, the sampling units SU (2 * k-1) and SU (2 * k) adjacent to each other have a timing signal T for instructing sampling at the same timing.
(2 * k-1) ・ T (2 * k) is input.

Therefore, the apparent signal line resolution of the sampling section 11 is p (n / 2 or (n + 1) /
2), among the sampling units SU1 to SUn of the sampling unit 11, the pairs of adjacent sampling units SU (2 * k-1) and SU (2 * k) output the video signal DAT at different timings. Sampling and adjoining sampling unit SU (2 * k-1) S
U (2 * k) samples the video signal DAT at the same timing. As a result, the video signal D having the signal line resolution p
The video data D (1, j) to D (p, j) are sampled from the AT, and the sampling result (D (1) is sent to each of the data signal lines SL1 to SLn while the scanning signal line GLj is selected. , j) to D (p, j)) can be output.

In the above configuration, each sampling unit S
In order to generate timing signals T1 to Tn to U1 to SUn, two independent shift registers SRA are provided.
-SRB is provided. Further, at the time of low resolution, the output of each stage of one shift register SRA is transmitted to a plurality of sampling units SU per stage, so that each sampling unit SU1 to SUn is based on only the output of one shift register SRA. Timing signals T1 to Tn to the other shift register S
Stop RB operation.

Therefore, compared with the case where the timing signals T1 to Tn are generated by the single-system shift register SR as in the prior art, regardless of the signal line resolution,
Drive frequency of each shift register SRA / SRB is 1/2
In addition, the number of stages of the shift register SRA that operates in the case of low resolution can be reduced to 1/2. Further, in the configuration of the present embodiment, even in the case of high resolution, the drive frequency of the shift register SRA operating at low resolution is suppressed to 1/2 of the signal line resolution. Therefore, the latch circuit LA forming each stage of the shift register SRA is
1 to LAp have the maximum driving frequency reduced to 1/2 and can be realized by a slower circuit.

As a result, the power consumption of the first data signal line drive circuit 3 is reduced to, for example, 1 /
It can be significantly reduced, such as 4 or less. Further, since the maximum driving frequency is low, the circuit scale and power consumption can be reduced.

Further, in the present embodiment, when the low-resolution video signal DAT is input, the power supply to the shift register SRB is stopped, so the power consumption of the shift register SRB in the inoperative state is reduced. it can. Further, in the present embodiment, when the resolution is low, the clock signal SCKB
Since the potential of is kept constant and does not fluctuate in the clock cycle, the power consumption can be reduced even in the external circuit (for example, the control circuit 6) that generates the clock signal SCKB.

In the above, the low resolution video signal DA
Although the case where the shift register SRA is used when T is input has been described as an example, the shift register SRB may be used as in the first data signal line drive circuit 3a illustrated in FIG. In this case, the shift register SRA
Corresponds to the first shift register described in the claims, and the shift register SRB corresponds to the second shift register.

In this configuration, in each block Bk of the switching unit 13a, the switch ASOk that is cut off when the resolution switching signal MC indicates low resolution is
The shift register SRA is provided on the signal path from the kth stage latch circuit LAk to the sampling unit SU (2 * k-1). Also, the switch ASNk connects the signal path from the latch circuit LBk of the kth stage of the shift register SRB and the signal path to the sampling unit SU (2 * k−1) when the resolution is low. Further, the register control unit 14 replaces the operation / non-operation of the shift register SRB with the shift register S depending on whether the resolution is high or not.
Controls whether to operate RA.

When the resolution is low, the shift register SRA
Regardless of which of the SRBs operates, according to the first data signal line drive circuit 3 (3a) having the above-described configuration, when the signal line resolution is high, the two systems of shift registers SRA.
By using the SRB, while suppressing the drive frequency of each shift register SRA / SRB to a low level, a high-resolution video signal DAT
Can be sampled normally. Further, the low-resolution video signal DAT is sampled using one of the small-scale and low-power-consumption shift registers SRA and SRB optimized for the low driving frequency. As a result, the first data signal line drive capable of driving each of the data signal lines SL1 to SLn with low power consumption, although the apparent signal line resolution can be changed according to the signal line resolution of the video signal DAT. The circuit 3 (3a) can be realized.

Here, the second data signal line drive circuit 3'will be described. The second data signal line drive circuit 3'includes
From the control circuit 6, the transfer instruction signal TRF, the lighting potential V
W, the non-lighting potential VB, and the display binary data signal (digital data) DD are input. Although not shown, the clock signal SC to the first data signal line drive circuit 3
A clock signal synchronized with KA and SSPA can be input as a timing signal from the control circuit 6 to perform display in synchronization with it.

The second data signal line drive circuit 3'includes a shift register that outputs a sampling signal based on the input timing signal and a binary data signal DD that is separately input according to the output from the shift register. A data holding unit that samples and holds the data, a data switching unit that switches the binary data potential of the lighting potential VW and the non-lighting potential VB according to the binary data signal held by the data holding unit, and the data thereof. The transfer instruction signal TRF is provided between the output signal of the switching unit and the data signal lines SL1 to SLn.
And an output control unit that controls the output of the data switching unit.

With such a configuration, in the case of normally black, when the lighting potential VW is selected by the data switching unit and the transfer instruction signal TRF is input, the output control unit performs output control so as to perform lighting display. . Then, if the non-lighting potential VB is selected by the data switching unit, the transfer instruction signal T
The output control unit does not operate even when RF is input.

On the other hand, in the case of normally white, the non-lighting potential VB is selected by the data switching section and the transfer instruction signal T
When RF is input, the output control unit performs output control so as to perform non-lighting display. When the lighting potential VW is selected by the data switching unit, the output control unit does not operate even if the transfer instruction signal TRF is input.

In this way, the driving of the respective data signal lines SL1 to SLn by the second data signal line driving circuit 3 ',
The scanning line GL by the scanning line signal drive circuit 4 as described above
Binary data can be displayed by driving 1 to GLm.

The second data signal line drive circuit 3 '
When a binary data image such as a character is displayed by superimposing it on the high-quality display image by the first data signal line drive circuit 3, an image synthesis for previously synthesizing the binary data image and the high-quality image data is performed. It is possible to display superposed images such as superimposed images without requiring a section. Further, the display of the binary data image by the second data signal line drive circuit 3 ′ and the display of the high quality image by the first data signal line drive circuit 3 are divided into display areas and displayed in different areas. You may

Normally, a video interface IC is provided for high-quality image display such as multi-gradation, color display, and high frame frequency. Then, for example, a control signal from the control circuit 6 is input to the video interface IC, a video signal DAT is output from the video interface IC, and the video signal DAT is input to the first data signal line drive circuit 3. Then, the display is driven as described above. Here, by providing the second data signal line drive circuit 3 ', it is not necessary to drive such an interface IC for multi-gradation video signals for displaying binary data, so that the power consumption is reduced accordingly. Can be realized.

By the way, the pixel array 2 shown in FIG. 2, the first data signal line drive circuit 3 (3a to 3d), the second data signal line drive circuit 3'and the scanning signal line drive circuit 4 are
After they are formed separately, they may be connected to each other by connecting the substrates on which they are formed. And each of the drive circuits 3 (3a to 3)
It is preferable that d), 3 ', and 4 are formed on the same substrate, that is, monolithically. Furthermore, in this case,
Since it is not necessary to connect each after forming each, reliability can also be improved. Note that in FIG. 2, circuits formed on the same substrate are surrounded by broken lines.

Further, in FIG. 2, the second signal line drive circuit 3 '
Is arranged on the side opposite to the first signal line driving circuit 3 with respect to the pixel array 2 in the display area, that is, the first signal line driving circuit 3
And the second signal line drive circuit 3'include the pixel array 2 in the display area.
The first signal line drive circuit 3
And the second signal line drive circuit 3'include the pixel array 2 in the display area.
It may be configured to be arranged on the same side with respect to. At this time, the second signal line drive circuit 3'is set to the pixel array 2 in the display area.
On the other hand, when it is arranged on the side opposite to the first signal line drive circuit 3, the space of the substrate can be effectively used, and the wiring can be complicated and the interference between the wirings can be avoided. Further, when the first signal line driving circuit 3 and the second signal line driving circuit 3'are arranged on the same side of the display area with respect to the pixel array 2, some wirings are shared or long-distance wiring is performed. It is possible to avoid signal delay and waveform distortion due to

In the following, as an example of the image display device 1 formed monolithically, the pixel array 2 and the drive circuits 3 (3a ...
The structure of the transistor and the manufacturing method thereof when the active elements 3d) and 4 are configured will be briefly described.

That is, the glass substrate 5 shown in FIG.
1 on the amorphous silicon thin film 5 as shown in FIG.
2 are deposited. Further, as shown in FIG. 9C, the amorphous silicon thin film 52 is irradiated with an excimer laser to change the amorphous silicon thin film 52 into a polycrystalline silicon thin film 53.

Further, as shown in FIG. 9D, the polycrystalline silicon thin film 53 is patterned into a desired shape,
As shown in (e), a gate insulating film 54 made of silicon dioxide is formed on the polycrystalline silicon thin film 53.

Further, in FIG. 9F, after the gate electrode 55 of the thin film transistor is formed of aluminum or the like on the gate insulating film 54, the source / gate of the thin film transistor is formed in FIGS. 9 (g) and 9 (h). Impurities are implanted into regions 56 and 57 which will be drain regions. Here, phosphorus is implanted into the n-type region 56 and boron is implanted into the p-type region 57. Since the remaining region is covered with the resist 58 before the impurity is injected into one region, the impurity can be injected into only a desired region.

Further, as shown in FIG. 9 (i), an interlayer insulating film 59 made of silicon dioxide or silicon nitride is deposited on the gate insulating film 54 and the gate electrode 55, as shown in FIG. 9 (j). So that the contact hole 6
After opening 0, metal wiring 61 such as aluminum is formed as shown in FIG.

As a result, as shown in FIG. 10, a thin film transistor having a forward stagger (top gate) structure in which a polycrystalline silicon thin film on an insulating substrate is used as an active layer can be formed. The figure shows an example of an n-channel transistor, and in the n-type region 56, the polycrystalline silicon thin film 53 below the gate electrode 55 is arranged so as to be sandwiched in the surface direction of the glass substrate 51. One of the regions 56a and 56b is
It becomes a source region and the other becomes a drain region.

As described above, by using the polycrystalline thin film transistor, the data signal line driving circuit 3 (3a to 3d) and the scanning signal line driving circuit 4 having practical driving ability are formed on the same substrate as the pixel array. Moreover, they can be configured by substantially the same manufacturing process. In the above description, the thin film transistor having the structure is described as an example. However, substantially the same effect can be obtained by using a polycrystalline thin film transistor having another structure such as an inverted stagger structure.

Here, in the steps shown in FIGS. 9A to 9K, the maximum temperature of the process is 600 ° C. at the time of forming the gate insulating film. Heat resistant glass can be used as the substrate 51.

By thus forming the polycrystalline silicon thin film transistor at 600 ° C. or lower, an inexpensive and large-area glass substrate can be used as the insulating substrate. As a result, the image display device 1 that is inexpensive and has a large display area can be realized.

Here, as the polycrystalline silicon thin film, N
i, Fe, Co, Sn, Pb, Ru, Rh, Pd, O
One in which crystallization is promoted by any one or a plurality of elements of s, Ir, Pt, Cu, and Au may be used, and good crystallinity and electrical characteristics can be obtained.

When the image display device 1 is a liquid crystal display device, a transmissive electrode (in the case of a transmissive liquid crystal display device) or a reflective electrode (in a reflective liquid crystal display device) is further provided through another interlayer insulating film. Cases) are formed.

[Second Embodiment] In the present embodiment, as an example in which the ratio of the signal line resolution at the time of high resolution to the signal line resolution at the time of low resolution is another value, the signal line resolutions are n and n. The configuration in the case of / 3 will be described.

That is, in the present embodiment, as the ratio is changed from 2: 1 to 3: 1, as shown in FIG.
As shown in FIG. 3, the scanning circuit unit 12b of the first data signal line drive circuit 3b includes three shift registers SRA to SRC.
Is provided. In the case of FIG. 11, the shift register SRA corresponds to the second shift register described in the claims, and the shift registers SRB and SRC correspond to the first shift register.

Accordingly, each shift register SRA ...
The number of SRC stages is set to values p, q, and r that are smaller than those in the case of two systems. Note that p is a quotient when n is divided by 3 when n is a multiple of 3, and is a value obtained by adding 1 to the quotient otherwise. Also, q, r
Is a quotient or a value obtained by adding 1 to the quotient, and p + q + r = n
Is.

Further, each data signal line SL ... Can be sequentially assigned to the outputs of the shift registers SRA to SRC. Specifically, among the output signals O1 to On, the output of each stage of the shift register SRA, that is, the output of the latch circuits LA1 to LAp is (3) of the output signals O1 to On of the scanning circuit unit 12b. It is output as a multiple +1) th output signal O1, O4 ... Similarly, each stage output of the shift register SRB (latch circuits LB1 to LB
output of q) is (multiple of 3 + 2) th output signal O2,
, And the output of each stage of the shift register SRC (outputs of the latch circuits LC1 to LCr) are output as output signals O3, O6 ...

Further, the switching unit 13b according to this embodiment.
Then, in the case of low resolution, the output of each stage of a certain shift register SRA is set to three sampling units S per stage.
It is configured to transmit to U.

More specifically, the switching unit 13b is
It is divided into p blocks B1 to Bp. Assuming that an integer equal to or less than p is k, each block Bk has the outputs O (3 * k-2) and O (3 * k- 1), O (3 * k) to the corresponding sampling units SU (3 * k-2), SU (3
* k-1), and the signal path to SU (3 * k) is provided.

Further, when the resolution switching signal MC indicates a low resolution, each block Bk has a sampling unit SU (3 * k-1) and a corresponding sampling unit SU (3 * k-1) from the inactive shift register SRB / SRC. SU (3 *
switch ASO to cut off the signal path to k)
It has k1 and ASOk2. Also, each block Bk
Is a signal path from the operating shift register SRA and the sampling units SU (3 * k-1) and SU (3 *) corresponding to the non-operating shift registers SRB and SRC when the low resolution is indicated. and a switch ASNk1 and ASNk2 for respectively connecting the signal path to k).

Note that n is 3 as in the first embodiment.
In the final block Bk, the signal path from the shift register SRB or SRC to the sampling unit 11 and the switches ASNp2 and ASOp2
And ASNp1 and ASOp1 are unnecessary.

Further, in each block Bk according to the present embodiment, each of the latch circuits LAk to LAk is provided in the same manner as the configuration of FIG.
Waveform shaping circuits WE (3 * k-2), WE (3 * k-1) and WE (3 * k) for adjusting the pulse width of the signal from Ck, respectively.
And waveform shaping circuits WE (3 * k-2), WE (3 * k-1) and W
Buffer circuits BF (3 * k-2), BF (3 * k-1) and BF (3 *) that buffer the output signal of E (3 * k), respectively.
k) and are provided.

In the above arrangement, the high resolution video signal D
When AT is input, the control circuit 6b gives a resolution switching signal MC (for example, high level) indicating high resolution to the first data signal line drive circuit 3b, as shown in FIG.

In response to this, in the switching unit 13b of the first data signal line drive circuit 3b, the switch ASO11
~ ASOp1 and ASO12 to ASOp2 become conductive, and switches ASN11 to ASNp1 and ASN
12 to ASNp2 are blocked. Thus, the data signal lines SL ... Are sequentially assigned to the outputs of the shift registers SRA to SRC.

When the resolution switching signal MC indicates high resolution, the register control section 14 supplies power to the shift registers SRB / SRC, for example,
The shift register SRB / SRC is operating. On the other hand, the control circuit 6b controls all the shift registers SRA to SRC.
In order to drive the clock signal SCKA, the shift timing frequency is 1/3 of the applied frequency of the video data D.
SCKC is output respectively. At this time, the control circuit 6b
To write individual data (video data D to each pixel PIX) in time to each data signal line SL, the phase of each clock signal SCKA to SCCK is shifted by each clock signal SCKA to SCCK. Register S
The shift timing instructed to RA to SRC is the data signal line SL corresponding to each shift register SRA to SRC.
Order (in this case, SCKA → SCKB → SCCK →
It is set to be repeated in the order of SCKA).

In this embodiment, each shift register SRA is
~ SRC are configured to shift on both edges of the clock signals SCKA to SRC. Therefore, the frequency of each clock signal SCKA to SCCK is 1/6 of the applied frequency of the video data D, and the clock signal SCKA
The phase difference of -SCCK is set to 60 degrees.

Further, the control circuit 6b causes the start pulse signals SSPA to the shift registers SRA to SRC so that the phase differences of the first-stage outputs O1 to OC of the shift registers SRA to SRC are delayed by the phase difference. ~
Output SSPC.

As a result, as shown in FIG. 12, the phase difference between the waveform of each output Oi of the scanning circuit section 12b and the previous output O (i-1), and the output signal Ti of the buffer circuit BFi.
And the output signal T (i-1) of the previous buffer circuit BF (i-1) becomes the above-mentioned phase difference. As a result, the buffer circuits BF1 to BFn inform the sampling unit 11 of timing signals T1 indicating different sampling timings.
~ Tn can be output.

Therefore, as in the first embodiment, the apparent signal line resolution of the sampling unit 11 is n, and each sampling unit SU of the sampling unit 11 is
1 to SUn are video signals D at different timings.
AT can be sampled. Accordingly, from the video signal DAT having the signal line resolution n, the video data D (1, j) to D (n,
j) is sampled, and while the scanning signal line GLj is selected, to each data signal line SL1 to SLn,
The sampling results (D (1, j) to D (n, j)) can be output.

On the other hand, when the low resolution video signal DAT is input, the control circuit 6b drives the resolution switching signal MC (for example, low level) indicating the low resolution to the first data signal line drive as shown in FIG. Output to the circuit 3b.

In response to this, in the switching unit 13b, the switches ASO11 to ASOp1 and ASO12 are switched.
~ ASOp2 is cut off and switch ASN11
~ ASNp1 and ASN12 to ASNp2 are conducted. In this state, the sampling unit SU (3 * k) starts from the kth stage (latch circuit LAk) of the shift register SRA.
-2), the signal paths to SU (3 * k-1) and SU (3 * k) become valid, and three adjacent data signal lines SL ... Are assigned to the shift register SRA as one set.

Further, the control circuit 6b controls the start pulse signals SSPB / SS to the shift registers SRB / SRC.
The PC is fixed to the low level, and the shift registers SRB and SRC, which are determined to be inoperative at low resolution, are inactivated. In addition, when the resolution switching signal MC indicates low resolution, the register control unit 14 shuts off the power supply to these shift registers SRB / SRC, for example. As a result, the power consumption of the shift registers SRB / SRC in the non-operating state can be reduced.

Further, the control circuit 6b is provided with a shift register S
The clock signals SCKB / SCCK to the RB / SRC are fixed to a constant potential. Thereby, for example, the control circuit 6
It is also possible to reduce the power consumption of the circuit that generates each clock signal, such as b.

On the other hand, the control circuit 6b includes the shift register S
In order to drive RA, the clock signal SCKA having the same shift timing frequency as the applied frequency of the video data D is used.
And the start pulse signal SSPA. In this embodiment, since the shift is performed at both edges, the frequency of the clock signal SCKA is 1/2 of the applied frequency of the video data D.

As a result, as shown by O1 in FIG. 13, the waveform of each output signal O (3 * k-2) output by each latch circuit LAk of the shift register SRA of the scanning circuit section 12b is as shown in the preceding stage. Output O signal of latch circuit LA (k-1) (3 * k-5)
Instead, the waveform has a timing delayed by the shift interval of the shift register SRA (in this example, by 180 degrees of the clock signal SCKA). The shift register SRB
Since the SRC stops operating, the output of each stage of the shift register SRB is a fixed value (low level in the example of FIG. 13).

Further, similarly to the first embodiment, each waveform shaping circuit WEi and buffer circuit B according to the present embodiment.
Fi only adjusts the pulse width and buffers it. Therefore, the buffer circuits BF (3 * k-2) to BF (3 * k) corresponding to the kth stage latch circuit LAk output signal Ti (3
* k-2) to Ti (3 * k) are output. In addition, the output signal T
i (3 * k-2) to Ti (3 * k) and 1 of the above latch circuit LAk.
Buffer circuit B corresponding to the latch circuit LA (k-1) in the preceding stage
Output of F (3 * k-5) to BF (3 * k-3) Ti (3 * k-5) to Ti (3
* k-3) is the same as the phase difference between the output signal O (3 * k-5) of the shift register SRA and the output signal (3 * k-2) of the shift register SRA. In the example, it is 180 degrees of the clock signal SCKA).

Therefore, the apparent signal line resolution of the sampling unit 11 is p, and among the sampling units SU1 to SUn of the sampling unit 11, three adjacent sampling units SU (3 * k-2) to SU ( 3 *
k) sample the video signal DAT at different timings, and the three adjacent sampling units SU (3 * k-2) and SU (3 * k) sample the video signal DAT at the same timing. To sample. As a result, the video data D (1, j) to D (p, j) are sampled from the video signal DAT having the signal line resolution p, and while the scanning signal line GLj is selected, each data signal line SL1 is selected. To SLn, sampling results (D (1, j) ~ D
(p, j)) can be output.

In the above description, the case where the shift register SRA operates at a low resolution has been described as an example, but as a matter of course, the shift register SRA operates at a low resolution as in the first data signal line drive circuit 3c shown in FIG. The SRB may be operated, or the first data signal line drive circuit 3 shown in FIG.
The shift register SRC may be operated at the time of low resolution as shown by d. In the case of FIG. 14, the shift register SRB corresponds to the second shift register described in the claims, and the shift registers SRA and SRC correspond to the first shift register. Further, in the case of FIG. 15, the shift register SRC is the second shift register and the shift register SRC is the second shift register.
RA · SRB corresponds to the first shift register.

Further, in the above first and second embodiments, the ratio of the signal line resolution at the time of high resolution to the signal line resolution at the time of low resolution is 2: 1 and 3: 1 respectively. As described above, for example, if x is an arbitrary integer of 2 or more, such as providing 4 system shift registers in the case of 4: 1, the x system shift registers can be used when the signal line resolution is x: 1. It may be provided.

In each of the above embodiments, in the high resolution mode, one data signal line SLi (one sampling unit) is assigned to each output Oi of each scanning circuit section 12 (12a to 12d). However, it is not limited to this. For example, when each pixel is composed of R, G, and B sub-pixels, and the sampling units that drive the data signal lines to the sub-pixels are driven at the same timing regardless of the resolution, For example, when the DAT is divided by a plurality of signal lines and transmitted, and sampling units for sampling each are driven at the same timing regardless of the resolution, the plurality of sampling units have the same timing regardless of the resolution. In the high resolution mode, a set of these sampling units may be assigned to each output Oi. In this case, in the low resolution mode, a plurality of sets, which are driven at temporally adjacent timings, of the sets of sampling units are driven on the basis of each stage output of the operating shift register, one by one. To be done.

Further, in each of the above-described embodiments, the case where each of the data signal lines SL1 to SLn is point-sequentially driven has been described as an example, but the case of line-sequential driving may be used. Even in this case, a sampling unit is provided for sampling the video data D, which indicates the signals to be output to the respective data signal lines SL1 to SLn, from the video signal DAT. Therefore, the same effect can be obtained by generating the timing signals T1 to Tn to the sampling section by the scanning circuit section and the switching section having the same configuration as the first data signal line drive circuit 3 (3a to 3d). To be

Furthermore, in each of the above-mentioned embodiments, each shift register (SRA to SRC) has a clock signal (SCKA to SRC).
The description has been given by taking the case of shifting at both edges of (SCCK) as an example, but the invention is not limited to this. The same effect can be obtained by shifting in synchronization with the clock signal. However, if the shift is performed at both edges as in the present embodiment, the frequency of the clock signal can be reduced to ½ if the shift period is the same as when shifting at one edge. Therefore, the power consumption of the clock signal generation circuit can be reduced.

In each of the above embodiments, the scanning circuit unit 1
2 (12a to 12d) and the switching unit 13 (13a to
13d) and the sampling unit 11 between the waveform shaping circuit W
The case where E ... and the buffer circuits BF ... Are provided has been described as an example, but the present invention is not limited to this. Even if the scanning circuit unit 12 (12a to 12d) directly drives the sampling unit 11, the scanning circuit unit 12 (12a to 1) is controlled so that the variation of the sampling timing is within the allowable range.
If the driving capability of 2d) is sufficiently large, the waveform shaping circuit WE
, And the buffer circuit BF may be omitted.

However, the higher the signal line resolution, the narrower the allowable range. In addition, a polycrystalline silicon thin film transistor is often limited in driving ability as compared with a case where a transistor is formed using single crystal silicon. Therefore, when the active element of the first data signal line drive circuit 3 (3a to 3d) is formed of a polycrystalline silicon thin film transistor, or when the maximum signal line resolution is high,
It is desirable to provide the waveform shaping circuits WE ... And the buffer circuits BF ... As in each of the above embodiments.

In each of the above embodiments, the switching unit 1
3 (13a to 13d) are provided with switches (ASN ...) That cut off the signal path from the non-operating shift register, but the invention is not limited to this. The circuit configuration of the shift register and the presence or absence of power supply to the shift register are set so that the output of the non-operating shift register does not interfere with the signal transmission from the operating shift register to each sampling unit. Good.

However, as in each of the above-mentioned embodiments, if the cutoff switch is provided, no matter what kind of circuit the shift register is composed of, there is no problem and the shift register is in the non-operating state. Power supply to the shift register can be stopped.

Regardless of the signal line resolution ratio x: 1, the signal driving method, the presence or absence of a waveform shaping circuit, and the configuration of the switching unit, the first data signal line driving circuit according to each of the above embodiments is When the signal line resolution is high, a timing signal T1 for sampling the high-resolution video signal DAT while suppressing the drive frequency of each shift register to a low level by using the shift registers of all systems
-Tn, and timing signals T1 to Tn for sampling the low-resolution video signal DAT using any one of the small-scale and low-power-consumption shift registers optimized for the low driving frequency. Is being generated. As a result, a data signal line drive circuit capable of driving each of the data signal lines SL1 to SLn with low power consumption, although the apparent signal line resolution can be changed according to the signal line resolution of the video signal DAT. realizable.

In the above description, the first data signal line drive circuit 3 (3a) of the active matrix type image display device 1 is used.
3d) has been described as an example, but the present invention is not limited to this. The present invention, for example, in an image forming apparatus such as a printer, when controlling the brightness of a plurality of linearly arranged areas to form an electrostatic latent image, a data signal line connected to each area is formed. It can also be applied to a data signal line drive circuit for driving.

In any case, each data is sampled from an input signal that transmits data indicating a signal to be output to each data signal line in a time division manner, and each data signal is based on the sampling result. In the case of the first data signal line drive circuit that drives the lines, in order to correctly sample each data regardless of which input signal of the plurality of signal line resolutions is input, as in the above case. The timing signal can be generated with low power consumption.

Also, in the above, the shift register (SRA
~ SRC) and the sampling unit 11 between the switching unit 1
By providing 3 (13a to 13d), when the signal line resolution is low, timing signals indicating the same timing are generated to the plurality of sampling units based on the output of one stage of the output of the shift register, The configuration for outputting the same value data to each of the data signal lines corresponding to these sampling units has been described.
It is not limited to this.

For example, the switching unit 13 (13a-13
d) is the sampling unit SU ... and the data signal line S
You may provide between Li ... In this configuration, when the signal line resolution is low, the sampling units SU corresponding to the respective stages are output based on the respective stage outputs (for example, the latch circuits LAT1 to LATp) of the shift register (for example, the shift register SRA) which are in the operating state. Samples the video signal DAT. Further, the switching unit 13 (13a to 13)
d) is a data signal line SL corresponding to the sampling unit SU from the sampling unit SU,
A signal path to the data signal line SL adjacent to the data signal line SL is formed. In this case, when the signal line resolution is high, the switching unit 13 (13a to 13d) generates signal paths to the sampling units SU1 to SUn and the corresponding data signal lines SL1 to SLn.

Even in this case, if the signal line resolution is low,
Since the input signal (video signal DAT) sampled at the sampling timing determined based on the output of one stage of the operating shift register is output to each of the plurality of adjacent data signal lines SL, the same The effect is obtained.

However, as in the first and second embodiments, when the switching unit 13 (13a to 13d) is provided in the front stage of the sampling unit 11 instead of the latter stage, the output of the sampling unit 11 is , Switching unit 13 (1
Equivalent data can be written to a plurality of data signal lines without passing through 3a to 13d). Therefore,
Due to the passage of the switching unit 13 (13a to 13d),
An error that occurs in the above data does not occur, and more accurate data can be written in the data signal line.

In the above description, the second data signal line drive circuit 3'is used for displaying one type of binary data, but the present invention is not limited to this. For example, the second data signal line drive circuit 3 ′ has the same configuration as the first data signal line drive circuit 3 (3 a to 3 d) and the second data signal line drive circuit 3 (3 a to 3 d) and the second data signal line drive circuit 3 (3 a to 3 d).
The resolution may be different from that of the data signal line drive circuit 3 ', and a configuration may be adopted in which the display quality of the same level is displayed by any of the data signal line drive circuits.

Further, for example, the second data signal line drive circuit 3'may be used for displaying a plurality of binary data of different resolutions. To this end, as the second data signal line drive circuit 3 ′, similarly to the first data signal line drive circuit 3, the signal line drive units provided corresponding to the plurality of signal lines respectively respond to the input signals. And a scanning unit for outputting a timing signal indicating a timing for operating the same. In the scanning unit, the first and second shift registers of different systems and the first and second shift registers in the high resolution mode are provided. A control means for operating the first shift register may be provided in the low resolution mode in which an input signal having a signal line resolution lower than that in the high resolution mode is applied.

[0161]

As described above, the signal line drive circuit according to the present invention includes, in the first signal line drive circuit, the first and second shift registers of different systems, and the first and second shift registers in the high resolution mode. A control means for operating the two shift registers and suspending the first shift register in the low resolution mode in which an input signal having a signal line resolution lower than that of the high resolution mode is applied is provided.

According to the above configuration, in the low resolution mode,
The first shift register is not operating. Also, the first
Since the second shift register and the second shift register are different systems from each other, a configuration of a conventional technique, that is, a configuration in which a single system shift register is provided, and in a low resolution mode, some stages are skipped to shift pulses Also, the operation speed required for the second shift register can be suppressed. Therefore, the second shift register can be configured by a circuit with lower power consumption.

As a result of these, even when either an input signal with a high signal line resolution or an input signal with a low signal line resolution is input, the power consumption of the power consumption is reduced in spite of the fact that the signal line drive section can be instructed to the correct operation timing. This has the effect of realizing a low signal line drive circuit.

Further, since the second signal line drive circuit which shares at least a part of the plurality of signal lines driven by the first signal line drive circuit is provided, for example, the display by the first signal line drive circuit is performed. By displaying an image having a display quality different from that of the image, the power consumption can be further reduced.

As described above, in the signal line drive circuit according to the present invention, in addition to the above configuration, the signal line drive section is a sampling circuit for sampling the input signal at the timing indicated by the timing signal, The first signal line drive circuit is configured to operate as a data signal line drive circuit.

According to this structure, it is possible to realize a data signal line drive circuit with low power consumption, although both an input signal with high signal line resolution and an input signal with low signal line resolution can be sampled correctly. Play.

As described above, in the signal line drive circuit according to the present invention, in addition to the above configuration, the scanning section, in the high resolution mode, performs sampling corresponding to each stage of the second shift register. A signal is transmitted to the circuit, a signal is transmitted from each stage of the first shift register to a corresponding sampling circuit, and in the low resolution mode, from each stage of the second shift register.
The configuration is provided with a switching circuit that switches the signal path so that the signal is transmitted to the corresponding sampling circuit and the sampling circuit corresponding to each stage of the first shift register.

According to this structure, in the low resolution mode,
A signal path is formed from each stage of the second shift register to a sampling circuit corresponding to each stage of the first and second shift registers, and a plurality of samplings are performed based on the timing signal from one stage of the second shift register. The circuit samples the input signal. As a result, in the low resolution mode, the same value data can be written in the data signal lines corresponding to these sampling circuits. Therefore, the apparent signal line resolution of the data signal line driven by the data signal line drive circuit can be adjusted according to the resolution of the input signal.

As described above, in the signal line drive circuit according to the present invention, in addition to the above-mentioned respective configurations, the first and second shift registers are synchronized with the clock signals transmitted by the clock signal lines different from each other. While operating, the clock signal supply to the first shift register is stopped in the low resolution mode, and the clock signals indicating different shift timings are supplied to the first and second shift registers in the high resolution mode. This is a configuration including clock signal control means.

According to this structure, in the low resolution mode,
The first shift register is deactivated and the clock signal supply to the first shift register is stopped.
Therefore, in the low resolution mode, it is possible to reduce the power consumption in the circuit that generates the clock signal to the first shift register and reduce the power consumption of the entire system including the signal line drive circuit and the clock signal control means. .

As described above, the image display device according to the present invention includes a plurality of data signal lines, a plurality of scanning signal lines arranged so as to intersect with each of the data signal lines, the data signal lines, and The sampling results of the pixels arranged in a matrix corresponding to the combination of the scanning signal lines, the scanning signal line driving circuit for driving the scanning signal lines, and the sampling results of the sampling circuits provided corresponding to the respective data signal lines are displayed. A data signal line drive circuit that outputs a corresponding signal to each of the data signal lines is provided, and the data signal line drive circuit is any one of the above-described first signal line drive circuits.

Therefore, there is an effect that it is possible to realize an image display device with low power consumption, although both a high-resolution video signal and a low-resolution video signal can be displayed correctly.

Further, since the second signal line drive circuit which shares at least a part of the plurality of signal lines driven by the first signal line drive circuit is provided, for example, the display by the first signal line drive circuit is performed. By displaying an image whose display quality is different from that of the image, it is possible to realize an image display device with lower power consumption.

As described above, the image display device according to the present invention has a configuration in which, in addition to the above configuration, the pixels, the data signal line drive circuit and the scanning signal line drive circuit are formed on the same substrate.

According to this structure, since the data signal line drive circuit and the scanning signal line drive circuit are formed on the same substrate as the pixel, after forming each on a different substrate,
The manufacturing cost and the mounting cost of each drive circuit can be reduced more than the case where each board is connected.

As described above, in the image display device according to the present invention, in addition to the above configuration, the active elements constituting the pixels, the data signal line drive circuit and the scanning signal line drive circuit are polycrystalline silicon thin film transistors. It is a composition.

According to this structure, the size of the substrate can be increased as compared with the case where the active element is formed of a single crystal silicon transistor. As a result, not only the power consumption is small, but also an image display device having a wide screen can be manufactured at low cost.

As described above, the image display device according to the present invention has a structure in which the active element is formed on the glass substrate by a process at 600 ° C. or lower in addition to the above structure.

According to this structure, since the active element is manufactured by the process at 600 ° C. or lower, the active element can be formed on the glass substrate. As a result, not only the power consumption is small, but also an image display device having a wide screen can be manufactured at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention and showing a main configuration of a first data signal line drive circuit.

FIG. 2 is a block diagram showing a main configuration of an image display device including the first data signal line drive circuit and the second signal line drive circuit.

FIG. 3 is a circuit diagram showing a schematic configuration of a pixel provided in the image display device.

FIG. 4 is a circuit diagram showing a configuration example of a switch provided in the first data signal line drive circuit.

FIG. 5 is provided in the first data signal line drive circuit,
It is a circuit diagram which shows the structural example of another switch.

FIG. 6 is a waveform diagram showing an operation of the first data signal line drive circuit and showing a signal waveform of each part in a high resolution mode.

FIG. 7 is a waveform diagram showing an operation of the first data signal line drive circuit and showing a signal waveform of each part in a low resolution mode.

FIG. 8 is a block diagram showing a modification of the first data signal line drive circuit.

FIG. 9 shows a manufacturing process of a thin film transistor which constitutes the above image display device, wherein (a) to (k) are
It is a process sectional view showing a substrate section in each process.

FIG. 10 is a cross-sectional view showing a structure of the thin film transistor.

FIG. 11 shows another embodiment of the present invention.
FIG. 3 is a block diagram showing a main configuration of a one-data signal line drive circuit.

FIG. 12 is a waveform diagram showing an operation of the first data signal line drive circuit and showing a signal waveform of each part in a high resolution mode.

FIG. 13 is a waveform chart showing an operation of the first data signal line drive circuit and showing a signal waveform of each portion in a low resolution mode.

FIG. 14 is a block diagram showing a modification of the first data signal line drive circuit.

FIG. 15 is a block diagram showing another modification of the first data signal line drive circuit.

FIG. 16 is a block diagram showing a conventional example and showing a main configuration of an image display device.

FIG. 17 is a block diagram showing a main configuration of a data signal line drive circuit provided in the image display device.

FIG. 18 is a waveform diagram showing an operation of the data signal line drive circuit and showing a signal waveform of each part.

FIG. 19 shows another conventional example and is a block diagram showing a main configuration of a data signal line drive circuit.

FIG. 20 is a waveform chart showing an operation of the data signal line drive circuit and showing a signal waveform of each portion in a low resolution mode.

[Explanation of Codes] 1 Image display device 3 · 3a to 3d First data signal line drive circuit (first
Signal line drive circuit 3'second data signal line drive circuit (second signal line drive circuit) 4 scanning signal line drive circuit 6 / 6b control circuit (clock signal control means) 12 ・ 12a to 12d scanning circuit unit (scanning unit) ) 13.13a to 13d switching unit (switching unit) 14 register control unit (control unit) GL1 ... Scanning signal line PIX (1,1) ... Pixel SL1 ... Data signal line (signal line) SRA to SRC shift register (first) And second shift register) SU1 ... Sampling unit (signal line driver / sampling circuit)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 623 G09G 3/20 623H 623M 650 650B G11C 19/00 G11C 19/00 J K (72) Invention Person Keiji Takahashi 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Prefecture Sharp Corporation (72) Inventor Hajime Washio 22-22, Nagaike-cho, Abeno-ku, Osaka City, Osaka Prefecture F-term (reference) 2H093 NA16 NA41 NA51 NA61 NC09 NC11 NC22 NC23 NC26 NC34 NC41 ND20 ND39 ND54 NE01 NE02 NE03 NE07 5C006 AC21 AF68 BB16 BC12 BC16 BC20 BF03 BF11 BF24 FA47 5C080 AA10 BB05 DD26 FF11 JJ02 JJ04 JJ06

Claims (8)

[Claims] 1. A first scanning unit is provided, which outputs a timing signal indicating a timing at which each signal line driving unit provided corresponding to each of a plurality of signal lines operates according to an input signal. A signal line drive circuit is provided, and the scanning unit operates the first and second shift registers of different systems, and the first and second shift registers in the high resolution mode, and operates from the high resolution mode. In the low resolution mode in which an input signal having a low signal line resolution is applied, a control means for suspending the first shift register is provided, and at least a part of the plurality of signal lines is provided in the first signal line. A signal line drive circuit, wherein a second signal line drive circuit common to the drive circuit is provided. 2. The signal line driving unit according to claim 1, wherein the signal line driving unit is a sampling circuit that samples the input signal at a timing indicated by the timing signal, and operates as a data signal line driving circuit. Line drive circuit. 3. The scanning section, in the high resolution mode, transmits a signal from each stage of the second shift register to a corresponding sampling circuit, and from each stage of the first shift register to each stage. While the signal is transmitted to the corresponding sampling circuit, in the low resolution mode, from each stage of the second shift register to the corresponding sampling circuit and the sampling circuit corresponding to each stage of the first shift register. 3. The signal line drive circuit according to claim 2, further comprising switching means for switching a signal path so that a signal is transmitted. 4. The first and second shift registers,
It operates in synchronization with clock signals transmitted through mutually different clock signal lines, stops the clock signal supply to the first shift register in the low resolution mode, and operates in the first resolution register in the high resolution mode.
2. A clock signal control means for supplying clock signals indicating different shift timings to the second shift register and the second shift register, respectively.
2. The signal line drive circuit described in 2 or 3. 5. An image display device using the signal line drive circuit according to claim 1, wherein the plurality of data signal lines are arranged so as to intersect with each of the data signal lines. A plurality of scanning signal lines, pixels arranged in a matrix corresponding to the combination of the data signal lines and the scanning signal lines, a scanning signal line driving circuit that sequentially drives the scanning signal lines, and the data. A data signal line drive circuit for outputting a signal according to a sampling result of a sampling circuit provided corresponding to the signal line to each of the data signal lines, wherein the data signal line drive circuit comprises the first signal line An image display device, comprising: a drive circuit, wherein the second signal line drive circuit shares at least a part of the plurality of data signal lines with the first signal line drive circuit. 6. The image display device according to claim 5, wherein the pixel, the data signal line drive circuit, and the scanning signal line drive circuit are formed on the same substrate. 7. The active element forming the pixel, the data signal line drive circuit and the scanning signal line drive circuit is a polycrystalline silicon thin film transistor.
The image display device described. 8. The image display device according to claim 7, wherein the active element is formed on a glass substrate by a process at 600 ° C. or lower.