JPH07219475A - Driving circuit for display device - Google Patents

Abstract

PURPOSE:To surely allocate the outputs corresponding to digital image signals to multiple data electrodes of a matrix type display device by providing a data input/output mode switching-over means switching over the first mode and the second mode. CONSTITUTION:A driving circuit 21 has four series of digital image signal input terminals Da-Dd, and it is operated in the first mode when the potential of a control signal input terminal C is 'Low'. Four series of digital image signals of R, G, B, W signals are inputted to the digital image signal input terminals Da-Dd respectively, and picture element voltages corresponding to the R, G, B, W signals are outputted from output terminals (l)-(3).... When either of two kinds of multiple series of digital image signals are inputted, the outputs corresponding to the inputted multiple series of digital image signals can be allocated to the prescribed data electrodes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit of a display device to which a plurality of series of digital video signals are inputted, and more particularly,
The present invention relates to a drive circuit of a display device for outputting a plurality of series of digital video signals to a plurality of data electrodes of a matrix type display device.

[0002]

2. Description of the Related Art Conventionally, three series of digital video signals composed of R signal, G signal and B signal, or R signal, G signal,
There is known an active matrix type color liquid crystal display device which inputs four series of digital video signals composed of a B signal and a W signal.

FIG. 7 is a schematic plan view showing the outline of an active matrix type color liquid crystal display device. Liquid crystal display device 1
Has a liquid crystal display panel 2. On the liquid crystal display panel 2, liquid crystal display cells are arranged in a matrix of M rows × N columns (M and N are integers), and a thin film transistor (TFT) is connected to each liquid crystal display cell.

Further, in the liquid crystal display device 1, a plurality of gate lines 3a, 3b ... 3M and a plurality of drain lines 4a, 4b ... 4N are arranged so as to be orthogonal to each other.
The above-mentioned TFTs are connected to the respective intersections of the gate lines and the drain lines.

A gate driver 5 is connected to the gate lines 3a to 3M, and a drain driver 6 is connected to the drain lines 4a to 4N. In the liquid crystal display device 1, a predetermined gate line 3a to 3M is selected in the gate driver 5 by a control signal given from the controller 7. The TFT on the selected gate line is turned on, and in that state, the pixel voltage is applied from the drain driver 6 to the drain lines 4a to 4N, and the pixel voltage is written to the liquid crystal display cell on the selected gate line. Is displayed.

By the way, in order to perform color display on the liquid crystal display panel 2, color filters are arranged on the display panel 2 in a fixed pattern. For example, in FIG.
In the example shown in (a), R (red), G (green), B (blue), and W (white) filters are arranged in this order. Further, in the display panel 2 shown in FIG.
The R, G, and B color filters are arranged in a stripe pattern in this order.

On the other hand, the drain driver 6 in the liquid crystal display device 1 of FIG. 7 receives a plurality of series of digital video signals corresponding to the color arrangement of the liquid crystal display panel 2 described above, and outputs a pixel voltage corresponding to the color arrangement. Drain line 4
a to 4N. For example, the drain driver 6 shown in FIG. 7 corresponds to the color array shown in FIG. 8A and has a plurality of series of digital video signal input terminals D _{A to} D _D.

An example of the drain driver 6 will be described with reference to FIG. The drain driver 6 has a shift register 8, a digital data memory 9, a latch circuit 10 and a voltage level selection circuit 11. Further, the digital data memory 9 has digital video signal input terminals D _{A to} D _D , and is a digital video signal composed of an R signal, a G signal, a B signal and a W signal corresponding to R, G, B and W described above. Is entered. The drain driver 6 receives the control signal from the controller 7 and, according to the output of the shift register 8, the R input from the digital video signal input terminals D _{A to} D _D into a predetermined storage area in the digital data memory 9.
Signals, G signals, B signals and W signals are stored. Then, the stored R signal, G signal, B signal and W signal are
After being latched by the latch circuit 10, it is applied to the voltage level selection circuit 11 to be applied with a predetermined voltage level and output to the output terminals, .... This output terminal,
Are the drain lines 4a to 4a shown in FIG. 7, respectively.
It is connected to 4N.

On the other hand, as shown in FIG. 8B, when the liquid crystal display panel 2 uses color filters of three colors of R, G and B, the drain driver 16 shown in FIG. Used. The drain driver 16 is
A digital data memory 19 having three series of digital video signal input terminals D _R , D _G and D _B is provided. By the output of the shift register 18, the R signal, the G signal, and the B signal input from the digital video signal input terminals D _{R to} D _B are stored in predetermined storage areas inside the digital data memory 19, respectively. Thereafter, the digital video signal for one horizontal scanning period is latched by the latch circuit 10 and then given a predetermined voltage level by the voltage level selection circuit 11 and output to the output terminals, ....

The drain driver 6 and the drain driver 16 described above are commercially available as one-chip ICs.

[0011]

However, the drain driver 6 is configured to use the 4-series digital video signal as an input as described above, while the drain driver 16 is configured to use the 3-series digital video signal. It is configured to be used as an input. That is, the drain driver 6 is configured to be used in the liquid crystal display panel 2 having the color arrangement shown in FIG. 8A, and the drain driver 16 is used as the liquid crystal display panel having the color arrangement shown in FIG. 8B. 2 is used.

Therefore, when the color arrangement of the liquid crystal display panel is changed, it is necessary to prepare a different drain driver. However, by processing the input digital video signal in the preceding stage of the drain driver, the drain driver 6 having, for example, four series of digital video signal input terminals is provided in the color array liquid crystal display panel shown in FIG. 8B. It can also be used for 2. However, when used in the liquid crystal display panel 2 shown in FIG. 8B, since the input digital video signal is composed of the R signal, the G signal and the B signal, as shown in the following formula,

[0013]

[Equation 1]

The input digital video signal must be converted so that the R signal, the G signal, and the B signal are sequentially assigned to the digital video signal input terminals D _{A to} D _D , respectively.

Similarly, when the drain driver 16 having three series of digital video signal input terminals is used in the liquid crystal display panel 2 of the color array shown in FIG. 8A, as shown in the following formula,

[0016]

[Equation 2]

Input digital video signals (R signal, G
Signal, B signal and W signal) had to be converted so that digital video signal input terminals D _R , D _G and D _B were sequentially assigned.

Therefore, since the digital video signal must be processed in the preceding stage of the drain drivers 6 and 16 as described above, a complicated digital video signal conversion circuit must be prepared separately, and such data conversion must be performed. When the circuit was provided, a commercially available controller could not be used as it was.

When the drain driver 6 having four series of digital video signal input terminals is used for the color liquid crystal display panel 2 having the color arrangement shown in FIG. 8B, only three series out of four series are used. It is also possible. However, in that case, only 3/4 of the output terminals of the drain driver 6 can be used. In addition, it is necessary to separately configure a dedicated TAB, which causes a cost increase.

An object of the present invention is to assign an output corresponding to a plurality of inputted digital video signals of a plurality of series to a predetermined data electrode regardless of which of the two kinds of digital video signals of a plurality of series is inputted. It is an object of the present invention to provide a drive circuit of a matrix type display device having a built-in structure capable of outputting the same.

[0021]

According to the present invention, a plurality of series of digital video signals are input, and outputs corresponding to the plurality of series of digital video signals are input to a plurality of data electrodes of a matrix type display device. When a x-series (x is an integer of 3 or more) digital video signal is applied to x data input terminals in a drive circuit of a display device that allocates and outputs, an output corresponding to the x-series digital video signal A first mode in which is assigned to the plurality of data electrodes and output, and a y-series (y is an integer of 2 or more smaller than x) digital video signal is given to y data input terminals, And a data input / output mode switching means for switching between a second mode in which an output corresponding to the y-series digital video signal is assigned to a plurality of data electrodes and output. Which is a driving circuit of the location.

Further, the drive circuit of the display device of the present invention is preferably used in the color liquid crystal display device described above. In that case, as described in claim 2, x is set to 4, that is, R signal, G signal. Signal, B signal, and W signal can be made to correspond to four series of digital video signals, and y is 3
That is, it is possible to correspond to three series of digital video signals composed of R signal, G signal and B signal.

Further, the drive circuit of the display device of the present invention is
Preferably, it is configured in a one-chip driver IC as described in claim 3.

[0024]

In the drive circuit of the display device of the present invention, the data input / output mode switching means is provided, and the data input / output mode switching means operates in accordance with the number of streams of the digital video signal inputted. It is possible to switch between the mode and the second mode. That is, when the mode is switched to the first mode, the output is assigned to the plurality of data electrodes and output according to the x-series digital video signal,
When used for the purpose of inputting a y-series digital video signal, by switching to the second mode, an output corresponding to the y-series digital video signal is assigned to a plurality of data electrodes and output. . Therefore, it is possible to configure a drive circuit of a display device corresponding to two kinds of digital video signals of a plurality of series without connecting a circuit for converting a digital video signal to the outside.

According to a third aspect of the present invention, by configuring the drive circuit of the display device in a one-chip driver IC, the drive of the display device capable of supporting two kinds of digital video signals of a plurality of series. The circuit can be configured as a one-chip IC.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An outline of a drive circuit of a display device according to an embodiment of the present invention will be described with reference to FIGS. Driving circuit 21 shown in FIGS. 1 and 2, 4 has a digital video signal input terminal D _a to D _d series, is configured as a driver for driving the data electrodes of the active matrix color liquid crystal display device There is something.

The drive circuit 21 has four series of digital video signal input terminals D _{a to} D _d , and when the potential of the control signal input terminal C is "low" as shown in FIG. Operated in mode. That is, four series of digital video signals of R, G, B and W signals are represented by the following equations:

[0028]

[Equation 3]

Each of the digital video signal input terminals D _a to
Input to D _d , output terminal, ..., R signal, G
The pixel voltage corresponding to the signal, the B signal, and the W signal is output. On the other hand, as shown in FIG. 2, when the “high” voltage V is applied to the control signal input terminal C, the drive circuit 21 is driven by the second circuit.
Is operated in the mode. In this case, as shown in the equation below,

[0030]

[Equation 4]

An R signal, a G signal and a B signal are input to the digital video signal input terminals D _{a to} D _c , respectively. The video signal input terminal D _d is not used. Also, the output terminal,
, ..., Output voltages corresponding to the R signal, the G signal, and the B signal are output to the respective units, as illustrated.

The drive circuit 21 of the display device of this embodiment is provided with the data input / output mode switching means so as to operate in the first mode and the second mode as described above. The digital video signal input / output mode switching means will be described more specifically with reference to FIGS.

FIG. 3 shows a drive circuit 2 of the display device of this embodiment.
2 is a schematic block diagram of No. 1 and is used as a drain driver in the color liquid crystal display device shown in FIG. 1, for example.

Referring to FIG. 3, drive circuit 21 has shift register 22, digital data memory 23, latch circuit 24 and voltage level selection circuit 25. The shift register 22 includes a data input / output switching circuit, which will be described later with reference to FIG. 4, and a predetermined memory in the digital data memory 23 according to the type of the digital video signal applied to the digital video signal input terminal. The output for storing the digital video signal in the area is the digital data memory 2
Give to 3. Digital data memory 23 has a digital video signal input terminal D _a to D _d, and R signals, G signals,
It has a storage area for storing B signals and W signals.

Depending on the output from the shift register 22,
The R signal, the G signal, the B signal, or the R signal, the G signal, the B signal, and the W signal stored in a predetermined storage area in the digital data memory 23 for one horizontal scanning period are output to the latch circuit 24. After being latched by the latch circuit 24, a predetermined voltage level is given by the voltage level selection circuit 25 and output to the output terminals. The latch circuit 24 and the voltage level selection circuit 25 can be configured in the same manner as a conventionally known drive circuit for a display device.

Next, an example of the shift register 22 having the data input / output mode switching circuit is shown in FIG. 4, a timing chart of the operation in the first mode is shown in FIG. 5, and a timing chart of the operation in the second mode is shown in FIG. 6 shows.

Referring to FIG. 4, the shift register 22 includes
First shift register unit 22A which operates in the first mode, that is, when four series of digital video signals are input
And a second shift register section 22B that operates the display circuit 21 in the second mode when a three-series digital video signal is input. Each shift register unit 22A, 2
2B is configured by connecting a plurality of flip-flops 26.

A data input / output mode switching circuit 27 is connected to the clock input terminal C of each flip-flop of the shift register sections 22A and 22B. The data input / output mode switching circuit 27 includes an AND gate 28,
29 and an inverter 30. The data switching circuit 27 has a control signal for switching between processing of four series of digital video signals (that is, the first mode) and processing of three series of digital video signals (that is, the second mode). And a clock input terminal CLK to which a clock signal is given from a controller (not shown). 3 / 4C
The H terminal is the input terminal of the inverter 30 and the AND gate 2.
9 is connected to one input end. In addition, the inverter 3
The output terminal of 0 is connected to one input terminal of the AND gate 28. Further, the clock input terminal CLK is connected to the other input terminals of the AND gates 28 and 29, respectively. The output terminal of the AND gate 28 has a first shift register section 22A for four series of digital video signal inputs.
Further, the output end of the AND gate 29 is connected to the second shift register section 22B.

The shift register units 22A and 22B are provided.
The inverted output bar Q of the flip-flops that make up
Output terminal F₁, F₂It was taken out as ... and this output
Edge F ₁, F₂... is the digital data memory shown in FIG.
It is connected to 23.

Next, the operation of the shift register 22 will be described.
This will be described with reference to FIGS. 5 and 6. When the digital video signal is a four-series digital video signal consisting of an R signal, a G signal, a B signal, and a W signal, that is, when the digital video signal is operated in the first mode, as shown in FIG.
A "low" voltage signal is provided. This is 3 / 4CH
This can be accomplished by connecting the terminal to ground potential. Alternatively, a relatively “low” voltage may be applied from the outside.

When the clock signal from the clock input terminal CLK rises while the "high" signal is input from the start pulse input terminal STH of the shift register section 22, the AND circuit of the data input / output mode switching circuit 27 is operated. The output of the gate 28 becomes "high", and the AND gate 2
The output of 9 becomes "low". Therefore, the operation first shift register section 22A is an inverted output, a bar Q that is, the output of "high" is output to the output terminal F ₁ to F _4. Further, a "high" signal is output to each of the four output terminals in response to the rising edge of the pulse of the clock signal.

On the other hand, when a "low" signal is input to the 3 / 4CH terminal, for example, when the power supply voltage is connected to the 3 / 4CH terminal, the data input / output mode switching circuit 27.
The AND gate 29 outputs a "high" signal to operate the second shift register section 22B. Therefore, as shown in FIG. 6, in accordance with the rising edge of the clock signal given from the clock input terminal CLK, the three output terminals F
₁ to F ₃ signal "high" is output in the following at the rising edge of the clock signal, the signal of "high" at the output terminal of each three is output.

Therefore, 3/4 of the shift register 22 is provided.
By inputting the “high” or “low” signal to the CH terminal as described above, the shift register 22 is set to the first
It is possible to operate in either of the above mode and the second mode.

In the above-mentioned embodiments, the example in which the present invention is applied to the driving circuit of the color liquid crystal display device has been described, but the driving circuit of the display device of the present invention is not limited to the one using liquid crystal,
It can also be used in a drive circuit of another matrix type display device such as a plasma display panel.

Further, the present invention can be widely used for switching a plurality of series of digital video signals, and is not limited to the above-mentioned switching between four series digital video signals and three series digital video signals.

[0046]

According to the drive circuit of the display device of the present invention,
Since the data input / output mode switching means for switching between the first mode and the second mode is provided, the output corresponding to the digital video signals is matrixed corresponding to the two types of digital video signals of a plurality of series. It is possible to reliably assign and output to the plurality of data electrodes of the mold display device.

Therefore, it is possible to provide a drive circuit of a display device capable of supporting two kinds of digital video signals of a plurality of series without connecting a complicated data conversion circuit or the like in the preceding stage of the drive circuit.

Further, since the input digital video signal is not converted, when the drive circuit of the display device of the present invention is used, a commercially available controller is used as it is, and two types of digital video of a plurality of series are used. Can respond to signals.

By constructing the drive circuit of the display device of the present invention in the one-chip driver IC as described in claim 3, the one-chip IC can be directly incorporated in the display device of different specifications. Therefore, it is possible to standardize the IC chip that constitutes the drive circuit of the display device.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing a drive circuit of a display device according to an embodiment of the present invention and showing a state of output when operating in a first mode.

FIG. 2 is a schematic configuration diagram showing a drive circuit of a display device of one embodiment of the present invention and showing an output state when operating in a second mode.

FIG. 3 is a schematic block diagram of a drive circuit of a display device of an example.

FIG. 4 is a circuit diagram showing an example of data input / output mode switching means in the drive circuit of the display device of the embodiment.

FIG. 5 is a diagram showing a timing chart when the data input / output mode switching circuit shown in FIG. 4 operates in the first mode.

6 is a diagram showing a timing chart when the data input / output mode switching circuit shown in FIG. 4 operates in a second mode.

FIG. 7 is a schematic configuration diagram for explaining an example of a color liquid crystal display device.

8A and 8B are schematic plan views showing color arrangement patterns in a color liquid crystal display panel.

FIG. 9 is a schematic block diagram for explaining a drive circuit of a conventional liquid crystal display device.

FIG. 10 is a schematic block diagram showing another example of a drive circuit of a conventional color liquid crystal display device.

[Explanation of symbols]

21 ... display device driving circuit 22: shift register (data input mode switching means) 22A ... first shift register section 22B ... second shift register section 27 ... data output mode switching circuit D _a to D _d ... Digital Video signal input terminal, ... Output terminal

Claims (3)

[Claims] 1. A drive for a display device, wherein a plurality of series of digital video signals are input, and outputs corresponding to the input plurality of series of digital video signals are assigned to a plurality of data electrodes of a matrix type display device and output. In the circuit, when an x-series (x is an integer of 3 or more) digital video signal is applied to x data input terminals, an output corresponding to the x-series digital video signal is output to the plurality of data electrodes. When a y-series (y is an integer of 2 or greater and smaller than x) digital video signal assigned to the first mode is assigned to y data input terminals, the y-series digital video signal is output. A drive circuit for a display device, comprising a data input / output mode switching means for switching a corresponding output to a second mode in which a plurality of data electrodes are assigned and output. 2. The drive circuit for a display device according to claim 1, wherein the x is 4 and the y is 3. 3. The drive circuit for a display device according to claim 1, wherein the drive circuit is configured in a one-chip driver IC.