JPH1155514A - Image processing unit and image processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the image processing unit by which gradation expression in an output image is improved and to provide its image processing method. SOLUTION: A clock 4×VCLK whose period is a multiple of a period of a video block is counted for a period by 3 pixels of input image data 112, an OR circuit 103 generates a signal in a timing different from each pixel for a period by 3 pixels depending on a count and a signal 117 is produced by interleaving the clock 4×VCLK depending on the generated signal and multi- value data 113 in 3-bit obtained from the input image data 112 are converted into serial data 119 denoting density data according to the signal 117.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image processing apparatus and an image processing method for expressing, for example, one pixel by area gradation.

[0002]

2. Description of the Related Art Conventionally, an image processing apparatus such as a printing apparatus which handles multi-valued image data has a multi-valued data processing circuit which divides one pixel into four parts in order to express it by area gradation and outputs it as video signals. . For example, as shown in FIG. 5, the multi-valued data conversion decoder 3 outputs one pixel of multi-valued data PX.
DATA [1: 0] is decoded, and the resulting data PDEC [3: 0] is converted into serial data by the parallel / serial conversion circuit 4 in accordance with a video clock (4 × VCLK) signal having a frequency four times as high as one pixel. There is a multi-value data processing circuit that outputs a converted video signal as a video signal Video corresponding to the one pixel.

[0003]

However, in the circuit having the above configuration, for example, when the multi-valued data is 2 bits, the number of gradations that can be expressed is four, and one pixel has an area gradation. If you divide it into four to represent it,
The number of gradations that can be expressed is five. Therefore, the two gradation expressions do not have a one-to-one correspondence, and the multi-value data is 01b,
10b (where b is a binary number; the same applies hereinafter)
An accurate density value cannot be expressed by the area gradation expression. For this reason, when expressing 01b and 10b, they are unavoidably expressed with different density (gradation) values.

Accordingly, an object of the present application is to provide an image processing apparatus and an image processing method capable of improving the gradation expression of an output image.

[0005]

In order to achieve the above object, an image processing apparatus according to the present invention has the following configuration.

That is, an image processing apparatus for processing input image data input in synchronization with a video clock, wherein a count N times the video clock is counted for a period of M pixels of the input image data Means, a signal generating means for generating a signal at a different timing for each pixel within the period of the M pixels according to a count value of the counting means, and a signal generated by the signal generating means, Thinning means for thinning out the N-times clock; and converting means for converting M-bit multi-value data obtained from the input image data into serial data representing density data in accordance with a signal obtained from the thinning means. It is characterized by the following.

[0007] An image processing apparatus for processing input image data input in synchronization with a video clock,
Counting means for counting a clock N times the video clock for a period of M pixels of the input image data, and different timings for each pixel within the period of the M pixels in accordance with the count value of the counting means A signal generating means for generating a signal in accordance with the signal, and converting means for converting M-bit multi-valued data obtained from the input image data into serial data representing density data in accordance with the signal generated by the signal generating means. , Is provided.

In order to achieve the above object, an image processing method according to the present invention has the following configuration.

That is, an image processing method for processing input image data input in synchronization with a video clock, wherein a clock N times the video clock is counted for a period of M pixels of the input image data, According to the counted value, 1 within the period of the M pixels.
A first signal is generated at a different timing for each pixel, a second signal is generated by thinning out the N times clock according to the generated first signal, and a second signal is generated according to the second signal. M obtained from the input image data
It is characterized in that multi-bit data is converted into serial data representing density data.

Alternatively, there is provided an image processing method for processing input image data input in synchronization with a video clock,
A clock N times the video clock is counted for a period corresponding to M pixels of the input image data, and a signal is generated at a different timing for each pixel within the period corresponding to the M pixels according to the counted value. And converting the M-bit multi-value data obtained from the input image data into serial data representing density data in accordance with the generated signal.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an image processing apparatus according to the present invention will be described below with reference to the drawings. In each of the embodiments described below, the present invention is applied to a multi-value data processing circuit in a laser driver circuit provided in a laser beam printer as a typical image processing apparatus, but is not limited thereto. Needless to say. Also, the present invention is applied to a multi-valued data processing circuit in which multi-valued data is 2 bits and multi-valued data of one pixel is divided into four, but the present invention is not limited to this. Needless to say.

<First Embodiment> FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a block diagram illustrating a multi-value data processing circuit of the image processing apparatus according to the first embodiment.

In the figure, 101 is a counter, 102 is a decoder, 103 is an OR circuit, 104 is an inverter, 105 is a flip-flop circuit, 106 and 107 are AND circuits, 108 is a multi-level data conversion decoder, and 109
Is a parallel-serial conversion circuit.

Reference numeral 111 denotes a video clock (4 × VCLK) signal having a frequency four times as high as one pixel, and 112 denotes 2b
It is multi-valued image data (PXDATA [1: 0]) signal, and 113 is decoded pixel data (PDEC [2:
0]) and 114 are count data (CNT [3:
0]) 117 is a modulated video clock (3 times)
× VCLK) signal, a load signal (LOAD) 118 for loading pixel data from the multi-level data conversion decoder,
Reference numeral 119 denotes a video signal (Video).

Next, the operation of the multi-level data processing circuit of FIG. 1 having the above configuration will be described with reference to FIG.

FIG. 2 is a timing chart showing the operation of the multilevel data processing circuit according to the first embodiment of the present invention.

The counter 101 has a 4 × VCLK signal 11
1 is constantly counted from 0h to Bh (h represents a hexadecimal number).

Output CNT [3: 0] of counter 101
(114) is decoded by the decoder 102, and when the counter value is 2h, 5h, 8h, Bh, respectively, the signal (DE)
C2, DEC5, DEC8, and DECB). D
The signals of EC2, DEC5, and DEC8 are output from the OR circuit 103.
The OR is taken, and the flip-flop 105 outputs 4 ×
It is sampled at the falling timing of VCLK.

Further, a logical product of the inverted output 116 of the flip-flop 105 and the 4 × VCLK signal is taken by the AND circuit 106 to generate a 3 × VCLK signal 117. Therefore, when the count value of the 4 × VCLK signal is 2h, 5h, 8h by the counter 101, the AND circuit 10
3 × V by thinning out by AND operation with 6
A CLK signal 117 is generated. Also, the DECB signal 1
15 clears the counter 101.

The multi-valued data conversion decoder 108 has 2 bi
t multi-valued image data 112 is converted to 3-bit pixel data 11
Convert to 3. Specifically, 2-bit multivalued image data 0
0b, 01b, 10b, and 11b are 000b, 001b, and 110 as 3-bit pixel data 113, respectively.
b, 111b. That is, as the value of the multi-valued image data increases, the number of bits where “1” is set increases.

The AND circuit 107 calculates the logical product of the lower two bits of the output of the counter 101 to generate a load signal 118. Thereby, the AND circuit 10
7 generates a load signal 118 every four counts by the counter 101.

Finally, the parallel / serial conversion circuit 10
9 loads the 3-bit pixel data 113 from the multi-level data conversion decoder 108 at the generation timing of the load signal 118, sequentially converts the 3-bit pixel data 113 while shifting it according to the 3 × VCLK signal 117, and outputs it as a video signal 119.

In the multi-valued data processing circuit that performs such an operation, the input 2-bit multi-valued image data 112
Is 01b for three or more pixels consecutively, the density value indicated by the video signal 119 is 1/4, 1/4, 2/4, 1 /
4, 1/4, 2/4,..., The average value of these values is calculated as (1/4 + 1/4 + 2/4 +...) ÷ 3 ≒ 1/3. Tone expression can be performed by using an appropriate density value.

When the 2-bit multi-valued image data is 10 bits continuously for three or more pixels, the value of the video signal 119 is 3/4, 3/4, 2/4, 3/4, 3/4, 2 /
,..., The average value of these values is calculated as (3/4 + 3/4 + 2/4 +...) ≒ 3 階 調 2/3. it can.

As described above, according to the present embodiment, even when the 2-bit multi-valued image data is 01b and 10b, if the multi-valued image data continues for three or more pixels, the average Then, since an appropriate density value can be obtained, the quality of an output image represented by a video signal (Video) output from the multi-value data processing circuit can be improved.

<Second Embodiment> In the first embodiment described above, the clock input to the parallel / serial conversion circuit 109 was manipulated in order to improve the quality of the output image. In the present embodiment, the quality of the output image is improved by operating the input pixel data instead of the clock. Hereinafter, the configuration different from the first embodiment will be mainly described. The main difference is that another one-stage selector is added in the parallel / serial conversion circuit 309.

FIG. 3 is a block diagram of a multi-value data processing circuit of an image processing apparatus according to a second embodiment of the present invention.

In the figure, 301 is a counter, 302 is a decoder, 303 is an OR circuit, 307 is an AND circuit, 308 is a multi-level data conversion decoder, and 309 is a modified parallel-serial conversion circuit.

Reference numeral 311 denotes a video clock (4 × VCLK) signal having a frequency four times the frequency of one pixel, and reference numeral 312 denotes 2b
it multi-value image data (PXDATA [1: 0]), 3
13 is the decoded pixel data (PDEC [2:
0]) and 314 are count data (C
NT [3: 0]), 318 is a load signal (LOAD),
320 is an operation signal (OPS), and 319 is a video signal (Video).

Next, the operation of the multi-level data processing circuit of FIG. 3 having the above configuration will be described with reference to FIG.

FIG. 4 is a timing chart showing the operation of the multilevel data processing circuit according to the second embodiment of the present invention.

The counter 301 has a 4 × VCLK signal 31
1 is always repeated from 0h to Bh.

The decoder 302 decodes the output CNT [3: 0] of the counter 301 and outputs signals (DEC2, DEC2, DEC2,
5, DEC8, DECB). DEC2, DE
The OR of the signals of C5 and DEC8 is taken by the OR circuit 303 to become an operation signal (OPS) 320. Also, DEC
The B signal 315 clears the counter 301. Therefore, when the count value of the counter 301 is 2h, 5h, 8h, the OR circuit 303 generates the operation signal (OPS) 320.

Further, the multi-level data conversion decoder 308
The multi-bit image data 312 of 2 bits is converted into the pixel data 313 of 3 bits. Specifically, 2-bit multi-value image data 00b, 01b, 10b, and 11b (where b is 2
Indicates a base number. The same applies to the following) but 3-bit pixel data 11
3 as 000b, 001b, 110b, 1
11b. That is, as the value of the multi-valued image data increases, the number of bits where “1” is set increases.

The lower 2 bits of the output of the counter 301 are ANDed by an AND circuit 307 to generate a load signal 318. Thereby, the AND circuit 307
Generates a load signal 318 every four counts.

Finally, the parallel / serial conversion circuit 30
9 to load the 3-bit pixel data 313 into the load signal 318
, And serially converted while sequentially shifting according to the 4 × VCLK signal 311, and output as a video signal 319. However, when the operation signal (OPS) 320 is generated when the video signal 319 is output, the data is output without shifting.

In the multi-valued data processing circuit performing such an operation, the input 2-bit multi-valued image data is 01
In the case of b, the value of the video signal 119 is 1/4, 1/4,
2/4, 1/4, 1/4, 2/4,..., The average of these values is calculated as: (1/4 + 1/4 + 2/4 +...) {3} 1/3, and gradation can be expressed by an appropriate density value.

When the 2-bit multivalued image data is 10b consecutively for three or more pixels, the value of the video signal 119 is 3/4, 3/4, 2/4, 3/4, 3/4, 2 /
,..., The average value of these values is calculated as (3/4 + 3/4 + 2/4 +...) ≒ 3 階 調 2/3. it can.

As described above, also in the present embodiment, when the 2-bit multi-valued image data is 01b and 10b and the multi-valued image data is continuous for 3 pixels or more, an appropriate density is obtained by averaging. Since the value can be obtained, the video signal (Video) output from the multi-level data processing circuit is obtained.
It is possible to improve the quality of the output image represented by o).

<Other Embodiments> In the above-described first embodiment, the 4 × VCLK signal is thinned out when the count value of the counter 101 is 2h, 5h, and 8h. However, the present invention is not limited to this. Since it is sufficient that the positions to be decimated are different between three pixels, for example, the count value is (2
h, 4h, 9h), (1h, 6h, 8h), or (1h, 4
h, Ah), etc.

In the second embodiment, the counter 30
The data was operated when the count value of 1 was 2h, 5h, and 8h. However, the present invention is not limited to this. For example, the operation position may be different between three consecutive pixels. , 4h, 9h), (1h, 6h,
8h) or (1h, 4h, Ah).

In the first and second embodiments, the output value of the multi-level data conversion decoder is changed from 00b → 00
0b, 01b → 001b, 10b → 110b, 11b →
Although the configuration is 111b, it is needless to say that the configuration is not limited to this.

Even if the present invention is applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), an apparatus (for example, a copying machine, a facsimile, etc.) comprising one device Equipment)
May be applied.

Further, an object of the present invention is to provide a storage medium storing a program code of software for realizing the functions of the above-described embodiments to a system or an apparatus, and to provide a computer (or CPU) of the system or apparatus.
And MPU) read and execute the program code stored in the storage medium.

In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention.

As a storage medium for supplying the program code, for example, a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, CD
-R, magnetic tape, non-volatile memory card, ROM, etc. can be used.

When the computer executes the readout program code, not only the functions of the above-described embodiment are realized, but also the OS (Operating System) running on the computer based on the instruction of the program code. ) And the like perform part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written into a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, based on the instruction of the program code, It goes without saying that a CPU or the like provided in the function expansion board or the function expansion unit performs a part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

[0049]

As described above, according to the present invention,
An image processing apparatus and an image processing method capable of improving the gradation expression of an output image are provided.

[0050]

[Brief description of the drawings]

FIG. 1 is a block diagram of a multi-value data processing circuit of an image processing apparatus according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the multi-level data processing circuit according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a multi-value data processing circuit of an image processing apparatus according to a second embodiment of the present invention.

FIG. 4 is a timing chart illustrating an operation of a multi-level data processing circuit according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a multi-value data processing circuit as a conventional example.

FIG. 6 is a diagram showing a conversion example of multi-value data as a conventional example.

[Explanation of symbols]

 101, 301 Counter 102, 302 Decoder 103, 303 OR circuit 104 Inverter 105 Flip-flop 106, 107, 307 AND circuit 108, 308 Multi-level data conversion decoder 109, 309 Parallel / serial conversion circuit

Claims (7)

[Claims] 1. An image processing apparatus for processing input image data input in synchronization with a video clock, wherein a count for counting a clock N times the video clock for a period of M pixels of the input image data Means, a signal generating means for generating a signal at a different timing for each pixel within a period of the M pixels according to a count value of the counting means, and a signal generated by the signal generating means, Thinning means for thinning out the N-times clock; and converting means for converting M-bit multi-valued data obtained from the input image data into serial data representing density data in accordance with a signal obtained from the thinning means. An image processing apparatus characterized by the above-mentioned. 2. An image processing apparatus for processing input image data input in synchronization with a video clock, wherein a count that counts a clock N times the video clock for a period of M pixels of the input image data. Means, a signal generating means for generating a signal at a different timing for each pixel within a period of the M pixels according to a count value of the counting means, and a signal generated by the signal generating means, Conversion means for converting M-bit multi-value data obtained from the input image data into serial data representing density data;
An image processing apparatus comprising: 3. The image processing apparatus according to claim 1, further comprising decoding means for decoding the (M-1) -bit input image data into M bits. 4. The signal generating means according to claim 1, wherein said signal generating means is a decoder for generating a signal each time the count value of said counting means reaches one of M types of predetermined values. 3. The image processing device according to 2. 5. The apparatus according to claim 1, wherein the conversion means generates a signal having a pulse width substantially proportional to a density by serially converting the M-bit multi-value data. Image processing device. 6. An image processing method for processing input image data input in synchronization with a video clock, comprising: counting a clock N times the video clock for a period of M pixels of the input image data; According to the counted value, a first signal is generated at a different timing for each pixel within the period of the M pixels, and the N times clock is generated according to the generated first signal. An image processing method comprising: generating a second signal by thinning out; and converting M-bit multi-valued data obtained from the input image data into serial data representing density data according to the second signal. . 7. An image processing method for processing input image data input in synchronization with a video clock, comprising: counting a clock N times the video clock for a period of M pixels of the input image data; In accordance with the counted value, a signal is generated at a different timing for each pixel within the period of the M pixels, and according to the generated signal, an M-bit multi-value obtained from the input image data is generated. An image processing method comprising converting data into serial data representing density data.