JPH1155229A - Transmission path switching device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the generation of a data error at the time of system switching even when the phase difference of an input signal is restored by locking a window in a state, that the phase difference of the input signal is outside the window, at the time of system switching in this state. SOLUTION: A read control circuit 7 generates a window and a read control signal 113 from an output signal 111(that is, a selected system FP(frame phase) signal 102 or 105) of a selector 3, an in-device FP signal 110, and an in-device CLK signal 109. The window and the read control signal 113 are not newly generated just after system switching, and the new generation is operated after the completion of the phase pull-in of a PLL circuit 8, that is, after the input of a pull-in completion signal 112 outputted by a pull-in detecting circuit 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission line switching device, and more particularly to a transmission line switching device which switches data signals of a 0-system transmission line and a 1-system transmission line without instantaneous interruption, and simultaneously converts a frame phase signal and a clock of a transmission line side into a frame phase signal of the device side. And a transmission line switching device having a function of switching to a clock.

[0002]

2. Description of the Related Art Conventionally, this type of transmission line switching device, when transmitting a data signal using a redundant 0-system transmission line and a 1-system transmission line, uses the 0-system and 1-system transmission lines on the transmission line receiving side. At the same time as switching without instantaneous interruption, a device side clock or the like synchronized in phase with a transmission line side clock or the like is generated and supplied to the device. FIG. 5 is a block diagram showing a conventional example.

In FIG. 5, an elastic memory (hereinafter referred to as an ES memory) for temporarily storing input data signals 101 and 104 from the 0-system and 1-system transmission lines, respectively.
4 and 5, and frame phase signals (hereinafter referred to as FP signals) 102 and 105 and clock signals (hereinafter referred to as CLK signals) 103 and 106 from the 0-system and 1-system transmission lines, respectively, to be supplied to the ES memories 4 and 5 respectively. Write control circuits 1 and 2 for generating read control signals, a selector 6 for selecting one of the data signals read from the ES memories 4 and 5 by a system select signal 107 and outputting the selected signal, and a 0-system and 1-system transmission FP signals 102 and 105 from the road
7, a selector 3 for selecting and outputting one of them, and an output signal of the selector 3, and an in-device frame phase signal (hereinafter referred to as an in-device FP signal) 11 synchronized with the output signal
0 and an internal clock signal (hereinafter referred to as an internal CLK signal) 109, and an output signal of the selector 3 based on the output signal of the selector 3 and the internal CLK signal 109, that is, a selected FP signal. A read control circuit 11 for generating a read control signal 113 having a predetermined phase difference (1/2 bit of a window width for absorbing the phase difference between the input data signals 101 and 104) and supplying the read control signal 113 to the ES memories 4 and 5; It is composed of

Next, the operation will be described. The memory capacity of the ES memories 4 and 5 is determined by the allowable phase difference between the input data signals 101 and 104 from the 0-system and 1-system transmission lines, that is, the allowable phase difference for switching the input data signals without instantaneous interruption. If n bits, each memory capacity is 2
It has n bits. The input data signals 101 and 104 are output from the write control circuits 1 and 2 according to the ES memories 4 and 5.
At this time, and at this time, they are respectively written with the phases of the FP signals 102 and 105 indicating the head of the input data signal.

The input data signals 101 and 104 written in the ES memories 4 and 5 are read in the same phase by the same read control signal 113. The read control signal 113 is generated by the read control circuit 11, but the FP signal on the side selected by the selector 3, for example, if the 0 system is selected, the read phase is the FP signal 102 and the phase delayed by n bits from the FP signal 102. In addition, read control signals having the same period are generated. Accordingly, for the input data signal 104 of the first system, the phase tolerance of ± n bits, that is, ± n
A bit-width window will be formed.

Therefore, if the phase difference between input data signals 101 and 104 is within this window, system selection signal 10
Even if the system switching is performed by using 7, the read data signals of the ES memories 4 and 5 have the same phase, so that no error occurs in the output data signal 108. FP signal 11 in the device
0, the PLL circuit 8 that outputs the in-device CLK signal 109 is synchronously controlled to follow the FP signal on the system switching side, and synchronizes with the FP signal on the switching side after a predetermined pull-in time after system switching.

[0007]

As described above, in the conventional example, there is no problem if the phase difference between the input data of system 0 and system 1 is within ± n bits, that is, within the range of the window. When the number of bits exceeds ± n bits, the following problem occurs.

When the switching is performed with a phase difference of ± n bits or more (outside the window range), there is a time difference between the generation time of the read control signal and the pull-in time of the PLL circuit. The pull-in time of the PLL is not uniquely determined by the performance of the PLL and the variation or deterioration of the analog parts, but a predetermined time is required. However, since the read control signal is generated digitally, it is immediately generated in the next frame. You.

FIG. 6 is a timing chart showing the phase relationship of each signal when system switching is performed with a phase difference of ± n bits or more. When the phase difference between the working data signal 101 and the standby data signal 104 is outside the window of ± n bits as shown in the left side of FIG. In the data 108, an instantaneous interruption data error occurs. However, after the switching, as shown in the center of FIG.
Thus, the phase state and the window state shown in FIG. Therefore, the output data 10
8 is normal data.

The in-apparatus FP signal 110 follows the FP signal 105 in accordance with the pull-in operation of the PLL 8, and is stabilized, and becomes the state shown in the right side of FIG. In this state, the read control signal 113
Since the phase relationship between the FP signal 105 and the window is distorted as shown in the figure, and the phase difference of the data signal 101 does not enter the window even if it is restored to within ± n bits as shown by the dotted line, the system switching is performed. In this case, an error occurs in the output data signal.

That is, if the system switching is performed in a state where the 0, 1 system has a phase difference of ± n bits or more, the 2n-bit window absorbing the phase difference of the 0, 1 system becomes the phase with the selected FP signal. There is a problem that even if the relationship is shifted and locked, and the phase difference between the 0 and 1 systems is restored within ± n bits, an instantaneous interruption occurs at the time of system switching.

[0012]

According to the present invention, there is provided a transmission line switching apparatus comprising: first and second memories for temporarily storing input data signals from a 0-system transmission line and a 1-system transmission line to absorb a phase difference between the input data signals; And second and third write control signals to be supplied to the first and second elastic memories, respectively, from the elastic memory of FIG. 1 and the frame phase signal and the clock signal from the 0-system and 1-system transmission lines. Write control circuit, a first selector for selecting and outputting one of data signals read from the first and second elastic memories by a system selection signal, and the 0-system and 1-system transmission lines A second selector for selecting and outputting one of the frame phase signals from the second selector according to the system selection signal, and receiving an output signal of the second selector and inputting the output signal And a PLL circuit for outputting the in-device frame phase signal and the in-device clock signal; and the output signal of the second selector from the output signal of the second selector and the in-device clock signal, that is, the selected frame. Generating a read control signal having a predetermined phase difference (1/2 bit of the window width of the first and second elastic memories for absorbing the phase difference of the input data) with respect to the phase signal; And a read control circuit for supplying to the second elastic memory.
In the transmission line switching device for switching between the system and the system 1 transmission line without instantaneous interruption, the read control circuit outputs the read control signal immediately after switching the first and second selectors by the system selection signal. The PLL is not newly generated.
There is provided means for generating a new read control signal after completion of the pull-in of the circuit. More specifically, the read control circuit receives the internal clock signal and divides the clock signal by the cycle of an initialization signal. The read control signal and the elastic memory are output from the counter. A decoder for outputting a window signal for setting a window width of the above, and a window signal, an output signal of the second selector, and a pull-in completion signal indicating completion of pull-in of the PLL circuit. A comparison circuit that outputs the initialization signal according to the phase of the output signal of the second selector at that time until the next input after switching, an output signal of the second selector and a frame signal in the device. And a pull-in detection circuit that outputs the pull-in completion signal indicating completion of the pull-in of the PLL circuit when the two phases match with each other. Further, the pull-in completion signal may be output from the PLL circuit. Further, the phase difference between the frame phase signals from the 0-system and 1-system is monitored, and an alarm is generated when a state in which the phase difference becomes larger than the window width set in the elastic memory continues for a predetermined period. A phase difference monitoring circuit may be added.

[0013]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In FIG. 1, input data signals 101 and 104 from the 0-system and 1-system transmission lines are respectively stored in elastic memories (referred to as ES memories) 4 and 5.
Write control signals supplied to the ES memories 4 and 5 from frame phase signals (hereinafter referred to as FP signals) 102 and 105 and clock signals (hereinafter referred to as CLK signals) 103 and 106 from the 0-system and 1-system transmission lines, respectively. And a selector 6 for selecting and outputting one of the data signals read from the ES memories 4 and 5 by the system selection signal 107, and the FP signal 102 from the 0-system and 1-system transmission lines. , 105 by selecting one of them by a system selection signal 107 and outputting the selected signal, an in-device frame phase signal (hereinafter referred to as an in-device FP signal) 110 which receives an output signal 111 of the selector 3 and synchronizes with the output signal. Internal clock (hereinafter referred to as internal CLK signal) 10
9 and the output signal 1 of the selector 3
A read control signal 113 having a predetermined phase difference with respect to the output signal of the selector 3, that is, the selected FP signal, is generated from the signal 11 and the internal CLK signal 109 and supplied to the ES memories 4 and 5. At the time of system switching by 107, means for temporarily holding the phase of the output read control signal 113 after switching, and for canceling this holding by a pull-in completion signal 112 indicating that the PLL circuit 8 has completed the pull-in operation. The read control circuit 7 has a phase comparison between the output signal 111 of the selector 3 and the FP signal 110 in the device, and a pull-in completion signal 11
2 is provided.

The PLL circuit 8 has an internal CLK signal 109 having the same frequency as the CLK signals 103 and 106 on the transmission line side.
A voltage controlled oscillator VCO 83 that outputs
The frequency of the signal 109 is divided and the FP signals 102 and 10 on the transmission path side are divided.
5, a frequency divider 81 for outputting an in-device FP signal 110 having the same frequency as that of the input device 5, and an output signal 111 of the selector 3, that is, an FP signal from a selected transmission path, is input thereto. A control circuit 82 performs phase comparison, controls the phase of the VCO 83 with this output, and synchronizes.

FIG. 2 is a block diagram showing an internal circuit of the read control circuit 7. A counter 72 which receives the internal CLK signal 109 and divides the frequency by synchronizing the initialization signal 701, a window signal 702 for setting a window width of the ES memory from an output signal of the counter 72, and a read control signal 113. , And the window signal 702 and the output signal 111 of the selector 3 are input, and it is monitored whether the window signal 702 is out of the range.
And a comparison circuit 71 that outputs an initialization signal 702 corresponding to the phase of the output signal 111 of the first embodiment.

If the pull-in completion signal 112 can be obtained from the internal circuit of the PLL circuit 8, the pull-in detection circuit 9
Is unnecessary.

Further, as shown by the dotted line, the FP signal 10
A phase difference monitoring circuit 10 for monitoring the phase difference between the signal lines 2 and 105 and generating an alarm when the state in which the phase difference is larger than the window width continues for a predetermined period is added to prevent a data error from occurring due to system switching. You may make it notify in advance.

Next, the operation will be described with reference to FIG. FIG.
1 is a timing chart showing the phase relationship between the signals in FIG. 1, where the phase difference between the 0 and 1 system data signals 101 and 104 is ± n.
Normal state within bits. As shown in the state on the left side of FIG.
Since the phase difference is absorbed by the memories 4 and 5, and the phases of the read data signals are aligned, no instantaneous interruption occurs in the output data 108. After the pull-in of the PLL circuit 8, the state shown on the right side of the figure is reached, the read control signal 113 is generated by the FP signal 105, and the window is shifted. Also, the FP signal 110 in the device is changed to the FP signal 105 by the pull-in of the PLL circuit 8.
Will be synchronized with.

Next, FIG. 4 is the same timing chart as FIG. 3, but at the time of abnormality when the phase difference between the 0 and 1 system data signals 101 and 104 becomes ± n bits or more. As shown in the state on the left side of the figure, when switching to the first system is performed by the system switching signal 107, the phase difference is not completely absorbed by the ES memories 4 and 5 because the data signal 104 of the first system is outside the window.
The output data 108 causes a data error. Immediately after this switching, as shown in the state in the center of FIG.
Reference numeral 13 holds the phase state and does not generate a window.
In this state, the output data 108 continues to generate an error.

However, as shown in the state on the right side of FIG.
When the circuit 8 completes the pull-in, the phase of the read control signal is switched by the switched FP signal 105 due to the generation of the pull-in completion signal 112, and a new window is generated. The in-apparatus FP signal 110 is synchronized with the FP signal 105. In this state, if the phase of the 0-system data signal 101 is restored to within ± n bits, the output data 1 will be maintained even if the system is switched to 0-system.
No error occurs at 08.

[0023]

As described above, according to the transmission line switching apparatus of the present invention, when system switching is performed in a state where the phase difference of the input signal is out of the window, a new window is not generated immediately after the switching. Since a new window is generated after the completion of the pull-in of the PLL circuit that generates the internal clock, the window is not locked in the out-of-window state. There is an effect that instantaneous interruption switching becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a read control circuit of FIG. 1;

FIG. 3 is a timing chart at the time of switching within a window, showing a phase relationship between signals in FIG. 1;

FIG. 4 is a timing chart showing a phase relationship between signals in FIG. 1 at the time of switching outside a window.

FIG. 5 is a block diagram showing a conventional example.

FIG. 6 is a timing chart showing a phase relationship between signals in FIG. 4;

[Explanation of symbols]

 1, 2 write control circuit 3, 6 selector 4, 5 ES memory 7 read control circuit 8 PLL circuit 9 pull-in detection circuit 10 phase difference monitoring circuit 101, 104 input data signal 102, 105 FP signal 107 system selection signal 108 output data signal

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toru Matsuda 1-403 Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Within NEC Telecommunication System Co., Ltd. 403-chome Inside NEC Telecom System Co., Ltd.

Claims (4)

[Claims] 1. A first and a second elastic memory for temporarily storing input data signals from the 0-system and 1-system transmission lines and absorbing a phase difference between the input data signals, respectively, and the 0-system and 1-system transmission. First and second write control circuits for generating write control signals to be supplied to the first and second elastic memories from a frame phase signal and a clock signal from a path, respectively, and the first and second write control circuits. And a first selector for selecting and outputting one of the data signals read out from the elastic memory by a system selection signal and a frame phase signal from the system 0 and system 1 transmission lines by the system selection signal. A second selector for selecting and outputting an output signal of the second selector, an in-apparatus frame phase signal synchronized with the output signal, and an in-apparatus frame phase signal. A PLL circuit for outputting a clock signal, and a predetermined phase difference (the predetermined phase difference) between the output signal of the second selector, that is, the selected frame phase signal, based on the output signal of the second selector and the internal clock signal. A read control signal having a half of the window width of the first and second elastic memories for absorbing the phase difference of the input data is generated and supplied to the first and second elastic memories. A transmission control circuit for switching between the 0-system and 1-system transmission lines without instantaneous interruption, wherein the read control circuit performs system switching of the first and second selectors by the system selection signal. Means for generating a new read control signal after the completion of pull-in of the PLL circuit without performing a new generation of the read control signal to be output immediately after the execution; A transmission line switching device characterized by the above-mentioned. 2. The read control circuit according to claim 1, wherein the read control circuit receives the internal clock signal and divides the clock signal by the cycle of an initialization signal, and outputs the read control signal and a window of the elastic memory from an output signal of the counter. A decoder for outputting a window signal for setting a width; a window signal, an output signal of the second selector, and a pull-in completion signal indicating completion of pull-in of the PLL circuit, and switching from the input of the pull-in completion signal A comparison circuit that outputs the initialization signal according to the phase of the output signal of the second selector at that time until the next input time, and outputs the output signal of the second selector and the frame signal in the device. 2. The transmission line switching device according to claim 1, further comprising a pull-in detection circuit that compares the phases and outputs the pull-in completion signal when the two phases match. 3. The transmission line switching device according to claim 2, wherein said pull-in completion signal is output from said PLL circuit. 4. A phase difference between the frame phase signals from the system 0 and the system 1 is monitored, and an alarm is generated when a state in which the phase difference becomes larger than a window width set in the elastic memory continues for a predetermined period. 4. The transmission line switching device according to claim 1, further comprising a phase difference monitoring circuit for generating the phase difference.