JPH1154641A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To minimize the base resistance of a bipolar transistor, to make a base-emitter breakdown voltage controllable, and to improve hfe in a semiconductor device of a Bi-CMOS structure. SOLUTION: This device has a spacer on the side surface of a first polysilicon 7 for forming an emitter diffusion layer 21 of a bipolar transistor. The spacer is formed by superposing a thermally oxidized film 8 formed in the same step as a gate oxide film of a MOS transistor, a second polysilicon 9 formed in the same step as a gate of the MOS transistor, and a sidewall 12 of the gate of the MOS transistor. By controlling the thickness of the polysilicon 9, a distance between the layer 21 and an external base diffusion layer 14 can be controlled, thereby making a base-emitter breakdown voltage controllable without changing the characteristics of NMOS and PMOS transistors. Further, since the step of forming the polysilicon 7 comes first, the emitter diffusion layer can be formed before activating a source-drain high- concentration diffusion layer of the MOS transistor, thereby realizing high hfe.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a Bi-CMOS device, and more particularly, to a structure and a manufacturing method of a bipolar transistor.

[0002]

2. Description of the Related Art Hitherto, various structures have been proposed in a BiC-MOS semiconductor device for realizing high performance of a bipolar element without requiring many steps. One of them is a technique for forming an emitter diffusion layer and an external base diffusion layer for the purpose of reducing the area and the base resistance. As a first conventional technique, a technique described in Japanese Patent Application Laid-Open No. 2-101177 will be described. First, as shown in FIG. 9A, after a selective oxide film 101 for element isolation and a gate oxide film 102 are formed on a main surface of a silicon substrate 100, the gate oxide film 102 in a bipolar transistor formation region is removed. , P-type polysilicon 104 and silicon oxide film 105 are sequentially formed. Next, as shown in FIG. 9B, the two-layered film of the P-type polysilicon 104 and the silicon oxide film 105 is processed by using the photo-etching technique to form the base extraction electrode 4A. Next, an external base diffusion layer (P-type semiconductor region) 108 is formed from the P-type polysilicon 104 to the silicon substrate 100.
Is formed. This P-type semiconductor region 108 becomes an external base diffusion layer. Next, as shown in FIG. 9C, after a thin silicon oxide film 117 is formed in order to prevent diffusion of N-type impurities in the bipolar transistor portion, the embedded contact portion 106 connecting the gate and the substrate 100 is formed. In order to form a window and to form a gate electrode 18A made of a polycide barrel, an N-type polysilicon 118 and a WSi film 119 are sequentially formed.

Next, as shown in FIG. 10A, the gate electrode 18A is processed to form an N ^- diffusion layer 107 for forming a low concentration drain. Next, FIG.
As shown in (b), after the CVD oxide film is deposited, sidewall spacers 110 are formed on the side surfaces of the gate electrode 18A of the MOS and the side surfaces of the base extraction electrode 4A of the bipolar transistor by anisotropic etching. . Further, as shown in FIG. 10C, an internal base layer 112 and an emitter diffusion layer 114 formed beforehand under the emitter are formed, and the source / drain 111 of the NMOS and the emitter polysilicon 113 of N-type polysilicon are formed. Formed,
Thereafter, normal processing is performed to complete the Bi-CMOS device.

In the first prior art, a sidewall spacer 110 is formed on a side wall of a base extraction electrode 4A,
The emitter electrode 113 is formed by self-alignment with the sidewall spacer 110, and the sidewall spacer 110 is formed on the side wall of the gate electrode 18A mainly composed of a transition metal. For this reason, the base extraction electrode 4A of the bipolar transistor and the gate electrode 18A of the MOS transistor are formed in different steps, and then the sidewall spacers 110 formed on the side walls of the two electrodes are formed in the same step. become. The base extraction electrode 4A is formed of P-type polysilicon, the external base diffusion layer 108 is formed using the P-type polysilicon as a diffusion source, and the emitter diffusion layer 114 and the sidewall spacer 1 are formed.
10 is formed. for that reason,
A margin for alignment between the emitter diffusion layer 114 and the external base diffusion layer 108 is not required, the area can be reduced, and the base resistance can be reduced.

As a second prior art, a structure in which an external base is formed using polysilicon serving as a diffusion source for forming an emitter diffusion layer as a mask has been proposed. In JP-A-3-235362 as the second embodiment, as shown in FIG. 11 (a), the P-type substrate 201 N ⁺
After selectively forming the buried layer 202 and the P ⁺ buried layer 203, an N ⁻ epitaxial layer 205 is deposited. Then
After selectively forming the P-well layer 205, the N-well layer 206, and the collector extraction layer 207, a field oxide film 208 is formed by a selective oxidation method. Next, a gate oxide film 209 and a gate electrode 21 made of first polysilicon are formed.
After forming 0, an N ^- source / drain layer 211, a P ^- source / drain layer 212, and a P ^- base layer 213 for the LDD structure of the MOS transistor are formed. At this time, the P ^- source / drain layer and the base diffusion layer may be formed simultaneously.

[0006] Next, as shown in FIG.
A silicon oxide film 214 is deposited by a method, and an emitter window 215 is opened in a region where an emitter of the bipolar transistor is to be formed by anisotropic etching such as RIE. Then
The second polysilicon 216 is deposited by the CVD method, and arsenic or phosphorus is ion-implanted to be N-type doped.

Next, as shown in FIG. 12A, a second polysilicon 216 and a silicon oxide film 2 are formed by using a resist 217 slightly larger than the emitter window 216 as a mask.
14 and the gate oxide film 209 are anisotropically etched by RIE or the like to expose the silicon surface to form an emitter electrode made of the second polysilicon, and to form a side wall made of the silicon oxide film 218 on the side surface of the polysilicon electrode 210. Form. Next, as shown in FIG.
Using the resist 217, the gate electrode 210, and the side wall 218 previously used for etching the second polysilicon 216 and the silicon oxide film 214 as a mask, polon is selectively ion-implanted to form a bipolar transistor, an external base 219, and a PMOS. P ⁺ source / drain layer 220 is selectively formed. At this time, since the external base is formed in a self-aligned manner using the resist 17 as a mask, the distance B between the second polysilicon 217 constituting the emitter electrode and the external base 219 can be reduced, and therefore the area can be reduced. And the base resistance of the bipolar transactor can be reduced.

Next, as shown in FIG. 12C, after removing the resist 217, a silicon oxide film 2 is formed on the semiconductor surface.
21 are formed. Next, the N ⁺ diffusion layer 222 of the collector region of the bipolar transistor and the N ⁺ diffusion layer 223 of the NMOS are formed by ion implantation of arsenic or phosphorus, and are annealed to activate these diffusion layers. An emitter 224 is formed from the polysilicon 216 by diffusing an N-type impurity. Through the above steps, a Bi-CMOS semiconductor device is formed.

In the second prior art, the semiconductor substrate 20
1, a gate oxide film 209 of a CMOS transistor, a gate electrode 210 made of first polysilicon, a base diffusion layer 213 of a bipolar transistor, an NMOS PM
A low concentration source / drain 211 of OS is formed, and a diffusion source for forming an emitter diffusion layer 224 through a first insulating film and an opening is formed on a base diffusion layer 213 of the bipolar transistor. A second polysilicon 216 is formed, and the second polysilicon 2
An external base diffusion layer 219 is formed using 16 as a mask. Further, the first insulating film is formed of an NMOS / PMOS.
Side wall 218 of the gate electrode 210 is formed, and the high concentration source / drain 223 is formed in self alignment with the low concentration source / drain 212 by the side wall 218.

[0010]

In the first prior art, the thickness of the gate sidewall obtained from the hot carrier resistance requirement and the ON current requirement of the MOS transistor, and the side wall thickness derived from the emitter-base breakdown voltage requirement of the bipolar transistor. The film thickness must match. However, since bipolar transistors are often required to have a high breakdown voltage, the emitter-base breakdown voltage must be increased. To this end, it is necessary to increase the thickness of the side wall and increase the distance between the emitter diffusion layer and the external base diffusion layer. On the other hand, when the thickness of the side wall is increased, there is a trade-off relationship that the ON current of the MOS transistor decreases, and there is a first problem that it is difficult to realize a high breakdown voltage and a high speed operation. Also, NMO
Since the gate dimensions of the S and PMOS transistors have been miniaturized, heat treatment for activation needs to be performed at low temperature and in a short time in order to prevent the lateral diffusion of the source / drain high concentration diffusion layer. In the prior art, an emitter diffusion layer of a bipolar transistor, an NMOS and a PM
Since the source / drain high concentration diffusion layer of each OS transistor is activated by the same heat treatment, there is also a second problem that hfe of the bipolar transistor does not increase.

In the second prior art, the distance between the emitter window and the emitter electrode can be adjusted by the exposure mask, so that the distance between the emitter diffusion layer and the external base diffusion layer can be set to be equal to or greater than the side wall thickness. Therefore, the first problem described above can be avoided. However, the second problem is difficult to improve due to its structure.

According to the present invention, a Bi-CMOS in which the gate dimensions of a MOS transistor are miniaturized and the base-emitter breakdown voltage can be controlled while minimizing the base resistance of the bipolar transistor, and the hfe is high.
It is intended to obtain a semiconductor device having the configuration with a minimum number of manufacturing steps.

[0013]

According to the present invention, there is provided a semiconductor device comprising:
A bipolar transistor comprising: a collector diffusion layer formed on the semiconductor substrate; an external base diffusion layer and a base diffusion layer formed on the collector diffusion layer; an emitter diffusion layer formed on the base diffusion layer; A diffusion layer, the external base diffusion layer, and an electrode electrically connected to the emitter diffusion layer, wherein the emitter electrode is formed of first polysilicon formed in close contact with the emitter diffusion layer. A thermal oxide film formed in the same step as the gate oxide film of the MOS transistor on a side surface of the first polysilicon, a second polysilicon formed in the same step as the gate of the MOS transistor, A spacer composed of a side wall of the MOS transistor gate and an insulating film formed in the same step; Serial emitter diffusion layer and the external base over gas diffusion layer is characterized in that it is formed in self-alignment. Here, a recess is formed between the first polysilicon and the substrate, the recess protruding from both sides of the first polysilicon toward the center, and a gate oxide film of the MOS transistor is formed in the recess. It is preferable that an eaves portion in which a thermal oxide film formed in the same step is embedded is present.

Further, a method of manufacturing a semiconductor device according to the present invention
A step of forming a collector diffusion layer on the semiconductor substrate, a step of forming a base diffusion layer on the collector diffusion layer, and a first source serving as a diffusion source for forming an emitter diffusion layer on the base diffusion layer Forming polysilicon in a required pattern, forming a gate oxide film of a MOS transistor on the surface of the semiconductor substrate by thermal oxidation, and simultaneously forming the same thermal oxide film on a side wall of the first polysilicon; And a second step for the gate of the MOS transistor.
Forming a desired pattern of polysilicon and simultaneously forming second polysilicon on both sides of the thermal oxide film on the side wall of the first polysilicon, and forming sidewalls on both sides of the MOS transistor gate. Forming and simultaneously forming side walls on the side surfaces of the second polysilicon on both sides of the first polysilicon, and a spacer comprising the first polysilicon, a thermal oxide film and a second polysilicon. Forming an external base diffusion layer with the mask as a mask, and diffusing impurities from the first polysilicon into the base diffusion layer to form an emitter diffusion layer.

In this case, after the base diffusion layer is formed, an oxide film is formed on the surface of the semiconductor substrate, and a narrower opening is formed in a region where the emitter diffusion layer is formed, thereby forming the semiconductor substrate. Exposing, forming the first polysilicon in a region including the opening in a required pattern, and then removing the oxide film by isotropic etching to form the first polysilicon and the semiconductor substrate. It is preferable to include a step of forming a concave portion between them and filling the concave portion with a thermal oxide film simultaneously with the gate oxide film.

According to the present invention, a thermal oxide film in the same step as the gate oxide film of the MOS transistor and a second step in the same step as the gate of the MOS transistor are formed on the side surface of the first polysilicon for forming the emitter diffusion layer. Polysilicon and M
Since the spacer overlaps with the side wall of the OS transistor gate, the distance between the emitter diffusion layer and the external base diffusion layer can be controlled by controlling the thickness of the second polysilicon, and the characteristics of NMOS and PMOS can be controlled. , The base-emitter breakdown voltage can be controlled without changing the threshold voltage. Also,
Since the step of growing the first polysilicon and forming a predetermined pattern is the first step, the emitter diffusion layer can be formed before the activation of the source / drain high concentration diffusion layer of the MOS transistor. High hfe can be realized.

[0017]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of the first embodiment of the present invention. An N-type collector diffusion layer 3, a P-well 4, and an N-well 5 are formed on a P-type substrate (p-sub) 1, and a region is defined by a field oxide film 2. A bipolar transistor is formed in the N-type collector diffusion layer 3, and an NMOS transistor and a PMO are formed on the P well 4 and the N well, respectively.
An S transistor is formed.

Base diffusion layer 6 and P ⁺ diffusion layer (external base diffusion layer) for constituting the bipolar transistor
14 are formed. An emitter diffusion layer 21 is formed in the base diffusion layer 6 using the emitter polysilicon 7 as a diffusion source. On the side surface of the emitter polysilicon 7, a gate oxide film 8 formed in the gate oxidation step of each of the MOS transistors, the gate polysilicon 9 of the MOS transistor, and the same sidewall oxide film as the gate sidewall of the MOS transistor Numerals 12 are respectively formed as spacers, and the emitter diffusion layers 21 and the external base diffusion layers 14 are formed in a self-aligned manner by the spacers. Further, a part of the collector electrode portion of the N-type collector diffusion layer 3 is provided with the NMOS.
The same N ⁺ diffusion layer 13 as the transistor is formed.

Meanwhile, in the NMOS transistor formed in the P-well 4, the gate polysilicon 9 and the N ^- diffusion layer 10 is formed in self-alignment, a side wall oxide film 12 and the gate polysilicon 9, N ⁺ diffusion Layer 13
Are formed in a self-aligned manner. Similarly, in the PMOS transistor formed in the N well 4, the gate polysilicon 9 and the P ⁻ diffusion layer 11 are formed in a self-aligned manner, and the side wall oxide film 12, the gate polysilicon 9 and the P ⁺ diffusion layer 14 are It is formed in a self-aligned manner. A Ti silicide 15 is formed on each of the diffusion layers described above, and a silicon oxide film 16 and a BPSG film 17 are stacked on the Ti silicide 15. In the contact portion, a barrier film 18 and a W plug are buried, and an AlCu film 20 is formed as a wiring.

FIG. 2 is a plan layout view of the emitter, base and collector contacts of the bipolar transistor. In particular, the dashed line in FIG. 2 shows the emitter polysilicon film.

The manufacturing method of FIGS. 1 and 2 is shown in FIGS. First, as shown in FIG. 3A, after a field oxide film 2 is formed in a required region on a P sub-substrate 1 by using a selective oxidation method, an N-type collector diffusion layer 3, a P well 4, and an N well 5 are respectively formed. It is formed by polon and phosphorus ion implantation at an energy of 500 keV to 1500 keV. Next, a silicon oxide film 23 is formed on the entire surface by thermal oxidation.
It is formed to a thickness of 50 nm. Thereafter, boron ions are implanted at an energy of 10 to 30 keV to form the base diffusion layer 6. Further, as shown in FIG. 3B, after the silicon oxide film 23 is entirely removed, an arsenic-doped emitter polysilicon 7 is grown from 150 nm to 250 nm and a predetermined pattern is formed. To 15 nm. At this time, a silicon oxide film is also formed on the emitter polysilicon 7.

Next, as shown in FIG. 4A, a phosphorus-doped gate polysilicon 9 is grown to a thickness of 150 nm,
A degree of heat treatment is performed. As a result, impurities are diffused from the emitter polysilicon 7 to the base diffusion layer 6 to form the emitter diffusion layer 21. Thereafter, the gate polysilicon 9 is processed into a predetermined pattern. At this time, sidewalls of the gate polysilicon 9 are formed on the side surfaces of the emitter polysilicon 7. Thereafter, N ⁻ diffusion layer 10 and P ⁻ diffusion layer 11 are selectively formed by an ion implantation method according to a conventional method. Further, as shown in FIG.
After a sidewall oxide film 12 is formed to a thickness of 100 nm over the entire surface, etch back is performed to form sidewalls on the side surfaces of the emitter polysilicon 7 and the gate polysilicon 9, respectively. After that, the portion where the P-type impurity is not to be introduced is masked with the photoresist 22 and the polon fluoride is coated with 40 to 6 parts.
Ion implantation is performed at an energy of 0 keV to form an external base diffusion layer 14 of the bipolar transistor and a P ⁺ diffusion layer 14 of the PMOS, respectively.

Further, in the same manner, as shown in FIG.
N ⁺ by arsenic ion implantation at an energy of 0 to 80 keV
After the diffusion layer 13 is formed, the external base diffusion layer, the P ⁺ diffusion layer, and the N ⁺ diffusion layer are activated by a heat treatment at about 800 ° C. In FIG. 4B, the impurity of the opposite conductivity type is introduced into the emitter polysilicon. However, since the area is small and the heat treatment temperature is low, there is almost no influence on the bipolar transistor. Thereafter, a Ti silicide 15 is formed on the surface of each of the diffusion layers and the polysilicon. Thereafter, as shown in FIG. 1, a silicon oxide film 16 and a BPSG film 17 are sequentially formed, flattened by a CMP method, a contact is opened, and a barrier metal 18, a W plug 19, and an AlCu wiring are formed. The semiconductor device described above is manufactured by sequentially forming the semiconductor device.

As described above, in this embodiment, the thermal oxide film in the same step as the gate oxide film 8 of the MOS transistor,
Second polysilicon 9 in the same step as the gate of the MOS transistor, and sidewall oxide film 1 of the gate of the MOS transistor
2 will have a superimposed spacer,
The distance between the emitter diffusion layer 21 and the external base diffusion layer 14 can be controlled by controlling the thickness of the second polysilicon 9. This allows NMOS,
The base-emitter breakdown voltage can be controlled without changing the characteristics of each transistor of the PMOS. Since the first step of growing the first polysilicon 7 serving as a diffusion source for forming the emitter diffusion layer 21 and forming a predetermined pattern is the first step, the source / drain high concentration diffusion layer 13 of the MOS transistor is formed. It is possible to form the emitter diffusion layer 21 before the activation, and it is possible to realize a high hfe.

FIG. 6 is a sectional view of a second embodiment of the present invention. This embodiment is suitable for the case where a higher base-emitter breakdown voltage is required as compared with the first embodiment. This embodiment is different from the first embodiment in that an eaves portion 8a is formed between the emitter polysilicon 7 and the base diffusion layer 6. The eave portion 8a is formed of the same silicon oxide film as the gate oxide film 8 of the MOS transistor. By forming the eaves portion 8a in this manner, the outer base diffusion layer 1 is formed by the eaves portion 8a.
4 and the emitter diffusion layer 21 become longer, thereby realizing a high base-emitter breakdown voltage. FIG. 7 is a layout diagram of contacts of the bipolar transistor according to the second embodiment.

FIG. 8 is a cross-sectional view showing main steps in manufacturing the second embodiment. First, as shown in FIG. 8A, after a field oxide film 2 is formed on a P sub-substrate 1 by using a selective oxidation method, an N-type collector diffusion layer 3, a P well 4, and an N well 5 are respectively set to 500 keV and 1500 k.
After being formed by polon and phosphorus ion implantation at an energy of eV, the silicon oxide film 23 is thermally
0 nm is formed. Thereafter, boron ions are implanted at an energy of 10 to 30 keV to form the base diffusion layer 6.
Thereafter, an opening is provided by photolithography.
Next, as shown in FIG. 8B, an arsenic-doped emitter polysilicon 7 is grown from 150 nm to 250 nm, a predetermined pattern is formed, and the entire silicon oxide film 23 is removed. As a result, depressions are formed on both sides of the emitter polysilicon 7 toward the center. Thereafter, when the gate oxide film 8 is formed to have a thickness of 6 to 15 nm, the eaves portion 8a is formed. Hereinafter, the semiconductor device of FIG. 6 described above is manufactured by performing the same manufacturing method as the steps after FIG. 3B of the second embodiment.

[0027]

As described above, according to the present invention, the side surface of the first polysilicon for forming the emitter diffusion layer is
Since the gate oxide film, the gate, and the gate side wall of the MOS transistor have spacers in which the thermal oxide film, the second polysilicon, and the side wall oxide film are overlapped with each other in the same process, the thickness of the second polysilicon film , The distance between the emitter diffusion layer and the external base diffusion layer can be controlled.
The base-emitter breakdown voltage can be controlled without changing the characteristics of the OS and the PMOS. According to the present invention, the first
In the first embodiment of the present invention, about 60
%, And about 120% in the second embodiment. Further, since the step of forming the emitter diffusion layer by forming the first polysilicon in a required pattern is before the activation of the source / drain high concentration diffusion layer of the MOS transistor, it is possible to realize a high hfe. it can. According to the present invention, it is possible to obtain a value of hfe which is about twice that of the second conventional technique.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a layout diagram of contacts of the semiconductor device of FIG. 1;

FIG. 3 is a first sectional view illustrating the method of manufacturing the semiconductor device in FIG. 1 in the order of steps;

FIG. 4 is a second sectional view illustrating the method of manufacturing the semiconductor device in FIG. 1 in the order of steps;

FIG. 5 is a third sectional view illustrating the method of manufacturing the semiconductor device of FIG. 1 in the order of steps;

FIG. 6 is a longitudinal sectional view of a second embodiment of the semiconductor device of the present invention.

FIG. 7 is a layout diagram of contacts of the semiconductor device of FIG. 6;

FIG. 8 is a sectional view showing main steps of a method for manufacturing the semiconductor device of FIG. 6;

FIG. 9 is a first sectional view showing an example of a conventional semiconductor device in the order of manufacturing steps.

FIG. 10 is a second sectional view showing an example of a conventional semiconductor device in the order of manufacturing steps.

FIG. 11 is a first sectional view showing another example of the conventional semiconductor device in the order of manufacturing steps.

FIG. 12 is a second sectional view showing another example of the conventional semiconductor device in the order of manufacturing steps.

[Explanation of symbols]

1 P substrate (semiconductor substrate) 2 field oxide film 3 collector diffusion layer 4 P-well 5 N-well 6 base diffusion layer 7 first polysilicon 8 gate oxide film 9 second polysilicon 10 N ^- diffusion layer 11 P ^- Diffusion layer 12 Side wall oxide film 13 N ⁺ diffusion layer 14 P ⁺ diffusion layer (external base diffusion layer) 15 Ti silicide 16 Silicon oxide film 17 PBSG film 18 Barrier film 20 AlCu film 21 Emitter diffusion layer

Claims (5)

[Claims] In a semiconductor device having a Bi-CMOS structure having a bipolar transistor and a MOS transistor on the same semiconductor substrate, the bipolar transistor has a collector diffusion layer formed on the semiconductor substrate and a collector diffusion layer formed on the collector diffusion layer. The formed external base diffusion layer and base diffusion layer, the emitter diffusion layer formed in the base diffusion layer, and the electrodes electrically connected to the collector diffusion layer, the external base diffusion layer, and the emitter diffusion layer, respectively. Wherein the emitter electrode is made of first polysilicon formed in close contact with the emitter diffusion layer;
A side surface of the first polysilicon, a thermal oxide film formed in the same step as the gate oxide film of the MOS transistor, a second polysilicon formed in the same step as the gate of the MOS transistor, A spacer formed by a side wall of a MOS transistor gate and an insulating film formed in the same step, wherein the emitter diffusion layer and the external base diffusion layer are formed in a self-aligned manner by the spacer; Semiconductor device. 2. The semiconductor device according to claim 1, wherein said emitter diffusion layer is formed by diffusing impurities from said first polysilicon. 3. The method according to claim 1, further comprising:
An eave portion in which a concave portion protruding toward the center from both sides of the first polysilicon is formed, and a thermal oxide film formed in the same step as the gate oxide film of the MOS transistor is embedded in the concave portion. Claim 1 or 2 wherein
Semiconductor device described in 4. A step of forming a collector diffusion layer on a semiconductor substrate, a step of forming a base diffusion layer on the collector diffusion layer, and a diffusion source for forming an emitter diffusion layer on the base diffusion layer. Forming a first polysilicon in a required pattern, and forming M on the surface of the semiconductor substrate.
Forming a gate oxide film of the OS transistor by thermal oxidation and simultaneously forming the same thermal oxide film on the side wall of the first polysilicon; and forming a second polysilicon for a gate of the MOS transistor by a required process. Forming a pattern and simultaneously forming second polysilicon on both sides of the thermal oxide film on the side wall of the first polysilicon;
Forming side walls on both sides of the MOS transistor gate;
At the same time, the second polysilicon on both sides of the first polysilicon
Forming a sidewall on the side surface of the polysilicon, forming an external base diffusion layer using a spacer made of the first polysilicon, the thermal oxide film, and the second polysilicon as a mask; A method of forming an emitter diffusion layer by diffusing an impurity from said polysilicon into said base diffusion layer. 5. After forming the base diffusion layer, an oxide film is formed on a surface of the semiconductor substrate, and a narrower opening is formed in a region where the emitter diffusion layer is formed to expose the semiconductor substrate. And forming the first polysilicon in a required pattern in a region including the opening, and thereafter, removing the oxide film by isotropic etching to form the first polysilicon with the semiconductor substrate. 5. The method of manufacturing a semiconductor device according to claim 4, further comprising a step of forming a recess between the two and filling the recess with a thermal oxide film simultaneously with the gate oxide film.