JPH1153738A - Optical disk device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the disadvantage that the slice level value of an automatic slice circuit for generating a square wave from a reproduced signal is shifted caused by defects or data pattern. SOLUTION: When a synchronous code non-detection signal is supplied during the sector reproduction of a specified block, an improper slice level value caused by the synchronous code non-detection is determined, and a changeover switch 90 in an automatic slice circuit 93 is turned OFF. Thus, the charging voltage of the capacitor of an integrator 92 in the automatic slice circuit 93 is charged, and the slice level of a comparator 91 is reset (0: initial value).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical disk device for recording data on an optical disk and reproducing data recorded on the optical disk, and an optical disk device for reproducing data recorded on the optical disk.

[0002]

2. Description of the Related Art Recently, a digital video disk (DVD) has been developed as an optical disk of a large-capacity recording medium, and data is recorded on the optical disk or recorded / reproduced for reproducing data recorded on the optical disk. An optical disk device for performing the operation and a reproduction-only optical device for reproducing data recorded on the optical disk have been developed.
In such an optical disc device, pits are formed by a mark length recording (mark edge recording) method, and recording of channel data is performed.

In the above-described reproducing circuit in the optical disk device, a reproduced signal (after amplification) from a detector of the optical head is used.
Is binarized by a comparator, and a signal obtained by integrating the binarized signal is fed back as a reference value of the comparator so that the high-level time and the low-level time of the binarized signal are always constant. , And slice level control.

In this reproducing circuit, a DSV (Digital
l Sum Value: summed by let
ting bit 1 be +1 and bit
0be-1) is assumed to be 0, and DS
When the data pattern of V0 is continuous, reproduction can be performed with high accuracy.

However, depending on the data pattern, DS
DSV does not become V0 and DSV increases monotonically with data time.
Alternatively, the data may decrease monotonously, and the data may not be correctly reproduced.

Similarly, when an optical disc has a defect, a code pattern in which the DSV becomes 0 is not obtained, and the level control value is largely shifted at the defective portion, so that a signal after the defective portion cannot be correctly reproduced. Occurs.

For example, as shown in FIG. 14, the correct slice level is 0, but when a data pattern in which the DSV monotonically increases continues, the slice level deviates from an appropriate value. FIG. 14 shows the FE5C
8H modulated data (H) (7T, 3T, 4T,
4T, 10T, and 4T) are continuous waveform diagrams showing a reproduction signal waveform and a DSV auto slice level fluctuation when continuous.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to provide an optical disk apparatus capable of performing stable reproduction signal processing irrespective of a data pattern or a defect.

[0009]

An optical disk apparatus according to the present invention, which reproduces data recorded on an optical disk, comprises an optical head for reproducing data from the optical disk, and a reproduction reproduced by the optical head. A converting means for converting a signal into a rectangular wave based on a slice level, generating a slice level from the rectangular wave, an edge detecting means for outputting an edge detection signal of the rectangular wave from the converting means, and an edge from the edge detecting means Generating means for generating a reproduction clock based on the detection signal; demodulating means for demodulating an edge detection signal from the edge detection means into reproduction data based on the reproduction clock generated by the generation means; Judgment means for judging an abnormality in the slice level of the conversion means, and the slide means of the conversion means by this judgment means. When abnormal levels is determined, and a setting means for setting a slice level of the conversion means to a predetermined value.

An optical disk device according to the present invention reproduces data based on a synchronization code from an optical disk on which data is recorded and a synchronization code is recorded at predetermined intervals of the data. An optical head for reproducing data, a converting means for converting a reproduction signal reproduced by the optical head into a rectangular wave with reference to a slice level, and generating a slice level from the rectangular wave, and an edge of the rectangular wave from the converting means Edge detection means for outputting a detection signal, generation means for generating a reproduction clock based on the edge detection signal from the edge detection means, and edge detection based on the reproduction clock generated by the generation means. Demodulation means for demodulating the edge detection signal from the means into reproduction data, and demodulated by the demodulation means. Determining means for judging an abnormality in the slice level of the conversion means when the synchronization code recorded at each of the predetermined intervals is not detected by the demodulated data; and judging an abnormality in the slice level of the conversion means by the judgment means. When this is done, it is constituted by setting means for setting the slice level of the conversion means to an initial value.

An optical disk apparatus according to the present invention reproduces data based on a synchronization code from an optical disk in which data is recorded and a synchronization code is recorded at predetermined intervals of the data. An optical head for reproducing data, a converting means for converting a reproduction signal reproduced by the optical head into a rectangular wave with reference to a slice level, and generating a slice level from the rectangular wave, and an edge of the rectangular wave from the converting means Edge detection means for outputting a detection signal, generation means for generating a reproduction clock based on the edge detection signal from the edge detection means, and edge detection based on the reproduction clock generated by the generation means. Demodulation means for demodulating the edge detection signal from the means into reproduction data, and demodulated by the demodulation means. When the synchronization code recorded at the predetermined interval by the demodulated data is not detected, a determination unit that determines an abnormality of the slice level of the conversion unit, a storage unit that stores an initial value of the slice level of the conversion unit, And setting means for setting the slice level of the conversion means to an initial value read from the storage means when the determination means determines that the slice level of the conversion means is abnormal.

An optical disk apparatus according to the present invention is a synchronous optical disk apparatus comprising: a synchronous code area in which a synchronous code is recorded; and a data area in which data is recorded and a synchronous code is recorded at predetermined intervals of data. An optical head for reproducing data from the optical disc, a conversion means for converting a reproduction signal reproduced by the optical head into a rectangular wave based on a slice level, First generating means for generating a slice level used by the converting means from the rectangular wave according to the above, an edge detecting means for outputting an edge detecting signal of the rectangular wave from the converting means, and an edge detecting signal from the edge detecting means. , A second generating means for generating a clock for reproduction, generated by the second generating means Demodulation means for demodulating the edge detection signal from the edge detection means into reproduction data based on the raw clock, and the synchronization code recorded at the predetermined intervals is not detected by the demodulation data demodulated by the demodulation means. Determining means for judging an abnormality of the slice level used by the conversion means; and a slice level generated by the first generation means when the demodulation means demodulates the synchronization code in the synchronization code area. Storage means for storing the average value of the conversion means as a reference value, and setting for setting the slice level of the conversion means to the reference value read from the storage means when the determination means determines that the slice level is abnormal. Means.

An optical disk device according to the present invention reproduces data based on a synchronization code from an optical disk on which data is recorded and a synchronization code is recorded at predetermined intervals of the data. An optical head for reproducing data, a converting means for converting a reproduction signal reproduced by the optical head into a rectangular wave with reference to a slice level, and generating a slice level from the rectangular wave, and an edge of the rectangular wave from the converting means Edge detection means for outputting a detection signal, generation means for generating a reproduction clock based on the edge detection signal from the edge detection means, and edge detection based on the reproduction clock generated by the generation means. Demodulation means for demodulating the edge detection signal from the means into reproduction data, and demodulated by the demodulation means. First determining means for determining whether or not the synchronization code recorded at each of the predetermined intervals is detected based on the demodulated data; each time a synchronization code is detected by the first determining means, a slice of the conversion means is detected; Storage means for storing a level as a reference value; second determination means for determining an abnormality in the slice level of the conversion means when the synchronization code is not detected by the first determination means; and second determination means The setting means sets the slice level of the conversion means to the reference value read from the storage means when it is determined that the slice level of the conversion means is abnormal.

An optical disk apparatus according to the present invention, which reproduces data recorded on an optical disk, comprises an optical head for reproducing data from the optical disk, and a reproduction signal reproduced by the optical head is referenced to a slice level. Converting means for converting a rectangular wave by the converting means, first generating means for generating a slice level used in the converting means from the rectangular wave by the converting means, edge detecting means for outputting an edge detection signal of the rectangular wave from the converting means, Second generating means for generating a clock for reproduction based on the edge detection signal from the edge detecting means, and generating the clock for reproduction based on the clock for reproduction generated by the second generating means. Demodulation means for demodulating the edge detection signal into reproduced data, a rectangular wave from the conversion means and an error from the edge detection means. Third generating means for generating a rising edge signal and a falling edge signal based on the edge detection signal, wherein a phase difference between the rising edge signal and the falling edge signal from the third generating means is smaller than a predetermined value. When the value is larger, the determining means for determining the abnormality of the slice level of the converting means, and the setting for setting the slice level of the converting means to an initial value when the determining means determines that the slice level is abnormal. Means.

An optical disk device according to the present invention, which reproduces data recorded on an optical disk, comprises: an optical head for reproducing data from the optical disk; and a reproduction signal reproduced by the optical head is referenced to a slice level. Converting means for converting a rectangular wave by the converting means, first generating means for generating a slice level used in the converting means from the rectangular wave by the converting means, edge detecting means for outputting an edge detection signal of the rectangular wave from the converting means, Second generating means for generating a clock for reproduction based on the edge detection signal from the edge detecting means, and generating the clock for reproduction based on the clock for reproduction generated by the second generating means. Demodulation means for demodulating the edge detection signal into reproduced data, a rectangular wave from the conversion means and an error from the edge detection means. Third generating means for generating a rising edge signal and a falling edge signal based on the edge detection signal, wherein a phase difference between the rising edge signal and the falling edge signal from the third generating means is smaller than a predetermined value. When the value is larger, the judging means for judging the abnormality of the slice level of the converting means, the storing means for storing the initial value of the slice level of the converting means, and the judging means judge the abnormality of the slice level of the converting means. At this time, it is constituted by setting means for setting the slice level of the conversion means to an initial value read from the storage means.

An optical disk apparatus according to the present invention comprises a synchronous code area in which a synchronous code is recorded, and a data area in which data is recorded and a synchronous code is recorded at predetermined intervals of data. An optical head for reproducing data from the optical disc, a conversion means for converting a reproduction signal reproduced by the optical head into a rectangular wave based on a slice level, First generating means for generating a slice level used by the converting means from the rectangular wave according to the above, an edge detecting means for outputting an edge detecting signal of the rectangular wave from the converting means, and an edge detecting signal from the edge detecting means. , A second generating means for generating a clock for reproduction, generated by the second generating means Demodulation means for demodulating an edge detection signal from the edge detection means into reproduction data based on a raw clock; a rising edge signal based on a rectangular wave from the conversion means and an edge detection signal from the edge detection means; And a falling edge signal. When the phase difference between the rising edge signal and the falling edge signal from the third generating means is larger than a predetermined value, the slice level of the converting means Storage means for storing, as a reference value, an average value of slice levels generated by the first generation means when the demodulation means demodulates the synchronization code in the synchronization code area. Reading the slice level of the conversion means from the storage means when the determination means determines that the slice level of the conversion means is abnormal. And a setting means for setting the reference value. An optical disc apparatus according to the present invention reproduces data based on a synchronization code from an optical disc in which data is recorded and a synchronization code is recorded at predetermined intervals of the data. Head, which performs conversion, a conversion unit that converts a reproduction signal reproduced by the optical head into a rectangular wave based on a slice level, and a first generation unit that generates a slice level used by the conversion unit from the rectangular wave generated by the conversion unit. Edge detecting means for outputting a rectangular wave edge detecting signal from the converting means; second generating means for generating a reproduction clock based on the edge detecting signal from the edge detecting means; The edge detection signal from the edge detecting means is reproduced on the basis of a reproduction clock generated by the means. Demodulation means for demodulating the data, demodulation data demodulated by the demodulation means, detection means for detecting the synchronization code recorded at the predetermined intervals by the demodulation data demodulated by the demodulation means, Storage means for storing a slice level by the generation means as a reference value, and a third means for generating a rising edge signal and a falling edge signal based on the rectangular wave from the conversion means and the edge detection signal from the edge detection means. Generating means, determining means for determining an abnormality in the slice level of the converting means when the phase difference between the rising edge signal and the falling edge signal from the third generating means is larger than a predetermined value, and this determining means When the means determines that the slice level of the conversion means is abnormal, the slice level of the conversion means is read from the storage means. And a setting means for setting the.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an optical disk system showing an embodiment of the present invention will be described with reference to the drawings.

An optical disk system 60 shown in FIG. 1 records data (information) on an optical disk (DVD-RAM) 1 as a recording medium by using focused light, or writes data recorded on the optical disk 1. It comprises an optical disk device 61 for reproduction, and an optical disk control device 62 as an external device for instructing the optical disk device 61 to perform recording and reproduction.

The optical disk 1 is formed by coating a metal film layer such as tellurium or bismuth in a donut shape on a surface of a substrate formed in a circle of, for example, glass or plastics. This is a phase change type rewritable optical disk in which data is recorded or recorded data is reproduced using both lands, and address data is recorded at predetermined intervals by recording marks in a mastering step.

As shown in FIGS. 2 and 3, the optical disc 1 has a lead-in area 2, a data test zone,
It comprises a drive test zone, a disc identification data zone, and a replacement management zone as a replacement management area.

The data area 3 is composed of a plurality of, for example, 24 zones 3a,.

The lead-out area 4 is composed of a plurality of tracks and, like the rewritable data zone 6,
It is a rewritable data zone, and the same data zone 6 can be recorded.

As shown in FIG. 3, the optical disc 1
Data zone 6 and data area 3 which are rewritable with emboss data zone 5 of lead-in area 2 in order from the inside
, 3x, and the data zone of the lead-out area 4, and the clock signal for each zone is the same.
And the number of sectors for each track is different.

In the zones 3a,..., 3x of the data area 3, the number of rotations (speed) becomes slower as going from the inner circumference to the outer circumference of the optical disc 1, and the number of sectors per track increases. I have.

The relationship between the speed data as the number of revolutions and the number of sectors per track for each of the zones 3a,... 3x, 4, 5, 6 is recorded in the table 10a of the memory 10 as shown in FIG. ing.

.. 3x of the data area 3
As shown in FIGS. 2 and 3, data is recorded in each track in units of ECC (error correction code) block data (for example, 38688 bytes).

The ECC block is composed of 16 sectors in which 2K bytes of data are recorded. As shown in FIG. 5, each sector has a 4-byte (32-bit) sector ID (identification data) as address data. ) 1-I
D16 is a 2-byte error detection code (IED: I
D error detection code) along with a horizontal ECC (error correction code) 1 and a vertical ECC 2 as an error correction code for reproducing data recorded in an ECC block. It is to be recorded. This ECC
Numerals 1 and 2 are error correction codes added to data as redundant words in order to prevent data from being unable to be reproduced due to a defect of the optical disk 1.

Each sector is composed of 172 bytes of 12 rows of data, and each row (line) is provided with a 10-byte horizontal ECC1 and 18 rows.
A vertical ECC2 for one row of a 2-byte configuration is provided. Thus, the error correction circuit 52 described later performs error correction processing for each line using the horizontal ECC 1 and performs error correction processing for each column using the vertical ECC 2. .

When the ECC block is recorded on the optical disk 1, as shown in FIG. 6, the data is written for each predetermined data amount of each sector (each predetermined data length interval, for example, 91 bytes: 1456 channel bits). Synchronization code (2 bytes: 3
2 channel bits).

As shown in FIG. 7, each sector is composed of 26 frames from the 0th frame to the 25th frame, and the synchronization code (frame synchronization signal) assigned to each frame indicates the frame number. Specific code for specifying (1 byte: 16 channel bits) and common code common to each frame (1 byte: 16 channel bits)
It is composed of

That is, as shown in FIG. 7, the zeroth frame is SY0, the second, tenth, and eighteenth frames are SY1,
The fourth, twelfth and twentieth frames are SY2, sixth and first frames.
The 4th and 22nd frames are SY3, the 8th, 16th and 24th frames are SY4, the 1st, 3rd, 5th, 7th and 9th frames are SY5, the 11th, 13th, 15th and 17th frames Is SY6, and the 19th, 21st, 23rd, and 25th frames are SY7.

.. 3x of the data area 3
As shown in FIG. 2, each track has
A header section 11 in which addresses and the like are recorded, respectively.
Are pre-formatted in advance.

The header section 11 is formed when the groove is formed. This header part 11
8 is composed of a plurality of pits 12, as shown in FIG. 8, and is preformatted for the groove 13 as shown in the figure. The center of the pit 12 is on the same line as the boundary line between the groove 13 and the land 14. Exists in the position.

As shown in FIG. 8, the pit string ID1 is the header part of the groove 1, the pit string ID2 is the header part of the land 1, the pit string ID3 is the header part of the groove 2, the pit string ID4 is the header part of the land 2, The pit string ID5 is a header part of the groove 3, and the pit string ID6 is a header part of the land 3.

Therefore, the header portions for grooves and the header portions for lands are formed alternately (in a staggered manner).

The format for each sector is shown in FIG.
Is shown in

In FIG. 9, one sector is composed of 2697 bytes (bytes), a 128-byte header area (corresponding to the header section 11), a 2-byte mirror area 17,
It is composed of a recording area 18 of 2567 bytes.

The channel bits recorded in the sector have a format in which 8-bit data is modulated into 16-bit channel bits by 8-16 code.

The header area 11 is an area where predetermined data is recorded when the optical disc 1 is manufactured. The header area 11 includes four header 1 areas, two header areas, three header areas, and four header areas.

The header 1 area to the header 4 area are composed of 46 bytes or 18 bytes, and a 36-byte or 8-byte synchronization code part VFO (Variable Frequency O).
scillator), 3-byte address mark AM (Addres
s Mark), 4-byte address part PID (Position Ide)
ntifier), 2-byte error detection code IED (ID Err
or Detection Code) 1 byte postamble PA
(Postambles).

The header 1 area and the header 3 area have a 36-byte synchronization code section VFO1, and the header area 2 and the header 4 area have an 8-byte synchronization code section VFO2.

The synchronous code portions VFO1 and VFO2 are regions for pulling in a PLL. The synchronous code portion VFO1 records a sequence of "010 ..." in channel bits for "36" bytes (576 bits in channel bits) ( (Recording a pattern at a fixed interval), and the synchronization code portion VFO
Reference numeral 2 denotes a sequence of “010...” Of channel bits recorded for “8” bytes (128 bits of channel bits).

The address mark AM is a "3" byte synchronization code indicating where the sector address starts. As a pattern of each byte of the address mark AM, a special pattern which does not appear in the data portion of "0100100000000100" is used.

Address portions PID1 to PID4 are sector addresses (including ID numbers) as 4-byte address information.
Is an area where is recorded. The sector address is a physical sector number as a physical address indicating a physical position on the track. Since this physical sector number is recorded in the mastering step, it cannot be rewritten.

The ID number is, for example, “1” in the case of PID1, and is a number indicating the number of the overwriting four times in one header section 11.

The error detection code IED is an error (error) detection code for a sector address (including an ID number).
It is possible to detect the presence or absence of an error in the read PID.

The postamble PA includes state information necessary for demodulation, and also has a role of adjusting the polarity so that the header section 11 ends with a space.

The mirror area 17 is used for offset correction of a tracking error signal, timing generation of a land / groove switching signal, and the like.

The recording area 18 has a gap area of 10 to 26 bytes, a guard 1 area of 20 to 26 bytes, and a V area of 35 bytes.
FO3 area, 3-byte pre-synchronous code (P
S) area, data area of 2418 bytes, postamble 3 (PA3) area of 1 byte, guard 2 area of 48 to 55 bytes, and buffer area of 9 to 25 bytes.

The gap area is an area where nothing is written.

The guard 1 area is an area provided to prevent the terminal deterioration at the time of repetitive recording peculiar to the phase change recording medium from reaching the VFO3 area.

Although the VFO3 area is also an area for PLL lock, it is also an area for synchronizing byte boundaries by inserting a synchronization code in the same pattern.

The PS (pre-synchronous code) area is a tuning area for connecting to a data area.

The data area includes a data ID and a data ID error correction code IED (Data ID Error Detection Code).
e), synchronization code, ECC (Error Correction Code)
), An EDC (Error Detection Code), user data, and the like. The data ID is a sector ID 1 of 4 bytes (32 channel bits) of each sector.
~ ID16. Data ID error correction code IED
Is a 2-byte (16-bit) error correction code for data ID.

The sector IDs (1 to 16) are composed of 1-byte (8-bit) sector information and a 3-byte sector number (logical sector number as a logical address indicating a logical position on a track). ing. The sector information includes a 1-bit sector format type area,
It is composed of a bit tracking method area, a 1-bit reflectivity area, a 1-bit reserved area, a 2-bit area type area, a 1-bit data type area, and a 1-bit layer number area.

The logical sector number is different from the physical sector number due to the slip replacement process due to the initial defect.

The PA (postamble) 3 area contains state information necessary for demodulation, and indicates the end of the last byte of the previous data area.

The guard 2 area is an area provided for preventing the end deterioration at the time of repetitive recording peculiar to the phase change recording medium from reaching the data area.

The buffer area is an area provided for absorbing fluctuations in the rotation of the motor for rotating the optical disk 1 so that the data area does not cover the next header section 11.

The reason why the gap area is expressed as 10 to 26 bytes is that a random shift is performed. The random shift is to shift the data write start position in order to reduce the repetitive recording deterioration of the phase change recording medium. The length of the random shift is adjusted by the length of the buffer area located at the end of the data area, and the entire length of one sector is fixed at 2697 bytes.

Further, in FIG.
Is rotated at a different rotation speed for each zone by the motor 23, for example. The motor 23 is controlled by a motor control circuit 24.

Recording of data on the optical disc 1
Alternatively, reproduction of data recorded on the optical disk 1 is performed by the optical head 25. The optical head 25 is fixed to a drive coil 27 constituting a movable part of a linear motor 26, and the drive coil 27 is connected to a linear motor control circuit 28.

A speed detector 29 is connected to the linear motor control circuit 28 so that a speed signal of the optical head 25 is sent to the linear motor control circuit 28.

The fixed portion of the linear motor 26 is provided with a permanent magnet (not shown).
The optical head 25 is moved in the radial direction of the optical disk 1 by exciting the magnetic head 7 by the linear motor control circuit 28.

The optical head 25 has an objective lens 30
Are supported by a wire or a leaf spring (not shown), and the objective lens 30 is moved in a focusing direction (an optical axis direction of the lens) by a driving coil 31.
The drive coil 32 can move in a tracking direction (a direction orthogonal to the optical axis of the lens).

The semiconductor laser oscillator 39 is driven by the laser control circuit 33 to generate laser light. The laser control circuit 33 corrects the amount of laser light from the semiconductor laser oscillator 39 in accordance with the monitor current from the photodiode PD for monitoring the semiconductor laser oscillator 39.

The laser control circuit 33 includes a PLL (not shown)
It operates in synchronization with a recording clock signal from a circuit. This PLL circuit divides the frequency of a basic clock signal from an oscillator (not shown) to generate a clock signal for recording.

Then, the laser light generated by the semiconductor laser oscillator 39 driven by the laser control circuit 33 is irradiated onto the optical disk 1 via the collimator lens 40, the half prism 41, and the objective lens 30. Is guided to the photodetector 44 via the objective lens 30, the half prism 41, the condenser lens 42, and the cylindrical lens 43.

The photodetector 44 comprises four divided photodetection cells 44a, 44b, 44c and 44d.

The output signal of the photodetector cell 44a of the photodetector 44 is supplied to one end of an adder 46a via an amplifier 45a, and the output signal of the photodetector cell 44b is supplied to an amplifier 45a.
b to one end of the adder 46b, and the output signal of the light sensing cell 44c is supplied to the adder 46b via the amplifier 45c.
a, and the output signal of the light detection cell 44d is
The signal is supplied to the other end of the adder 46b via the amplifier 45d.

The output signal of the photodetector cell 44a of the photodetector 44 is supplied to one end of an adder 46c via an amplifier 45a, and the output signal of the photodetector cell 44b is supplied to the amplifier 45a.
b is supplied to one end of an adder 46d, and the output signal of the light sensing cell 44c is supplied to the adder 46d via an amplifier 45c.
d, the output signal of the photodetector cell 44d is
The signal is supplied to the other end of the adder 46c via the amplifier 45d.

The output signal of the adder 46a is supplied to the inverting input terminal of the differential amplifier OP2.
Is supplied with the output signal of the adder 46b. As a result, the differential amplifier OP2 outputs a signal (focus error signal) relating to the focus point according to the difference between the adders 46a and 46b.
To be supplied. The output signal of the focusing control circuit 47 is
And the laser light is controlled so that it is always just focused on the optical disc 1.

The output signal of the adder 46c is supplied to the inverting input terminal of the differential amplifier OP1.
Is supplied with the output signal of the adder 46d. Thus, the differential amplifier OP1 supplies a tracking error signal to the tracking control circuit 48 according to the difference between the adders 46c and 46d.
The tracking control circuit 48 creates a track drive signal according to the tracking error signal supplied from the differential amplifier OP1.

The track drive signal output from the tracking control circuit 48 is supplied to the drive coil 32 in the tracking direction. The tracking error signal used in the tracking control circuit 48 is supplied to the linear motor control circuit 28.

Each of the light detecting cells 44 of the light detector 44 in the state where the focusing and tracking are performed as described above.
a, the sum signal of the outputs of .about.
The signal obtained by adding the output signal from 6d by the adder 46e is
The change in reflectivity from pits (recording data) formed on the track is reflected. This signal is supplied to a data reproducing circuit 38, where the recorded data is reproduced.

The reproduced data reproduced by the data reproducing circuit 38 is subjected to error correction by the error correction circuit 52 using the provided error correction code ECC, and thereafter, the optical disk as an external device is transmitted through the interface circuit 55. Output to the control device 62.

When the tracking control circuit 48 moves the objective lens 30, the linear motor control circuit 28 operates the linear motor 26, that is, the optical motor 26 so that the objective lens 30 is positioned near the center of the optical head 25. The head 25 is moved.

A data generation circuit 34 is provided at a stage preceding the laser control circuit 33. The data generation circuit 34 is provided with the ECC block format data as the recording data as shown in FIG. 5 supplied from the error correction circuit 52 and the ECC block synchronization code as shown in FIG. An ECC block data generation circuit 34a for converting into ECC block format data for recording; and an ECC block data generation circuit 34
and a modulation circuit 34b for modulating the recording data from a by the 8-16 code conversion system.

The data generation circuit 34 is supplied with recording data to which an error correction code has been added by the error correction circuit 52 and dummy data for error checking read from the memory 10. Error correction circuit 52
Is supplied with recording data from an optical disk control device 56 as an external device via an interface circuit 55 and a bus 49.

The error correction circuit 52 converts the 32 Kbytes of recording data supplied from the optical disc control unit 62 to 2K bytes.
Each of the horizontal and vertical error correction codes (ECC1, ECC1) for the recording data in the sector unit for each byte.
2), a sector ID (logical address number) is added, and format data of an ECC block as shown in FIG. 5 is generated.

The optical disk device 61 has a focusing control circuit 47, a tracking control circuit 48, a linear motor control circuit 28, and a D which is used for exchanging information between the CPU 50 for controlling the entire optical disk device. A / A converter 51 is provided.

The motor control circuit 24, linear motor control circuit 28, laser control circuit 33, data reproduction circuit 3
8, a focusing control circuit 47, a tracking control circuit 48, an error correction circuit 53, etc.
This is controlled by the PU 50, and this C
The PU 50 performs a predetermined operation according to a control program recorded in the memory 10.

The memory 10 stores a control program and is used for data recording. The memory 10 has a table 10a in which speed data as the number of revolutions and the number of sectors for each track are recorded for each of the zones 3a,... 3x, 4, 5, and 6.

The data reproducing circuit 38 shown in FIGS.
1. As shown in FIG. 12, a binarization circuit 71, a PLL circuit 72, a shift register 74, a demodulation circuit 75, an address mark detection circuit 76, a word boundary counter 77, an IED check circuit 78, an address comparison circuit 79, a header detection It comprises a signal generation circuit 80 and a synchronization code detection circuit 81.

As shown in FIGS. 11 and 12, the binarizing circuit 71 delays the output from the comparator 91, the integrator 92 and the changeover switch 90, and the output from the comparator 91. And a logic circuit 95 for outputting an edge detection signal by taking an exclusive OR of the delayed output from the delay circuit 94 and the output from the comparator 91. ing. The comparator 91 is a circuit that compares an output signal from the adder 46e with a signal obtained by integrating the output signal of the comparator 91 by the integrator 92. The integrator 92
It comprises a charge pump and a capacitor (not shown). The voltage charged in the capacitor of the integrator 92 is discharged when the changeover switch 90 is turned on. The changeover switch 90 is connected to the CPU 50
It is turned on by a switching signal (reset signal) from the CPU. This on-time is good for a moment.

The auto slicing circuit 93 changes the waveform of the output signal (reproduced signal) from the adder 46e as shown in FIG. 13A to a waveform close to a square wave. This is as shown in FIG. The edge detection circuit 96 is a circuit for detecting the edge of the signal waveform from the auto slice circuit 93, and the edge detection signal is as shown in FIG. The edge detection signal output from the edge detection circuit 96 becomes a binarized signal output from the binarization circuit 71 and is output to the PLL circuit 72.

The PLL circuit 72 includes an edge detection circuit 9
A channel clock and channel data are generated by the binarized signal from FIG. 6, and as shown in FIGS. 11 and 12, a phase comparator 97, a charge pump 98, an integrator 99, and a voltage controlled oscillator (VOC) ) 100. That is, the PLL is applied to both the falling edge and the rising edge from the edge detection circuit 96.

The phase comparator 97 is a lock-in type phase comparator, and compares the phase of the binary signal (reproduction signal) from the edge detection circuit 96 with the phase of the clock signal from the voltage controlled oscillator 100. And outputs a signal having a pulse width proportional to the compared phase difference. This phase comparator 97
Data (channel data) synchronized with the clock signal from is output to the shift register 74.

The phase comparator 97 comprises three flip-flop circuits 97a, 97b, 97c and two AND circuits 97
d and 97e and two inverter circuits 97f and 97g, and an output signal from the AND circuit 97d is shown in FIG.
3 (d), the output signal from the AND circuit 97e is a discharge signal, and these signals are output to the charge pump 98.

The charge pump 98 is connected to the phase comparator 9
A subtractor for subtracting the charge signal from the discharge signal from 7 is integrated, and the result of this subtraction is integrated by the integrator 99 and output to the voltage controlled oscillator (VOC) 100.

A voltage controlled oscillator (VCO; voltage)
control oscillator) 100 is
Voltage value (analog value) of signal supplied from integrator 99
And outputs a binary clock signal (channel clock) having a frequency proportional to the channel clock. The channel clock is a signal as shown in FIG.

The channel clock of the voltage controlled oscillator 100 is output to the phase comparator 97 and also to the shift register 74, the demodulation circuit 75, the address mark detection circuit 76, and the word boundary counter 77.

The shift register 74 converts the supplied channel data into 16-bit parallel data and outputs it. The 16-bit channel data from the shift register 74 is supplied to a demodulation circuit 75 and an address mark detection circuit 76.

The demodulation circuit 75 outputs the data stored at the address corresponding to the 16-bit address data from the shift register 74 when the word boundary signal is supplied from the word boundary counter 77 as ROM output data. A demodulation ROM (not shown) and R from the demodulation ROM
It is composed of a parallel-serial converter (not shown) for converting demodulated data as OM output data into serial data in accordance with a data clock generated by dividing the channel clock from the PLL circuit 72 and outputting the data. .

The ROM output data is data obtained by demodulating 16-bit channel bits into 8-bit data based on a predetermined (8, 16) code conversion rule corresponding to the address data. is there.

The demodulated data signal from the demodulation circuit 75 is
It is output to the ED check circuit 78 and the address comparison circuit 79. The data clock created by the demodulation circuit 75 is output to the IED check circuit 78, the address comparison circuit 79, and the header detection signal generation circuit 80.

The address mark detection circuit 76 is composed of a comparator. Each time the channel clock is supplied from the PLL circuit 72, the 16-bit channel data from the shift register 74 matches the 16-bit address mark. The address mark detection signal is output when they match with each other. The address mark detection signal from the address mark detection circuit 76 is output to a word boundary counter 77, an IED check circuit 78, an address comparison circuit 79, and a header detection signal generation circuit 80.

The word boundary counter 77 counts using the address mark detection signal from the address mark detection circuit 76 as a trigger and outputs a word boundary signal for each fixed-length block code (16 channel bits). The word boundary signal from the word boundary counter 77 is output to the demodulation circuit 75.

After the address mark detection signal from the address mark detection circuit 76 is supplied to the IED check circuit 78, the sector address of the 6-byte address part PID supplied from the demodulation circuit 75 and the error detection code IED
Are accepted based on the data clock, and whether or not the sector address is correct is determined based on whether or not the operation result of the accepted sector address with the error detection code IED is “0”.

The check result of the IED check circuit 78 is output to the header detection signal generation circuit 80.

After receiving the address mark detection signal from the address mark detection circuit 76, the address comparison circuit 79 receives the 4-byte sector address of the address part PID supplied from the demodulation circuit 75 based on the data clock. The ID number in the received sector address is compared with any one of "1" to "4", and a signal corresponding to the matching ID number is output.
The signal corresponding to the ID number from the address comparison circuit 79 is output to the header detection signal generation circuit 80. For example,
When the ID number is “1”, “00” is output, and when the ID number is “2”, “01” is output, and the ID number is “3”.
In this case, "10" is output, and when the ID number is "4", "11" is output.

The address comparing circuit 79 outputs the received sector address to the CPU 30 as address data.

The header detection signal generation circuit 80 generates a signal corresponding to the ID number supplied from the address comparison circuit 79 when the check result from the IED check circuit 78 is correct, and an address from the address mark detection circuit 76. A header detection signal is generated at the end of the mirror mark area in accordance with the mark detection signal and the number of bytes counted by the data clock from the demodulation circuit 75. For example, an address mark detection signal is supplied. It is constituted by a binary counter for counting the number of subsequent bytes by the data clock from the demodulation circuit 75. The header detection signal from the header detection signal generation circuit 80 is output to the CPU 50. For example, if a signal indicating that the check result correctly indicates "1" as an ID number is supplied, a header detection signal is generated 94 bytes after the address mark detection signal is supplied from the address mark detection circuit 76, and the check result is output. When a signal indicating "2" is correctly supplied as an ID number, a header detection signal is generated 76 bytes after the address mark detection signal is supplied from the address mark detection circuit 76, and the check result indicates that the ID number is correctly "ID". When a signal indicating "3" is supplied, a header detection signal is generated 30 bytes after the address mark detection signal is supplied from the address mark detection circuit 76, and the check result is a signal indicating "4" as the ID number correctly. Is supplied, the address mark detection signal from the address mark detection circuit 76 is supplied. And it generates a header detection signal after 12 bytes from being.

The synchronization code detection circuit 81 is composed of a byte counter and a comparator, counts the number of bytes based on the header detection signal from the header detection signal generation circuit 80, and corresponds to the data area according to the count value. Each time the channel clock is supplied from the PLL circuit 72, whether or not the 16-bit channel data from the shift register 74 matches the 16-bit synchronization code pattern (common code pattern) is determined. If a comparison is made and a match is found, a synchronization code detection signal is output to the synchronization code non-detection circuit 82.

The synchronization code non-detection circuit 82 is composed of a frame counter, a synchronization code detection window signal generation circuit, and a synchronization code non-detection determination circuit, and the number of bytes based on the synchronization code detection signal from the synchronization code detection circuit 81 When the synchronization code detection signal is not supplied from the synchronization code detection circuit 81 while the signal is being generated, a synchronization code detection window signal is generated while the count value is a predetermined value. , The synchronization code non-detection signal
0 is output.

Next, a description will be given of a reproduction operation of a sector of a predetermined block in the above configuration.

That is, the reproduced signal as the output signal from the adder 26e is binarized by the binarization circuit 71,
Channel data and a channel clock are generated by the circuit 72 and supplied to the shift register 74.

The channel clock from the PLL circuit 72 is supplied to the demodulation circuit 75, the address mark detection circuit 76,
The word boundary counter 77 is supplied to the synchronization code detection circuit 81.

That is, the reproduced signal as the output signal of the adder 26e is supplied to the comparator 91 in the auto slice circuit 93.
Is supplied to the inverting input terminal of. The slice level set by the integrator 92 is supplied to a non-inverting input terminal of the comparator 91. Thus, the comparator 91 slices the reproduced signal from the adder 26e with the slice level from the integrator 92, changes the waveform to a waveform close to a square wave, and outputs the waveform to the edge detection circuit 96.
Output to the integrator 92. The slice level from the integrator 92 is changed by the output of the comparator 91.

The edge detection circuit 96 is provided with a comparator 91
And outputs the detected edge detection signal to the phase comparator 97 of the PLL circuit 72 as a binarized signal.

The phase of the binary signal (reproduction signal) from the edge detection circuit 96 is compared with the phase of the clock signal from the voltage controlled oscillator 100, and a signal having a pulse width proportional to the compared phase difference is output. .

Data (channel data) synchronized with the clock signal from the phase comparator 97 is stored in the shift register 7.
4 and the charge signal and the discharge signal are output to the charge pump 98.

The charge pump 98 is connected to the phase comparator 9
A subtractor for subtracting the charge signal from the discharge signal from 7 is integrated, and the result of this subtraction is integrated by the integrator 99 and output to the voltage controlled oscillator (VOC) 100.

The voltage controlled oscillator 100 converts the binary clock signal (channel clock) having a frequency proportional to the voltage value (analog value) of the signal supplied from the integrator 99 into the shift register 74, the demodulation circuit 75, and the address mark detection. Output to the circuit 76, word boundary counter 77, and synchronization code detection circuit 81.

In this state, shift register 74
Converts the supplied channel data into 16-bit parallel data, and supplies it to the demodulation circuit 75 and the address mark detection circuit 76. Address mark detection circuit 76
When the address mark is detected by the channel data from the shift register 74, the address mark detection signal is sent to the word boundary counter 77, the IED check circuit 78, the address comparison circuit 79, and the header detection signal generation circuit 80.
To supply. The word boundary counter 77 counts using the address mark detection signal from the address mark detection circuit 76 as a trigger, and outputs a word boundary signal to the demodulation circuit 75 for each fixed-length block code (16 channel bits).

The demodulation circuit 75 converts the 16-bit address data from the shift register 74 when the word boundary signal is supplied from the word boundary counter 77 into ROM output data, and divides the channel clock to create the data. In accordance with the data clock, the demodulated data signal converted to serial
Output to the ED check circuit 78 and the address comparison circuit 79. The data clock generated by the demodulation circuit 74 is supplied to the IED check circuit 78 and the address comparison circuit 7.
9, output to the header detection signal generation circuit 80 and the synchronization code non-detection circuit 82.

After the address mark detection signal from the address mark detection circuit 76 is supplied to the IED check circuit 78, the sector address of the 6-byte address part PID supplied from the demodulation circuit 74 and the error detection code IED
Is determined based on the data clock, and whether the sector address is correct is determined based on whether or not the calculation result of the received sector address with the error detection code IED is "0". Output to the generation circuit 80.

After the address mark detection signal from the address mark detection circuit 76 is supplied to the address comparison circuit 79, the address comparison circuit 79 determines the 4-byte sector address of the address part PID supplied from the demodulation circuit 75 based on the data clock. ID in the received sector address
The number corresponding to any one of “1” to “4” is compared, and a signal corresponding to the matching ID number is output to the header detection signal generation circuit 80.

Then, the CPU 50 determines whether or not the address data matches the address data for starting the reproduction processing. If not, the CPU 50 performs the above-described access processing again.

If they match, the CPU 50 outputs the data in the data area of the first sector demodulated by the demodulation circuit 75 in the data reproduction circuit 38 to the error correction circuit 52. Further, the data in the data area for each subsequent sector is output to the error correction circuit 52. Thereby, 1E
The data of the CC block is supplied to the error correction circuit 52. When the error correction processing by the error correction circuit 52 is performed, the CPU 50 outputs the data of the sector instructed to be reproduced in the reproduced ECC block to the optical disc control circuit 62 as a reproduction result in such a state. The header detection signal generation circuit 80 includes a signal corresponding to the ID number supplied from the address comparison circuit 79 when the check result from the IED check circuit 78 is correct, and an address mark detection signal from the address mark detection circuit 76. A header detection signal is generated corresponding to the end of the mirror mark area according to the number of bytes counted by the data clock from the demodulation circuit 75 and output to the synchronization code detection circuit 81.

Then, the synchronous code detecting circuit 81
The number of bytes is counted based on the header detection signal from the header detection signal generation circuit 80, and the shift is performed every time a channel clock is supplied from the PLL circuit 72 while corresponding to the data area according to the count value. Register 74
Is compared with the 16-bit synchronization code pattern (pattern of the common code), and when they match, a synchronization code detection signal is output to the synchronization code non-detection circuit 82. You.

Thus, the synchronization code non-detection circuit 82
Counts the number of bytes based on the synchronization code detection signal from the synchronization code detection circuit 81, and generates a synchronization code detection window signal while the count value is a predetermined value. When the synchronization code detection signal is not supplied from the synchronization code detection circuit 81, a synchronization code non-detection signal is output to the CPU 50.

Thus, during reproduction of a sector of a predetermined block, when a synchronization code non-detection signal is supplied, the CPU 50 determines that the slice level value has become inappropriate due to the non-detection of the synchronization code. A switching signal (reset signal) is output to a changeover switch 90 in the auto slice circuit 93.

Thereafter (after a predetermined time), the changeover switch 90 is turned off again, whereby the capacitor in the integrator 92 is charged by the output of the comparator 91.
The output of the integrator 92 is output to the non-inverting input terminal of the comparator 91 as a slice level. As a result, by switching the changeover switch 90 by the changeover signal from the CPU 50, the charge voltage of the capacitor of the integrator 92 in the auto slice circuit 93 is discharged, and the slice level of the comparator 91 is reset (0: initial value). )
In other words, once the capacitor is short-circuited to the reference voltage, it is possible to avoid the disadvantage that the slice level value of the auto-slice circuit that generates a square wave from the reproduced signal is shifted due to the defect or data pattern shown in FIG.

Next, a second embodiment will be described.

In the above-described first embodiment, when the synchronization code is not detected, the charge voltage of the integrator (capacitor) of the auto slice circuit is discharged, so that the slice of the auto slice circuit, which is the output of the integrator, is discharged. Although the case where the level is reset has been described, in the second embodiment, as shown in FIGS. 15, 16 and 17, the output of the integrator 92 in the auto slice circuit 93 is set to the A / D converter 1
01 and the non-inverting input terminal of the comparator 91 in the auto slice circuit 93.
Are connected via the D / A converter 102,
The output of the integrator 92 in the auto slice circuit 93 is A / D
The data is converted into a digital value by the converter 101 and
The slice level value as a digital value is again converted into an analog signal by the D / A converter 102 via the reference numeral 50 and supplied to the non-inverting input terminal of the comparator 91, and no synchronization code is detected. Hour, CPU 50
The slice level value output from the
This is changed to an appropriate value set to 0.

The description of the same parts as those in the first embodiment will be omitted.

That is, as shown in FIG. 15, the output of the integrator 92 of the auto slice circuit 93 is output from the A / D converter 10.
1 and converted into a digital value by the CPU 50.
The signal is converted into an analog signal by the / A converter 102 and supplied to the non-inverting input terminal of the comparator 91. Also, the slice level value as a preset suitability value is
It is stored in the memory 10.

In such a state, when the check result from the IED check circuit 78 is correct, the header detection signal generation circuit 80 outputs a signal corresponding to the ID number supplied from the address comparison circuit 79 and an address. According to the address mark detection signal from the mark detection circuit 76 and the number of bytes counted by the data clock from the demodulation circuit 75, a header detection signal is generated at the end of the mirror mark area, and the synchronization code detection is performed. Output to the circuit 81.

Then, the synchronous code detection circuit 81
The number of bytes is counted based on the header detection signal from the header detection signal generation circuit 80, and the shift is performed every time a channel clock is supplied from the PLL circuit 72 while corresponding to the data area according to the count value. Register 74
Is compared with the 16-bit synchronization code pattern (pattern of the common code), and when they match, a synchronization code detection signal is output to the synchronization code non-detection circuit 82. You.

Thus, the synchronization code non-detection circuit 82
Counts the number of bytes based on the synchronization code detection signal from the synchronization code detection circuit 81, and generates a synchronization code detection window signal while the count value is a predetermined value. When the synchronization code detection signal is not supplied from the synchronization code detection circuit 81, a synchronization code non-detection signal is output to the CPU 50.

Thus, during reproduction of a sector of a predetermined block, when a synchronization code non-detection signal is supplied, the CPU 50 determines that the slice level value has become inappropriate due to the non-detection of the synchronization code. A digital value as an appropriate value is read from the memory 10, converted into an analog value by the D / A converter 102, and output to the non-inverting input terminal of the comparator 91 as a slice level.

After that (after a predetermined time), the CPU 50
The D / A converter 102 converts the digital value supplied from the A / D converter 101 into an analog value as it is, and outputs the analog value to the non-inverting input terminal of the comparator 91 as a slice level.

As a result, when the synchronization code cannot be detected, the slice level supplied to the comparator 91 in the auto slice circuit 93 is changed to an appropriate value.
That is, by determining that the slice level value is deviated from the appropriate value and temporarily setting the slice level to the initial value, the slice level value of the auto slice circuit that generates a square wave from the reproduced signal is deviated due to a defect or a data pattern. The drawback of that can be avoided.

Next, a third embodiment will be described.

In the second embodiment described above, the case where the slice level value output from the CPU 50 is changed to the appropriate value set in the memory 10 in advance when the synchronization code is not detected has been described. In the third embodiment, the auto slice circuit 93 at the time of VFO pull-in is used.
The average value of the digital value from the A / D converter 101 as the output of the integrator 92 is stored in the memory 10,
When the synchronization code is not detected, the slice level value output from the CPU 50 is changed to the average value stored in the memory 10.

The description of the same parts as those in the second embodiment will be omitted.

That is, as shown in FIGS. 15, 16 and 17, the output of the integrator 92 of the auto slice circuit 93 is converted into a digital value by the A / D converter 101,
The slice level value as a digital value is again converted to an analog signal by the D / A converter 102 via the CPU 50 and supplied to the non-inverting input terminal of the comparator 91.

In such a state, when the check result from the IED check circuit 78 is correct, the header detection signal generation circuit 80 outputs a signal corresponding to the ID number supplied from the address comparison circuit 79 and an address. According to the address mark detection signal from the mark detection circuit 76 and the number of bytes counted by the data clock from the demodulation circuit 75, a header detection signal is generated at the end of the mirror mark area, and the synchronization code detection is performed. The circuit 81 outputs to the CPU 50.

Then, CPU 50 determines the VFO3 area according to the count value from a binary counter (not shown) that counts the number of bytes based on the header detection signal from header detection signal generation circuit 80, and determines this VFO3 area. The integrator 9 of the auto slice circuit 93
The average value of the digital values supplied from 2 through the A / D converter 101 is determined as an appropriate slice level and stored in the memory 10.

The synchronization code detection circuit 81 counts the number of bytes based on the header detection signal from the header detection signal generation circuit 80, and according to the count value, while corresponding to the data area, the PLL circuit Each time the channel clock from 72 is supplied, it is compared whether or not the 16-bit channel data from the shift register 74 matches the 16-bit synchronization code pattern (common code pattern). , A synchronization code detection signal is output to the synchronization code non-detection circuit 82.

As a result, the synchronization code non-detection circuit 82
Counts the number of bytes based on the synchronization code detection signal from the synchronization code detection circuit 81, and generates a synchronization code detection window signal while the count value is a predetermined value. When the synchronization code detection signal is not supplied from the synchronization code detection circuit 81, a synchronization code non-detection signal is output to the CPU 50.

Thus, during reproduction of a sector of a predetermined block, when a synchronization code non-detection signal is supplied, the CPU 50 determines that the slice level value has become inappropriate due to the non-detection of the synchronization code. A digital value (average value of a slice level at the time of VFO pull-in) as an appropriate value is read from the memory 10 and converted into an analog value by a D / A converter 102 and converted into a comparator 91 as a slice level.
Is output to the non-inverting input terminal.

Thereafter, the CPU 50 again converts the digital value supplied from the A / D converter 101 into a D / A
The converter 102 converts the analog value into an analog value and outputs the analog value to the non-inverting input terminal of the comparator 91 as a slice level.

As a result, when the synchronization code cannot be detected, the slice level supplied to the comparator 91 in the auto slice circuit 93 is changed to an appropriate value.
In other words, it is determined that the slice level value is deviated from the proper value, and the slice level of the auto slice circuit that generates a square wave from the reproduced signal is deviated due to a defect or a data pattern by temporarily setting the slice level to the average value. The disadvantage of doing so can be avoided.

Next, a fourth embodiment will be described.

In the above-described second embodiment, the case has been described where the slice level value output from the CPU 50 is changed to an appropriate value preset in the memory 10 when no synchronization code is detected. In the fourth embodiment, the A / D converter 101 as the output of the integrator 92 in the auto slice circuit 93 every time the synchronization code is detected.
Is stored in the memory 10 as an appropriate value, and when the synchronization code is not detected, the CPU 50
Is changed to an appropriate value stored in the memory 10.

The description of the same parts as those in the second embodiment will be omitted.

That is, as shown in FIGS. 18, 16 and 17, the output of the integrator 92 of the auto slice circuit 93 is converted into a digital value by the A / D converter 101.
The slice level value as a digital value is again converted to an analog signal by the D / A converter 102 via the CPU 50 and supplied to the non-inverting input terminal of the comparator 91. In addition, as shown in FIG.
1, a synchronous code detection signal is supplied to the CPU 50.

In such a state, when the check result from the IED check circuit 78 is correct, the header detection signal generation circuit 80 outputs a signal corresponding to the ID number supplied from the address comparison circuit 79 and an address. According to the address mark detection signal from the mark detection circuit 76 and the number of bytes counted by the data clock from the demodulation circuit 75, a header detection signal is generated at the end of the mirror mark area, and the synchronization code detection is performed. Output to the circuit 81.

Then, the synchronization code detection circuit 81
The number of bytes is counted based on the header detection signal from the header detection signal generation circuit 80, and the shift is performed every time a channel clock is supplied from the PLL circuit 72 while corresponding to the data area according to the count value. Register 74
And whether the 16-bit channel data and the 16-bit synchronization code pattern (common code pattern) match, and when they match, sends a synchronization code detection signal to the synchronization code non-detection circuit 82 and the CPU 50. Is output.

Then, when the synchronization code detection signal is supplied from the synchronization code detection circuit 81, the CPU 50
The digital value supplied from the integrator 92 of the auto slice circuit 93 via the A / D converter 101 is determined as an appropriate slice level, and stored in the memory 10.

The synchronization code non-detection circuit 82 counts the number of bytes based on the synchronization code detection signal from the synchronization code detection circuit 81, and generates a synchronization code detection window signal while the count value is a predetermined value. When the synchronization code detection signal is not supplied from the synchronization code detection circuit 81 while this signal is being generated, a synchronization code non-detection signal is output to the CPU 50.

Thus, during reproduction of a sector of a predetermined block, when a synchronization code non-detection signal is supplied, the CPU 50 determines that the slice level value has become inappropriate due to the non-detection of the synchronization code. A digital value as an appropriate value is read from the memory 10, converted into an analog value by the D / A converter 102, and output to the non-inverting input terminal of the comparator 91 as a slice level.

Thereafter, the CPU 50 again converts the digital value supplied from the A / D converter 101 into a D / A
The converter 102 converts the analog value into an analog value and outputs the analog value to the non-inverting input terminal of the comparator 91 as a slice level.

As a result, when the synchronization code cannot be detected, the slice level supplied to the comparator 91 in the auto slice circuit 93 is changed to an appropriate value.
In other words, by determining that the slice level value is deviated from the appropriate value and setting the slice level to the slice level value at the time of detecting the synchronization code, the slice level value of the auto slice circuit that generates a square wave from the reproduced signal is defective or defective. It is possible to avoid the disadvantage that the data pattern shifts.

Next, a fifth embodiment will be described.

In the above-described first embodiment, when the synchronization code is not detected, the charge voltage of the integrator (capacitor) of the auto slice circuit is discharged so that the slice of the auto slice circuit, which is the output of the integrator, is discharged. Although the case where the level is reset has been described, in the fifth embodiment, as shown in FIGS. 19, 20, and 21, the synchronization code detection circuit 81 and the synchronization code non-detection circuit 82 of the first embodiment are deleted. Instead, it is determined that the phase difference between the rising edge and the falling edge of the output signal from the auto slicing circuit 93 has increased (when it exceeds a certain value, it is determined that the slice level is not at an appropriate value). A level judging circuit 105 is provided, and the output signal from the slice level judging circuit 105 is used as a switching signal as a switch of the auto slice circuit 93. Isureberu may be reset.

In this case, the slice level judgment circuit 105
Is the output signal of the auto slice circuit 93 and the PLL circuit 7
2 determines that the phase difference between the rising edge and the falling edge of the output signal from the auto slice circuit 93 has increased based on the charge signal output from the phase comparator 97 in FIG. As described above, the inverter circuit 105a, the AND circuits 105b and 105c, the charge pump 105d, the low-pass filter 105e, the comparator 1
05f.

A signal obtained by inverting the output signal from auto slice circuit 93 by inverter circuit 105a and phase comparator 9
AND with the charge signal from the AND circuit 105b
2 from the AND circuit 105b.
2 (f) and a falling edge signal as shown in FIG. 23 (f) are output to the charge pump 105d.

Also, by taking the logical product of the output signal from the auto slice circuit 93 and the charge signal from the phase comparator 97 by the AND circuit 105c, the AND circuit 105c outputs the logical product of FIG. 22 (g) and FIG. A rising edge signal as shown in (g) is output to the charge pump 105d.

The charge pump 105d receives the falling edge signal from the AND circuit 105b and the AND circuit 105b.
A subtractor for subtracting the rising edge signal from c is output to the comparator 105f via the low-pass filter 105e. That is, as shown in FIG. 24B, a signal corresponding to the phase difference between the falling edge signal and the rising edge signal as shown in FIG. Is output.

The comparator 105f includes the low-pass filter 10
A signal value corresponding to the phase difference between the falling edge signal and the rising edge signal from 5e and a reference value (reference value) are compared, and when a phase difference larger than the reference value occurs, it is determined that the slice level is abnormal. Judgment is made and a changeover signal is output to the changeover switch 90.

The reproduced signal from the adder 46e is shown in FIG.
2 (a) and FIG. 23 (a), the output signal of the auto slice circuit 93 is shown in FIG. 22 (b) and FIG. 23 (b), and the edge detection signal of the edge detection circuit 96 is shown in FIG. 23 (c) and FIG. 23 (c), the charge signal of the phase comparator 97 is shown in FIG. 22 (d) and FIG. 23 (d), and the channel clock of the voltage controlled oscillator 100 is shown in FIG. e) and (e) of FIG.

The description of the same parts as those in the first embodiment will be omitted.

That is, as shown in (f) and (g) of FIG. 22, when the phase difference between the rising edge and the falling edge is small during the reproduction process, the slice level judgment circuit 105 It is determined that the slice level is appropriate, and no switching signal is output.

Also, when performing the reproduction process, FIG.
As shown in (f) and (g), when the phase difference between the rising edge and the falling edge is large, the slice level determination circuit 105 determines that the slice level is shifted, and switches the switching signal to the switch 90. Output to

Thereafter (after a predetermined time), the changeover switch 90 is turned off again, whereby the capacitor in the integrator 92 is charged by the output of the comparator 91.
The output of the integrator 92 is output to the non-inverting input terminal of the comparator 91 as a slice level. As a result, by switching the changeover switch 90 in response to the changeover signal from the slice level judgment circuit 105, the auto slice circuit 9 is switched.
The charging voltage of the capacitor of the integrator 92 in 3 is discharged,
By resetting the slice level of the comparator 91 once (0: initial value), it is possible to avoid the disadvantage that the slice level value of the auto slice circuit that generates a square wave from the reproduced signal is shifted due to a defect or a data pattern.

Next, a sixth embodiment will be described.

In the fifth embodiment, when the phase difference between the rising edge and the falling edge is large, the output voltage of the integrator (capacitor) of the auto slice circuit is discharged by discharging the charging voltage. Although the case where the slice level of the auto slice circuit is reset has been described, in the sixth embodiment, as shown in FIGS. 25, 26 and 27, the output of the integrator 92 in the auto slice circuit 93 is A / D. The CPU 50 is connected via a D / A converter 102 to a non-inverting input terminal of a comparator 91 in an auto slice circuit 93, and is connected to a CPU 50 via a converter 101. Is output to the CPU 50 as a slice level abnormality determination signal, and the integrator 92 in the auto slice circuit 93 is output.
Is converted to a digital value by the A / D converter 101, and the slice level value as the digital value is converted again to an analog signal by the D / A converter 102 via the CPU 50, The slice level output from the CPU 50 when the phase difference between the rising edge and the falling edge is large, that is, when the slice level abnormality determination signal of the slice level determination circuit 105 is output to the inverting input terminal. The value is changed to an appropriate value set in the memory 10 in advance.

The description of the same parts as in the fifth embodiment is omitted.

That is, as shown in FIGS. 26 and 27,
The output of the integrator 92 of the auto slice circuit 93 is converted into a digital value by the A / D converter 101,
The slice level value as a digital value via 0 is converted again into an analog signal by the D / A converter 102 and supplied to the non-inverting input terminal of the comparator 91. Also,
A slice level value as a preset suitability value is stored in the memory 10.

In such a state, when the phase difference between the rising edge and the falling edge is large, as shown in FIGS. Outputs a judgment signal.

Thus, the CPU 50 determines that the slice level value has become inappropriate when the slice level abnormality determination signal is supplied during the reproduction of the sector of the predetermined block, Is read out, converted into an analog value by the D / A converter 102, and output to the non-inverting input terminal of the comparator 91 as a slice level.

Thereafter (after a predetermined time), the CPU 50
The D / A converter 102 converts the digital value supplied from the A / D converter 101 into an analog value as it is, and outputs the analog value to the non-inverting input terminal of the comparator 91 as a slice level.

As a result, when the phase difference between the rising edge and the falling edge is large, the slice level supplied to the comparator 91 in the auto slice circuit 93 is changed to an appropriate value. Can be avoided that the slice level value of the auto slice circuit that generates the data is shifted due to a defect or a data pattern.

Next, a seventh embodiment will be described.

In the sixth embodiment described above, when the phase difference between the rising edge and the falling edge is large, the CPU 50
The slice level value output from the
Although the case of changing to the appropriate value set to 0 has been described, in the seventh embodiment, the A / A as the output of the integrator 92 in the auto slice circuit 93 when the VFO is pulled in.
The average value of the digital values from the D converter 101 is stored in the memory 1
0, and when the phase difference between the rising edge and the falling edge is large, that is, when the slice level determination circuit 10
When the slice level abnormality determination signal of No. 5 is output, C
The slice level value output from the PU 50 is stored in the memory 10
The average value is changed to the average value stored in.

The description of the same parts as in the sixth embodiment is omitted.

That is, as shown in FIGS. 25, 26 and 27, the output of the integrator 92 of the auto slice circuit 93 is converted into a digital value by the A / D converter 101.
The slice level value as a digital value is again converted to an analog signal by the D / A converter 102 via the CPU 50 and supplied to the non-inverting input terminal of the comparator 91.

In such a state, when the check result from the IED check circuit 78 is correct, the header detection signal generation circuit 80 outputs a signal corresponding to the ID number supplied from the address comparison circuit 79 and an address. According to the address mark detection signal from the mark detection circuit 76 and the number of bytes counted by the data clock from the demodulation circuit 75, a header detection signal is generated corresponding to the end of the mirror mark area and output to the CPU 50. .

Then, the CPU 50 determines the VFO3 area according to the count value from a binary counter (not shown) that counts the number of bytes based on the header detection signal from the header detection signal generation circuit 80, and determines this VFO3 area. The integrator 9 of the auto slice circuit 93
The average value of the digital values supplied from 2 through the A / D converter 101 is determined as an appropriate slice level and stored in the memory 10.

When the phase difference between the rising edge and the falling edge is large, as shown in FIGS. 23 (f) and 23 (g), a slice level abnormality determination signal is output from the slice level determination circuit 105 to the CPU 50. I do.

Thus, the CPU 50 determines that the slice level value has become improper when the slice level abnormality determination signal is supplied during the reproduction of the sector of the predetermined block. A digital value (average value of the slice level at the time of VFO pull-in) is read out, converted to an analog value by the D / A converter 102, and output to the non-inverting input terminal of the comparator 91 as a slice level.

Thereafter, the CPU 50 again converts the digital value supplied from the A / D converter 101 into a D / A
The converter 102 converts the analog value into an analog value and outputs the analog value to the non-inverting input terminal of the comparator 91 as a slice level.

As a result, when the phase difference between the rising edge and the falling edge is large, the slice level supplied to the comparator 91 in the auto slice circuit 93 is changed to an appropriate value. Can be avoided that the slice level value of the auto slice circuit that generates the data is shifted due to a defect or a data pattern.

Next, an eighth embodiment will be described.

In the sixth embodiment described above, when the phase difference between the rising edge and the falling edge is large, the CPU 50
The slice level value output from the
Although the case of changing to the appropriate value set to 0 has been described, the eighth embodiment includes the synchronization code detection circuit 81 described in the first embodiment, and the auto slice circuit is provided every time the synchronization code is detected. The digital value from the A / D converter 101 as the output of the integrator 92 in the memory 93 is stored in the memory 10 as an appropriate value, and when no synchronization code is detected, the slice level value output from the CPU 50 is stored. This is changed to the appropriate value stored in the memory 10.

The description of the same parts as those in the sixth embodiment will be omitted.

That is, as shown in FIGS. 28, 26 and 27, the output of the integrator 92 of the auto slice circuit 93 is converted into a digital value by the A / D converter 101,
The slice level value as a digital value is again converted to an analog signal by the D / A converter 102 via the CPU 50 and supplied to the non-inverting input terminal of the comparator 91. Further, as shown in FIG.
1, a synchronous code detection signal is supplied to the CPU 50.

In such a state, when the check result from the IED check circuit 78 is correct, the header detection signal generation circuit 80 outputs the signal corresponding to the ID number supplied from the address comparison circuit 79 and the address According to the address mark detection signal from the mark detection circuit 76 and the number of bytes counted by the data clock from the demodulation circuit 75, a header detection signal is generated at the end of the mirror mark area, and the synchronization code detection is performed. Output to the circuit 81.

Then, the synchronous code detecting circuit 81
The number of bytes is counted based on the header detection signal from the header detection signal generation circuit 80, and the shift is performed every time a channel clock is supplied from the PLL circuit 72 while corresponding to the data area according to the count value. Register 74
Is compared with a 16-bit synchronization code pattern (common code pattern), and when they match, a synchronization code detection signal is output to the CPU 50.

Then, when the synchronous code detection signal is supplied from the synchronous code detection circuit 81, the CPU 50
The digital value supplied from the integrator 92 of the auto slice circuit 93 via the A / D converter 101 is determined as an appropriate slice level, and stored in the memory 10.

When the phase difference between the rising edge and the falling edge is large, as shown in FIGS. 23 (f) and 23 (g), the slice level judgment circuit 105 sends a slice level abnormality judgment signal to the CPU 50. Output.

Thus, the CPU 50 determines that the slice level value has become improper when the slice level abnormality determination signal is supplied during the reproduction of the sector of the predetermined block. Is read out, converted into an analog value by the D / A converter 102, and output to the non-inverting input terminal of the comparator 91 as a slice level.

Thereafter, the CPU 50 again converts the digital value supplied from the A / D converter 101 into a D / A
The converter 102 converts the analog value into an analog value and outputs the analog value to the non-inverting input terminal of the comparator 91 as a slice level.

As a result, when the phase difference between the rising edge and the falling edge is large, the slice level supplied to the comparator 91 in the auto slice circuit 93 is changed to an appropriate value. Can be avoided that the slice level value of the auto slice circuit that generates the data is shifted due to a defect or a data pattern.

[0198]

As described in detail above, according to the present invention, it is possible to provide an optical disk apparatus capable of performing stable reproduction signal processing regardless of a data pattern or a defect.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an optical disk system according to an embodiment of the present invention.

FIG. 2 is an exemplary plan view showing a schematic configuration of the optical disc shown in FIG. 1;

FIG. 3 is a diagram showing a schematic configuration of the optical disc shown in FIG. 1;

FIG. 4 is a diagram for explaining the number of rotations for each zone of the optical disc shown in FIG. 1 and the number of sectors in one track;

FIG. 5 is a diagram for explaining a configuration of an ECC block of the optical disc shown in FIG. 1;

FIG. 6 is an exemplary view for explaining a configuration of an ECC block of the optical disc shown in FIG. 1;

FIG. 7 is an exemplary view for explaining the configuration of each sector of the ECC block shown in FIG. 6;

FIG. 8 is a diagram for explaining preformat data in a header section of the optical disc shown in FIG. 2;

FIG. 9 is a diagram showing a sector format of the ECC block shown in FIG. 6;

FIG. 10 is a block diagram for explaining a configuration of a data reproducing circuit according to the first embodiment;

FIG. 11 is a block diagram for explaining a configuration of a main part of the data reproduction circuit according to the first embodiment;

FIG. 12 is a circuit diagram for explaining a configuration of a main part of the data reproduction circuit according to the first embodiment;

FIG. 13 is a view for explaining signal waveforms of main parts of the data reproduction circuit shown in FIG. 12;

FIG. 14 is a waveform chart for explaining a conventional slice level fluctuation state.

FIG. 15 is a block diagram for explaining a configuration of a data reproducing circuit according to the second and third embodiments.

FIG. 16 is a block diagram for explaining a configuration of a main part of a data reproduction circuit according to the second and third embodiments.

FIG. 17 is a circuit diagram for explaining a configuration of a main part of the data reproduction circuit according to the second and third embodiments.

FIG. 18 is a block diagram for explaining a configuration of a data reproducing circuit according to a fourth embodiment;

FIG. 19 is a block diagram illustrating a configuration of a data reproducing circuit according to a fifth embodiment;

FIG. 20 is a block diagram for explaining a configuration of a main part of a data reproduction circuit according to a fifth embodiment;

FIG. 21 is a circuit diagram illustrating a configuration of a main part of a data reproduction circuit according to a fifth embodiment;

FIG. 22 is an exemplary view for explaining signal waveforms of main parts of the data reproduction circuit shown in FIG. 21;

FIG. 23 is an exemplary view for explaining signal waveforms of main parts of the data reproduction circuit shown in FIG. 21;

FIG. 24 is a waveform chart for explaining a signal waveform associated with a slice level fluctuation state and a phase shift outputted from a low-pass filter.

FIG. 25 is a block diagram for explaining a configuration of a data reproducing circuit according to sixth and seventh embodiments;

FIG. 26 is a block diagram for explaining a configuration of a main part of a data reproducing circuit according to sixth and seventh embodiments;

FIG. 27 is a circuit diagram for explaining a configuration of a main part of a data reproduction circuit according to sixth and seventh embodiments.

FIG. 28 is a block diagram illustrating a configuration of a data reproduction circuit according to an eighth embodiment;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Optical disk 10 ... Memory 25 ... Optical head 38 ... Data reproduction circuit 50 ... CPU 71 ... Binarization circuit 72 ... PLL circuit 81 ... Synchronization code detection circuit 82 ... Synchronization code non-detection circuit 90 ... Changeover switch 91 ... Comparator 92 ... Integrator 93 ... Auto slice circuit 96 ... Edge detection circuit

Claims (11)

[Claims] 1. An optical disk device for reproducing data recorded on an optical disk, comprising: an optical head for reproducing data from the optical disk; and a reproduction signal reproduced by the optical head, wherein a rectangular wave is formed based on a slice level. Conversion means for generating a slice level from the square wave, edge detection means for outputting a square wave edge detection signal from the conversion means, and an edge detection signal from the edge detection means.
Generating means for generating a clock for reproduction; demodulating means for demodulating an edge detection signal from the edge detecting means into reproduction data based on the clock for reproduction generated by the generating means; Determining means for determining a level abnormality; and setting means for setting the slice level of the converting means to a predetermined value when the determining means determines that the slice level is abnormal. Optical disk device. 2. An optical disc device for reproducing data from an optical disc on which data is recorded and on which a synchronization code is recorded at predetermined intervals of the data, based on the synchronization code. An optical head for performing the conversion, a conversion signal for converting a reproduction signal reproduced by the optical head into a rectangular wave based on a slice level and generating a slice level from the rectangular wave, and an edge detection signal of the rectangular wave from the conversion unit Based on an edge detection signal from the edge detection means.
Generating means for generating a clock for reproduction; demodulating means for demodulating the edge detection signal from the edge detecting means into reproduction data based on the clock for reproduction generated by the generating means; Judging means for judging an abnormality in the slice level of the conversion means when the synchronization code recorded at each of the predetermined intervals is not detected by the demodulated data to be obtained; Setting means for setting a slice level of the conversion means to an initial value when the determination is made. 3. A comparator for converting a reproduction signal into a rectangular wave based on a slice level, and an integrator for generating a slice level from the rectangular wave by integrating an output signal from the comparator. 3. The optical disc apparatus according to claim 2, wherein the setting means sets a slice level to an initial value by discharging a charging voltage of the integrator. 4. An optical disc device for reproducing data from an optical disc on which data is recorded and on which a synchronization code is recorded at predetermined intervals of the data, based on the synchronization code. An optical head for performing the conversion, a conversion signal for converting a reproduction signal reproduced by the optical head into a rectangular wave based on a slice level and generating a slice level from the rectangular wave, and an edge detection signal of the rectangular wave from the conversion unit Based on an edge detection signal from the edge detection means.
Generating means for generating a clock for reproduction; demodulating means for demodulating the edge detection signal from the edge detecting means into reproduction data based on the clock for reproduction generated by the generating means; When the synchronization code recorded at each of the predetermined intervals is not detected by the demodulated data to be detected, a determination unit for determining an abnormality in the slice level of the conversion unit, and an initial value of the slice level of the conversion unit are stored. Storage means; and setting means for setting a slice level of the conversion means to an initial value read from the storage means when the determination means determines that the slice level of the conversion means is abnormal. Optical disk device. 5. An optical disk comprising: a synchronization code area in which a synchronization code is recorded; and a data area in which data is recorded and a synchronization code is recorded at predetermined intervals of data. In an optical disk device for reproducing data, an optical head for reproducing data from the optical disk, a conversion unit for converting a reproduction signal reproduced by the optical head into a rectangular wave based on a slice level, First generating means for generating a slice level used by the converting means from the rectangular wave; edge detecting means for outputting an edge detecting signal of the rectangular wave from the converting means; and an edge detecting signal from the edge detecting means. hand,
Second generating means for generating a clock for reproduction; demodulating means for demodulating an edge detection signal from the edge detecting means into reproduced data based on the clock for reproduction generated by the second generating means; A determination unit for determining an abnormality of a slice level used by the conversion unit when the synchronization code recorded at the predetermined interval is not detected by the demodulation data demodulated by the demodulation unit; Storage means for storing, as a reference value, an average value of slice levels generated by the first generation means when demodulating the synchronization code in the synchronization code area; Setting means for setting a slice level of the conversion means to a reference value read from the storage means when an abnormality is determined. Optical disc apparatus according to claim. 6. An optical disc apparatus for reproducing data from an optical disc on which data is recorded and on which a synchronization code is recorded at predetermined intervals of the data, based on the synchronization code. An optical head for performing the conversion, a conversion signal for converting a reproduction signal reproduced by the optical head into a rectangular wave based on a slice level and generating a slice level from the rectangular wave, and an edge detection signal of the rectangular wave from the conversion unit Based on an edge detection signal from the edge detection means.
Generating means for generating a clock for reproduction; demodulating means for demodulating the edge detection signal from the edge detecting means into reproduction data based on the clock for reproduction generated by the generating means; First determining means for determining whether or not the synchronization code recorded at each of the predetermined intervals is detected from the demodulated data to be detected; and each time the synchronization code is detected by the first determining means, the conversion is performed. Storage means for storing a slice level of the means as a reference value; and
A second judging means for judging an abnormality of the slice level of the converting means; and when the second judging means judges an abnormal slice level of the converting means, the slice level of the converting means is stored in the storage means. An optical disk device, comprising: setting means for setting a read reference value. 7. An optical disk device for reproducing data recorded on an optical disk, comprising: an optical head for reproducing data from the optical disk; and a reproduction signal reproduced by the optical head, wherein a rectangular signal is reproduced based on a slice level. Converting means for converting the rectangular wave generated by the converting means into a slice level used by the converting means; edge detecting means for outputting a rectangular wave edge detection signal from the converting means; Based on the edge detection signal from the edge detection means,
Second generating means for generating a clock for reproduction; demodulating means for demodulating an edge detection signal from the edge detecting means into reproduced data based on the clock for reproduction generated by the second generating means; A third generation unit that generates a rising edge signal and a falling edge signal based on the rectangular wave from the conversion unit and the edge detection signal from the edge detection unit; and a rising edge from the third generation unit. When the phase difference between the edge signal and the falling edge signal is larger than a predetermined value, a judging means for judging an abnormality of the slice level of the converting means. The judging means judges an abnormal slice level of the converting means. Setting means for setting the slice level of the conversion means to an initial value. 8. The method according to claim 1, wherein the first generating means comprises an integrator, and the setting means sets a slice level to an initial value by discharging a charging voltage of the integrator. The optical disk device according to claim 7, wherein 9. An optical disk device for reproducing data recorded on an optical disk, comprising: an optical head for reproducing data from the optical disk; and a reproduction signal reproduced by the optical head, wherein a rectangular wave is formed based on a slice level. Converting means for converting the rectangular wave generated by the converting means into a slice level used by the converting means; edge detecting means for outputting a rectangular wave edge detection signal from the converting means; Based on the edge detection signal from the edge detection means,
Second generating means for generating a clock for reproduction; demodulating means for demodulating an edge detection signal from the edge detecting means into reproduced data based on the clock for reproduction generated by the second generating means; A third generation unit that generates a rising edge signal and a falling edge signal based on the rectangular wave from the conversion unit and the edge detection signal from the edge detection unit; and a rising edge from the third generation unit. When the phase difference between the edge signal and the falling edge signal is larger than a predetermined value, a determination unit that determines an abnormality of the slice level of the conversion unit, and a storage unit that stores an initial value of the slice level of the conversion unit. When the determination means determines that the slice level of the conversion means is abnormal, the slice level of the conversion means is set to an initial value read from the storage means. Optical disk apparatus characterized by comprising a setting means. 10. An optical disk comprising: a synchronization code area in which a synchronization code is recorded; and a data area in which data is recorded and a synchronization code is recorded at predetermined intervals of data. In an optical disk device for reproducing data, an optical head for reproducing data from the optical disk, a conversion unit for converting a reproduction signal reproduced by the optical head into a rectangular wave based on a slice level, First generating means for generating a slice level used by the converting means from the rectangular wave; edge detecting means for outputting an edge detecting signal of the rectangular wave from the converting means; and an edge detecting signal from the edge detecting means. hand,
Second generating means for generating a clock for reproduction; demodulating means for demodulating an edge detection signal from the edge detecting means into reproduced data based on the clock for reproduction generated by the second generating means; A third generation unit that generates a rising edge signal and a falling edge signal based on the rectangular wave from the conversion unit and the edge detection signal from the edge detection unit; and a rising edge from the third generation unit. When the phase difference between the edge signal and the falling edge signal is larger than a predetermined value, the conversion means determines the slice level abnormality, and the demodulation means demodulates the synchronization code in the synchronization code area. A storage means for storing, as a reference value, an average value of slice levels generated by the first generation means; When abnormality of Sureberu is determined, the optical disk apparatus characterized by the slice level of the conversion means equipped with a setting means for setting the read out reference value from said storage means. 11. An optical disc apparatus for reproducing data from an optical disc on which data is recorded and on which a synchronization code is recorded at predetermined intervals of the data, based on the synchronization code. An optical head for performing the conversion, a conversion unit for converting a reproduction signal reproduced by the optical head into a rectangular wave based on a slice level, and a first generation for generating a slice level used by the conversion unit from the rectangular wave by the conversion unit Means, edge detection means for outputting a rectangular wave edge detection signal from the conversion means, and based on the edge detection signal from the edge detection means,
Second generating means for generating a clock for reproduction; demodulating means for demodulating an edge detection signal from the edge detecting means into reproduction data based on the clock for reproduction generated by the second generating means. Detecting means for detecting a synchronization code recorded at each of the predetermined intervals based on demodulated data demodulated by the demodulation means; and slices generated by the first generation means each time the synchronization code is detected by the detection means. Storage means for storing a level as a reference value; third generation means for generating a rising edge signal and a falling edge signal based on the rectangular wave from the conversion means and the edge detection signal from the edge detection means; When the phase difference between the rising edge signal and the falling edge signal from the third generation means is larger than a predetermined value, the slice of the conversion means Determining means for determining a bell abnormality; setting means for setting the slice level of the converting means to a reference value read from the storage means when the determining means determines that the slice level is abnormal; An optical disk device comprising: