JPH1153426A - Printed board designing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To design a printed board of high quality with high efficiency by feeding various restriction conditions back to a circuit diagram base and putting the restriction conditions, etc., back to the circuit diagram base. SOLUTION: A restriction condition output part 13 puts final wiring restriction conditions and parameters of simulation together and outputs an alteration and addition restriction condition file 15. The restriction condition output file 15 outputs what restrictions are imposed on which signal or how alterations are made. Further, name changes of components are also outputted. A back annotation processing is performed by supplying circuit diagram data 5 and restriction condition output file 15 to a back annotation processing part 16. The back annotation process part 16 can reflect the added wiring restrictions and the parameter values of the simulation on the circuit diagram. Then a restriction condition added circuit diagram 17 and restriction condition added circuit diagram data 18 after back annotation are outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a printed circuit board design system for performing automatic wiring using a computer.

[0002]

2. Description of the Related Art In modern electronic equipment and electronic equipment, it is common to use one or more printed circuit boards for forming an electronic circuit and interconnect a large number of active and passive electric components by the printed circuit boards. It is a target. As the performance of these electronic devices and the like becomes higher, the number of printed circuit boards used is increased, and the complexity is further increased. In order to design such a complicated multilayer printed circuit board, it is common to utilize a CAD system and design in cooperation with a designer. This system is called a package design logic circuit diagram creation CAD system or a layout CAD system.

Japanese Patent Laid-Open Publication No. Hei 7-98725 discloses a conventional wiring processing system. That is, at the time of checking the logical quality of a high-density printed circuit board, if there is an improper connection in a portion where the necessity of the logical change has occurred, an error message is output and the existing wiring pattern in that portion is automatically deleted.
When automatic wiring processing is performed on the last connected portion, it may be determined that the last connected portion does not move the existing wiring pattern and patterning cannot be performed using only an empty channel. In that case, the priority order of the existing wiring patterns is determined according to the type and use of the signal, a change order flag is set, and according to the attribute, the existing wiring patterns are moved from the lower priority wiring patterns. There is disclosed a wiring processing method in which when the connection is not possible, the priority is sequentially increased and the connection is performed.

The logical change is fed back to logical information,
Thereafter, the wiring pattern that does not match the logical information is automatically deleted. In addition, a changeable order flag is provided for each of the non-changeable wiring patterns whose electrical characteristic specifications are severely restricted and cannot be moved, those that are not desired to be moved as much as possible, and those that can be moved, for each rank. This attribute is defined in the logical information.
Based on this attribute, it moves from the rank pattern that can be moved by the changeable order flag during the automatic wiring processing. Wiring channels are secured while minimizing the movement of wiring patterns having severe electrical characteristics.

In order to promptly check the route of the logic pattern and the moved existing wiring pattern without omission, an identification flag is automatically added to the changed and moved wiring pattern. When outputting a wiring pattern diagram such as a screen display / plotter output, a wiring pattern whose logic has been changed and moved is distinguished from other wiring patterns.

[0006]

In the above-described conventional wiring processing method, when a pattern is currently being designed or when it is necessary to change the logic after manufacturing, the wiring pattern having severe electrical characteristics is affected. It is intended to allow design changes without the need.

Further, the logical change must return to the logical information (processing design data), which has been a factor of delaying the pattern design.

Further, consideration is given only to the same design data. At present, this design data may be used to design other printed circuit boards.Simulation is repeated during pattern design, and component changes, pattern constraint changes, and simulation parameters are also changed several times. , These changed information are not reflected on the circuit diagram data. Therefore, it is necessary to register or correct parameters each time a simulation is performed.

Accordingly, an object of the present invention is to provide various CAD systems with wiring constraints and various simulation conditions for automatic wiring, and to feed back these various constraints to the circuit diagram base, and to provide various constraint conditions to the circuit diagram base. This enables automatic wiring and simulation under the same constraints again when redesigning a printed circuit board or designing using this circuit diagram, thereby enabling high-quality and highly efficient printed circuit board design. The purpose is to provide a printed circuit board design method.

[0010]

In order to solve the above-mentioned problems, a printed circuit board designing method according to the present invention uses a CAD system and designs a printed circuit board through a plurality of processing steps in cooperation with an operator. In the design method, the constraint conditions defined on the net in each of the processing steps are output to a constraint file, and the defined net name, the definition condition, and the processing step name are output to the constraint file. The file and the circuit diagram data are transferred to the back annotation processing unit, and the various constraint conditions are written on the circuit diagram in which the net name is described.

Here, when writing the constraint condition, a design rule check function is provided so that the constraint condition does not intersect with the circuit symbol and the wiring. When the intersection occurs, the design rule check function is provided near the defined net name. The constraint condition is not described, but described in the margin.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a printed circuit board design system according to the present invention will be described below in detail with reference to the accompanying drawings. However, needless to say, the present invention is not limited to only the specific embodiment.

First, a flow chart of a preferred embodiment of a printed circuit board design system according to the present invention will be described with reference to FIG. Based on the handwritten circuit diagram 1, design data (netlist data) 4 is created by a circuit diagram registration CAD system. At this time, the wiring constraint condition 3 is also input to the circuit diagram registration CAD system 2. After confirming the contents registered in the circuit diagram registration CAD system 2, the netlist data 4
To the layout CAD system 6. The circuit diagram registration CAD system 2 also outputs circuit diagram data 5. An example of the circuit diagram data 5 is shown in FIG. The circuit diagram data 5 describes information such as coordinates, net names, and coordinates of components on each sheet of the circuit diagram in the circuit diagram.

In the layout CAD system 6, an automatic arrangement process 7 is performed. Automatic placement is performed based on wiring constraint conditions 3 registered in advance. In the automatic placement processing 7, placement is performed in accordance with wiring restrictions (one-stroke, shortest, etc.), component height restrictions, and thermal restrictions. After the automatic placement processing 7, an automatic wiring processing 8 is performed. This automatic wiring process 8
Performs the automatic wiring processing based on the wiring restriction condition 3 input in advance similarly to the automatic arrangement processing 7. For the non-wiring correction after the automatic wiring, the operator performs the non-wiring correction processing 9 manually.

At the stage when all wiring operations are completed, various simulations 10 are performed. For example, the simulation 10 here is mainly for simulation of a transmission path such as delay and crosstalk. In this simulation 10, the resistance value of the resistor is changed, a filter component is added to prevent power supply noise, a ground shield of a signal pattern,
Various corrections such as line length correction of Max and Min are performed, and a printed circuit board that does not cause a problem when commercialized is designed. In the simulation 10, a wiring constraint is input in advance and a simulation is performed. Leakage of wiring constraints, input errors, or unexpected situations may occur.

This simulation (SIM) result 11
If the result is not satisfactory, change 12 of the wiring constraint conditions such as change of parameters (constants) of various simulations and change of components is performed. After these changes, automatic wiring processing 8 or pattern correction processing 9 by an operator is performed again. These processing decisions are repeated until the simulation result 11 becomes good. If the simulation result 11 passes, the constraint condition output unit 1
3, information on the initial wiring constraint condition 3 and the changed or added constraint condition 12 are sent.

FIG. 3 shows an example of the added constraint condition 12. The constraint output unit 13 summarizes the final wiring constraint and simulation parameters,
The change / additional constraint file 15 is output. This constraint condition output file 15 outputs which signal is given what kind of constraint or is changed. Also, a change in the part name (change in resistance value, etc.) is output.

When the simulation 10 is completed, an artwork (ARTWORK) process 14 is performed, and a production operation of printed circuit board manufacturing data 19 is performed. The data obtained in this operation is passed to a printed circuit board manufacturer, and the printed circuit board is manufactured.

Next, the back annotation processing will be described. This back annotation processing is performed by giving the circuit diagram data 5 and the constraint condition output file 15 to the back annotation processing unit 16. The back annotation processing unit 16 can reflect the added wiring constraints and simulation parameter values in the circuit diagram. This is because there is a table indicating whether or not the signal name of each sheet in the circuit diagram data 5 and its coordinate data exist. The wiring constraint of the signal name output to the constraint file this time is represented by the signal name. Paste near the coordinates of.

FIG. 4 is an image diagram showing the above-described attached wiring restrictions. At this time, make sure that the attached constraints do not overlap with other component symbols, wiring, and signal names.
(Design rule check). In the case of overlap, a note is instructed, and a constraint condition is attached to the margin. These processes are performed, and the constraint adding circuit diagram 17 and the constraint adding circuit diagram data 18 after the back annotation are output. Next time, when a revised design, a new logical change, or a diversion design occurs, the design can be performed using the constraint condition adding circuit diagram 17 and the constraint condition adding circuit diagram data 18.

[0021]

As described above, according to the present invention, a pattern or a component whose wiring constraint is changed during the pattern design can be reflected in the initial circuit diagram. Can be executed without any problem. Therefore, automatic wiring and simulation can be performed again under the same constraint conditions, and a high-quality and high-efficiency printed circuit board can be designed.

[Brief description of the drawings]

FIG. 1 is a flowchart of a preferred embodiment of a printed circuit board design method according to the present invention.

FIG. 2 is a circuit diagram registration CA in the flowchart of FIG. 1;
It is a figure showing an example of the circuit diagram data obtained from D system.

FIG. 3 is a diagram illustrating an example of a constraint condition changed or added in the flowchart of FIG. 1;

FIG. 4 is an image diagram of a constraint condition file in the flowchart of FIG. 1;

[Explanation of symbols]

 1-18 processing steps

Claims (3)

[Claims] In a printed circuit board design method for designing a printed circuit board through a plurality of processing steps in cooperation with an operator using a CAD system, the constraints defined on the net in each of the processing steps are stored in a constraint file. The constraint file outputs the defined net name, the definition condition, and the processing step name. The constraint file and the circuit diagram data are passed to a back annotation processing unit, and the circuit in which the net name is described. A printed circuit board design method characterized by writing the above-mentioned various constraint conditions on a drawing. 2. A design rule check function for writing the constraint condition so that the constraint condition does not intersect with a circuit symbol and a wiring.
Printed circuit board design method described in 1. 3. The printed circuit board design method according to claim 2, wherein when the intersection occurs, the constraint condition is not described near the defined net name and is written in a margin.