JPH11506852A - 多数のバスマスタと共用レベル２キャッシュとを備える多レベルキャッシュシステムでのキャッシュスヌーピングオーバーヘッドの低減 - Google Patents

多数のバスマスタと共用レベル２キャッシュとを備える多レベルキャッシュシステムでのキャッシュスヌーピングオーバーヘッドの低減

Info

Publication number
JPH11506852A
JPH11506852A JP9501132A JP50113297A JPH11506852A JP H11506852 A JPH11506852 A JP H11506852A JP 9501132 A JP9501132 A JP 9501132A JP 50113297 A JP50113297 A JP 50113297A JP H11506852 A JPH11506852 A JP H11506852A
Authority
JP
Japan
Prior art keywords
cache
level
address
tag
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9501132A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11506852A5 (enExample
Inventor
ボウルズ，ジェイムズ・イー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JPH11506852A publication Critical patent/JPH11506852A/ja
Publication of JPH11506852A5 publication Critical patent/JPH11506852A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP9501132A 1995-06-05 1996-06-04 多数のバスマスタと共用レベル２キャッシュとを備える多レベルキャッシュシステムでのキャッシュスヌーピングオーバーヘッドの低減 Pending JPH11506852A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/462,985 US5740400A (en) 1995-06-05 1995-06-05 Reducing cache snooping overhead in a multilevel cache system with multiple bus masters and a shared level two cache by using an inclusion field
US08/462,985 1995-06-05
PCT/US1996/008592 WO1996039666A1 (en) 1995-06-05 1996-06-04 Reducing cache snooping overhead in a multilevel cache system with multiple bus masters and a shared level two cache

Publications (2)

Publication Number Publication Date
JPH11506852A true JPH11506852A (ja) 1999-06-15
JPH11506852A5 JPH11506852A5 (enExample) 2004-07-08

Family

ID=23838479

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9501132A Pending JPH11506852A (ja) 1995-06-05 1996-06-04 多数のバスマスタと共用レベル２キャッシュとを備える多レベルキャッシュシステムでのキャッシュスヌーピングオーバーヘッドの低減

Country Status (4)

Country Link
US (2) US5740400A (enExample)
EP (1) EP0834130A1 (enExample)
JP (1) JPH11506852A (enExample)
WO (1) WO1996039666A1 (enExample)

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US7870340B2 (en) 2002-05-06 2011-01-11 Sony Computer Entertainment Inc. Methods and apparatus for controlling hierarchical cache memory

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US5867675A (en) * 1996-08-06 1999-02-02 Compaq Computer Corp Apparatus and method for combining data streams with programmable wait states
US5897656A (en) * 1996-09-16 1999-04-27 Corollary, Inc. System and method for maintaining memory coherency in a computer system having multiple system buses
US6115794A (en) * 1997-04-14 2000-09-05 International Business Machines Corporation Method and system of providing a pseudo-precise inclusivity scheme in a sectored cache memory for maintaining cache coherency within a data-processing system
US6374330B1 (en) * 1997-04-14 2002-04-16 International Business Machines Corporation Cache-coherency protocol with upstream undefined state
US6233665B1 (en) * 1997-05-27 2001-05-15 Unisys Corporation Mapping shared DRAM address bits by accessing data memory in page mode cache status memory in word mode
US5996048A (en) * 1997-06-20 1999-11-30 Sun Microsystems, Inc. Inclusion vector architecture for a level two cache
US6496904B1 (en) * 1999-05-05 2002-12-17 Compaq Information Technologies Group, L.P. Method and apparatus for efficient tracking of bus coherency by using a single coherency tag bank
US6591341B1 (en) * 2000-03-31 2003-07-08 Intel Corporation Multilevel cache system and method having a merged tag array to store tags for multiple data arrays
EP1304620A1 (en) * 2001-10-17 2003-04-23 Texas Instruments Incorporated Cache with selective write allocation
US20030115402A1 (en) * 2001-11-16 2003-06-19 Fredrik Dahlgren Multiprocessor system
US7027064B2 (en) * 2002-02-28 2006-04-11 Sun Microsystems, Inc. Active block write-back from SRAM cache to DRAM
US7577816B2 (en) * 2003-08-18 2009-08-18 Cray Inc. Remote translation mechanism for a multinode system
US8307194B1 (en) 2003-08-18 2012-11-06 Cray Inc. Relaxed memory consistency model
US7543133B1 (en) 2003-08-18 2009-06-02 Cray Inc. Latency tolerant distributed shared memory multiprocessor computer
US7735088B1 (en) 2003-08-18 2010-06-08 Cray Inc. Scheduling synchronization of programs running as streams on multiple processors
US7421565B1 (en) 2003-08-18 2008-09-02 Cray Inc. Method and apparatus for indirectly addressed vector load-add -store across multi-processors
US7366873B1 (en) 2003-08-18 2008-04-29 Cray, Inc. Indirectly addressed vector load-operate-store method and apparatus
US7437521B1 (en) 2003-08-18 2008-10-14 Cray Inc. Multistream processing memory-and barrier-synchronization method and apparatus
US7743223B2 (en) * 2003-08-18 2010-06-22 Cray Inc. Decoupling of write address from its associated write data in a store to a shared memory in a multiprocessor system
US7519771B1 (en) 2003-08-18 2009-04-14 Cray Inc. System and method for processing memory instructions using a forced order queue
US7503048B1 (en) 2003-08-18 2009-03-10 Cray Incorporated Scheduling synchronization of programs running as streams on multiple processors
US7334110B1 (en) 2003-08-18 2008-02-19 Cray Inc. Decoupled scalar/vector computer architecture system and method
GB2422926B (en) * 2005-02-04 2008-10-01 Advanced Risc Mach Ltd Data processing apparatus and method for controlling access to memory
US7386682B2 (en) * 2005-02-11 2008-06-10 International Business Machines Corporation Reducing number of rejected snoop requests by extending time to respond to snoop request
JP4189402B2 (ja) * 2005-02-21 2008-12-03 パナソニック株式会社 キャッシュ回路
TWI277877B (en) * 2005-03-08 2007-04-01 Via Tech Inc Method and related apparatus for monitoring system bus
US7478769B1 (en) 2005-03-09 2009-01-20 Cray Inc. Method and apparatus for cooling electronic components
JP4990505B2 (ja) * 2005-04-04 2012-08-01 株式会社日立製作所 記憶制御装置及びストレージシステム
EP1986101B1 (en) * 2006-02-14 2012-06-20 Fujitsu Ltd. Coherency maintaining device and coherency maintaining method
US20080104333A1 (en) * 2006-10-31 2008-05-01 Veazey Judson E Tracking of higher-level cache contents in a lower-level cache
US8463458B2 (en) * 2009-09-03 2013-06-11 Johnson Outdoors Marine Electronics, Inc. Depth highlight, depth highlight range, and water level offset highlight display and systems
JP5440067B2 (ja) * 2009-09-18 2014-03-12 富士通株式会社 キャッシュメモリ制御装置およびキャッシュメモリ制御方法
US9418009B2 (en) * 2013-12-27 2016-08-16 Intel Corporation Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory
US10102129B2 (en) 2015-12-21 2018-10-16 Intel Corporation Minimizing snoop traffic locally and across cores on a chip multi-core fabric
US9983995B2 (en) * 2016-04-18 2018-05-29 Futurewei Technologies, Inc. Delayed write through cache (DWTC) and method for operating the DWTC
US11301403B2 (en) 2019-03-01 2022-04-12 Micron Technology, Inc. Command bus in memory

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US5297269A (en) * 1990-04-26 1994-03-22 Digital Equipment Company Cache coherency protocol for multi processor computer system
US5249284A (en) * 1990-06-04 1993-09-28 Ncr Corporation Method and system for maintaining data coherency between main and cache memories
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US5564035A (en) * 1994-03-23 1996-10-08 Intel Corporation Exclusive and/or partially inclusive extension cache system and method to minimize swapping therein
US5584013A (en) * 1994-12-09 1996-12-10 International Business Machines Corporation Hierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache is prevented when the cache entry is the only inclusive entry in the first level cache

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7870340B2 (en) 2002-05-06 2011-01-11 Sony Computer Entertainment Inc. Methods and apparatus for controlling hierarchical cache memory

Also Published As

Publication number Publication date
US5740400A (en) 1998-04-14
EP0834130A1 (en) 1998-04-08
US5796980A (en) 1998-08-18
WO1996039666A1 (en) 1996-12-12

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