JPH1146175A - Method and circuit for detecting failure of time division multiplexing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform failure detection with high efficiency by fetching radio transmission data to a time division multiplexing circuit at the same time of sending the radio transmission data and detecting a failure of the time division multiplexing circuit based on the radio transmission data before sending and the fetched radio transmission data. SOLUTION: When a mode for failure detection is set, the time division multiplexing circuit 1 serially sends radio transmission data which is written to a sending data register 11 by a CPU 2 that is outside the circuit from a radio data sending terminal 3a. At the same time, the sent radio transmission data is fed back to a radio data receiving terminal 3b and accumulated in a receiving data register 12. After that, a comparing part 13 performs batch comparison of data of the register 11 with data of the register 12 with full bits (e.g. 160 bits), and a result of the comparison result is sent to the CPU 2. The CPU 2 performs decision processing of a failure state based on the data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting a failure in a time division multiplexing circuit having a failure detection function and a circuit thereof.

[0002]

2. Description of the Related Art As a time division multiplexing circuit in the TDMA-TDD system, there is a time division multiplexing circuit for a portable telephone. However, for detecting a failure in this conventional circuit, a transmission slot and a reception slot as shown in FIG. A time division method assigned by a half cycle is used, and a function of transmitting and receiving wireless data from a time division multiplexing circuit is clearly separated.

[0003]

In the above conventional example, since the transmission function and the reception function of the radio data are clearly separated, the time division multiplexing circuit performs the transmission and simultaneously feeds back the data to itself. Receiving data, storing data in a reception data register installed inside, and comparing the data with, for example, the value of a transmission data register in which the CPU has written wireless transmission data, failed to detect a failure. .

Therefore, when detecting a failure in a certain time division multiplexing circuit, a plurality of time division multiplexing circuits are required. Also, since it is necessary to control a plurality of time division multiplexing circuits, CP
The control of U becomes complicated. For example, in the case of the conventional example, the received wireless data is transmitted from the time-division multiplexing circuit by eight bits in a
Since U detects a failure while reading, there is a problem that it takes time to detect a failure.

The present invention has been made in view of the above problems, and has as its object to provide a failure detection method for a time division multiplexing circuit having a failure detection function capable of performing failure detection with high efficiency, and a circuit therefor. To be.

[0006]

To achieve the above object, according to the first aspect of the present invention, a radio transmission data to be transmitted and simultaneously transmitted to a time division multiplexing circuit in the TDMA-TDD system is taken in. A failure of the time division multiplexing circuit is detected based on the wireless transmission data before transmission and the captured wireless transmission data.

According to a second aspect of the present invention, in the first aspect of the present invention, there is provided a transmission data register for storing radio transmission data, and a reception data register for taking in and storing radio transmission data transmitted from the transmission data register. A time-division multiplexing circuit which incorporates a comparison unit for comparing the data stored in both registers at once, and a CPU for determining a failure of the time-division multiplexing circuit based on the comparison result of the comparison unit. It is characterized by being provided in.

According to a third aspect of the present invention, in the first aspect of the present invention, the radio transmission data transmitted from the transmission data register is scrambled by the scramble circuit and coded radio transmission data is fed back in the time division multiplexing circuit. It is characterized by the following. According to a fourth aspect of the present invention, in the second aspect of the present invention, the wireless transmission data transmitted from the transmission data register is subjected to privacy processing by a privacy circuit and encoded wireless transmission data is fed back in the time division multiplexing circuit. And

According to a fifth aspect of the present invention, in the second aspect of the present invention, wireless transmission data transmitted from the transmission data register and not subjected to confidential processing and scramble processing is fed back in the time division multiplexing circuit. . According to a sixth aspect of the present invention, in the second aspect of the present invention, the wireless transmission data once sent out of the time division multiplexing circuit is fed back into the time division circuit.

According to a seventh aspect of the present invention, in the second aspect of the present invention, the wireless transmission data transmitted from the transmission data register is confidentially processed by the privacy circuit and encoded, and the wireless transmission data is transmitted from the transmission data register. Radio transmission data which is coded by scrambling the radio transmission data by a scramble circuit, radio transmission data transmitted from a transmission data register and not subjected to confidential processing and scrambling, and radio transmission once transmitted outside the time division multiplexing circuit. It is characterized in that feedback is provided by switching transmission data.

According to an eighth aspect of the present invention, in the first aspect of the present invention, the transmission data register into which the radio transmission data is written by the CPU outside the time division multiplexing circuit, and the radio transmission data transmitted from the transmission data register are fetched. A reception data register to be stored, and a register provided in a time-division multiplexing circuit for serially comparing the fetched wireless transmission data with the wireless transmission data in the transmission data register to determine the presence / absence of a failure and providing the determination result in a time-division multiplexing circuit. And a means for writing the data in a time-division multiplexing circuit.

According to a ninth aspect of the present invention, in the eighth aspect of the present invention, the register is reset when the failure detection mode is released. According to a tenth aspect of the present invention, in the first aspect of the present invention, a transmission data register into which a wireless transmission data is written by a CPU outside the time division multiplexing circuit, and a reception unit that captures and stores the wireless transmission data transmitted from the transmission data register Time-division multiplexing includes a data register, means for encoding the wireless transmission data in the transmission data register with a scramble code, and means for comparing the encoded data with the data in the reception data register to determine whether there is a failure. It is characterized by being provided in a circuit.

According to the eleventh and the first aspects of the present invention, a transmission data register into which radio transmission data is written by a CPU outside the time division multiplexing circuit, and a reception for fetching and storing the radio transmission data transmitted from the transmission data register. Time-division multiplexing includes a data register, means for encoding the wireless transmission data in the transmission data register with a secret code, and means for comparing the encoded data with the data in the reception data register to determine whether there is a failure. It is characterized by being provided in a circuit.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention sets a failure detection mode for detecting a failure of a time division multiplexing circuit, and transmits radio transmission data as shown in FIG. Frame division is performed. In other words, the single time-division multiplexing circuit simultaneously transmits the wireless transmission data for failure detection and receives the wireless transmission data at the same time, and determines the original of the transmitted wireless transmission data and the transmitted and received wireless transmission data. A failure of the time division multiplexing transmission circuit is detected based on this.

Hereinafter, the present invention will be described with reference to embodiments. (Embodiment 1) FIG. 2 shows a configuration of the present embodiment.
In the present embodiment, a function of detecting a failure by comparing data is provided inside the time division multiplexing circuit 1. That is, the time-division multiplexing circuit 1 includes therein a transmission data register 11, a reception data register 12, and a comparison unit 13 for comparing the radio transmission data stored in the registers 11, 12.

When the mode for failure detection is set, the time division multiplexing circuit 1 serially transmits the wireless transmission data written to the transmission data register 11 by the CPU 2 outside the circuit from the wireless data transmission terminal 3a. At the same time as the transmission, the transmitted wireless transmission data is transmitted to the wireless data receiving terminal 3
b and is stored in the reception data register 12.

Then, the comparing unit 13 compares the data of the transmission data register 11 and the data of the reception data register 12 all at once (for example, 160 bits), and sends the data of the comparison result to the CPU 2. CPU
2 performs a failure state determination process based on this data. (Embodiment 2) This embodiment also has a function of detecting a failure by comparing data in the same manner as the first embodiment.
As shown in FIG. 3, the wireless transmission data from the transmission data register 11 is transmitted to the wireless data transmission terminal 3a via the privacy circuit 14 and the scramble circuit 15 as shown in FIG.
It is sent out more. Further, the wireless transmission data output from the scramble circuit 15 for detecting a failure is directly transmitted to the reception data register 1 in the time division multiplexing circuit 1.
It is designed to return to 2.

When the failure detection mode is set, the time-division multiplexing circuit 1 stops the operation of the privacy circuit 14 and operates the scramble circuit 15 to scramble the radio transmission data to be fed back. And so on. Therefore, the scrambled radio transmission data is stored in the reception data register 12, and the comparison unit 13 compares the radio transmission data with the transmission data register 11.
And the wireless transmission data written in all bits (for example, 1
(60 bits). Since the wireless transmission data written in the transmission data register 11 by the CPU 2 is encoded by the scramble circuit 15 at the time of transmission, the comparison unit 13 compares the wireless transmission data of both registers 11 and 12 at once to determine the different bit positions of the data. The result is sent to the CPU 2 as a comparison result. Since the CPU 2 can determine the bit position of the wireless transmission data changed by the scramble circuit 15, the CPU 2 can determine the failure state of the time division multiplexing circuit 1 by checking the comparison result data from the comparison unit 13. .

(Embodiment 3) In Embodiment 2, the operation of the secret talk circuit 14 is stopped in the failure detection mode, and the wireless transmission data encoded by the scramble circuit 15 is fed back. In the failure detection mode, the privacy communication circuit 14 is operated even in the failure detection mode, and the radio transmission data processed by the privacy conversation circuit 14 is processed by the scramble circuit 15.
The feedback is made before it is input to. FIG. 4 shows the configuration of the present embodiment.

When the failure detection mode is set, the time-division multiplexing circuit 1 performs a secret process on the radio transmission data and then stores it in the reception data register 12. Comparison section 13
Performs batch comparison of all the bits (for example, 160 bits) of the radio transmission data subjected to the confidential processing and the radio transmission data written in the transmission data register 11. Since the wireless transmission data written in the transmission data register 11 by the CPU 2 is encoded by the scramble circuit 15 at the time of transmission, the comparison unit 13 compares the wireless transmission data of both registers 11 and 12 at once to determine the different bit positions of the data. The result is sent to the CPU 2 as a comparison result. Since the CPU 2 can determine the bit position of the wireless transmission data changed by the privacy circuit 14, the failure state of the time division multiplexing circuit 1 can be determined by checking the comparison result data from the comparison unit 13. .

(Embodiment 4) This embodiment also detects a failure by comparing data. In this embodiment, serial wireless transmission data output from the transmission data register 11 is directly stored in the reception data register 12. It is like that. FIG. 5 shows the configuration of the present embodiment.

Here, the data stored in the reception data register 12 is the same as the radio transmission data written in the transmission data register 11 by the CPU 2 if there is no failure. In the time-division multiplexing circuit 1, the serial wireless transmission data output from the transmission data register 11 before entering the secret communication circuit 14 and the scramble circuit 15 in the failure detection mode is stored in the reception data register 12, and then the storage is performed. The comparison unit 13 collectively compares the data in the reception data register 12 and the wireless transmission data written in the transmission data register 11 by the comparison unit 13 for all bits (for example, 160 bits), and sends the comparison result to the CPU 2. CPU2
Since the wireless transmission data written in the transmission data register 11 is not encoded, the comparison result of the comparison unit 13 is
Comparison result data indicating whether data is different between the two registers 11 and 12 is sent to the CPU 2, and the CPU 2 determines a failure state.

(Embodiment 5) This embodiment also performs a failure detection by comparing data.
As shown in FIG. 5, the wireless communication device includes a secret communication circuit 14 and a scramble circuit 15, but the wireless transmission data transmitted from the wireless data transmission terminal 3a is received and returned via the wireless data reception terminal 3b as in the first embodiment. It has become.
Note that an output pad 16A of the chip is interposed between the scrambled circuit 15 and the wireless data transmission terminal 3a, and an input pad 16B of the chip is interposed between the wireless data reception terminal 3b and the reception data register 12.

When the failure detection mode is set, the time division multiplexing circuit 1 sends out the radio transmission data to be fed back once to the outside of the time division multiplexing circuit 1 and then feeds back the radio transmission data into the circuit. At this time, the operations of the secret talk circuit 14 and the scramble circuit 15 are stopped. If the operation of the time-division multiplexing circuit 1 is normal, the reception data register 11 stores the same radio transmission data as the radio transmission data written in the transmission data register 11 by the CPU 2. The data is stored in all bits (for example, 16 bits).
0 bit). Since the wireless transmission data written by the CPU 14 is not encoded, the comparison result indicates whether the data differs between the wireless transmission data written in the transmission data register 11 and the wireless transmission data stored in the reception data register 12. The result of the comparison is sent to the CPU 2 and the CPU 2 determines the failure state.

(Embodiment 6) In this embodiment, the failure detection method in Embodiments 2 to 5 is switched by a switch 17 as shown in FIG. 7, and the serial output of the transmission data register 11 and the secret communication circuit 14 The output, the output of the scramble circuit 15, and the data which is once sent out of the circuit via the output pad 16A from the scramble circuit 15 and then fed back into the circuit are switched and stored in the reception data register 12, and the data in each case is stored. Do the comparison.

That is, in the case of the second embodiment, if there is a failure in the secret communication circuit 14 whose operation has been stopped and a failure in the transmission data register 11, it cannot be specified where the failure is. Further, in the case of the third embodiment, if a failure exists in the transmission data register 11, it cannot be specified whether the privacy circuit 14 has failed or the transmission data register 11 has failed. On the other hand, in the case of the fourth embodiment, it is possible to specify whether or not the transmission data register 11 has a failure, but it is not possible to specify whether or not the privacy circuit 14 and the scramble circuit 15 have a failure. In the case of Embodiment 5,
If there is a failure in the confidential circuit 14, the scramble circuit 15, and the transmission data register 11 whose operation has been stopped, it cannot be specified where the failure is. In order to solve the problems of each of the above embodiments, the time division multiplexing circuit 1 of the present embodiment switches the switch 17 according to the instruction of the CPU 2 in the failure detection mode to switch the reception data register 12.
The data to be stored is switched.

(Embodiment 7) In this embodiment, the time division multiplexing circuit 1 has two transmission data registers 11 as shown in FIG.
a and 11b are provided, and the wireless transmission data is written by the CPU 2 respectively, and the wireless transmission data of one transmission data register 11a is output to the outside from the wireless data transmission terminal 3a and is input to the exclusive OR 18 and the other transmission data is transmitted. The wireless transmission data of the data register 11b is input to the exclusive OR 18. Exclusive OR 18 is used for both transmission data registers 11
The radio transmission data a and 11b are compared. When there is no bit error, the comparison result is always "L", and when even a single bit has a bit error, it is "H". This comparison result is sent to the 1-bit register 19. The 1-bit register 19 is specifically composed of a D-type flip-flop 21 and a selector 20 as shown in FIG. 9, and the D-type flip-flop 21 outputs the output of the selector 20 to a D terminal.
The output is output to the external CPU 2 as an OK or NG signal and is returned to the input of the selector 20. The selector 20 switches between the comparison result and the output of the D-type flip-flop 21 according to the output and outputs.

When the comparison result input from the exclusive OR 18 to the selector 20 is "L", that is, when there is no bit error, the D-type flip-flop 21 which outputs "L" in the initial state is used. Upon receiving the output, the selector 20 selects the comparison result input. Next, when there is a bit error and “H” is output from the exclusive OR 18 as a comparison result, the D-type flip-flop 21 latches the “H” comparison result based on the clock input, and outputs “H”. Generate output. In response to the output of “H”, the selector 20 selects the output of the D-type flip-flop 21. Therefore, if at least one bit error is detected, the D-type flip-flop 21
, The comparison result of “H” is latched. Accordingly, the CPU 2 can receive the output of the D-type flip-flop 21 and know whether the time division multiplexing circuit 1 is in failure (NG) or not (OK).

That is, the CPU 2 does not determine whether a failure or non-failure based on the comparison result, but simply receives the result of the determination. It is done in. (Embodiment 8) In the present embodiment, the configuration of the 1-bit register 19 in Embodiment 9 is configured as shown in FIG. That is, in the seventh embodiment, once a bit error is detected, an NG signal indicating a bit error is continuously output, and therefore, even when a failure is detected again, an NG signal indicating a bit error is continuously output. There are inconveniences.

Therefore, in the present embodiment, once the CPU 2 switches the mode from the failure detection mode to the normal operation mode, the D-type flip-flop 21 is reset by giving a reset signal at a predetermined timing. ing. The other configuration is the same as that of the eighth embodiment, and the description of the entire configuration will be omitted here.

(Embodiment 9) This embodiment is different from Embodiment 2 shown in FIG.
3, a scramble code encoding circuit 22 is provided as shown in FIG. The encoding circuit 22 encodes the wireless transmission data in the transmission data register 11 with a scramble code and provides the encoded data to the comparison unit 11.

That is, in the present embodiment, the failure can be determined in the time division multiplexing circuit 1 by comparing the encoded data with the data stored in the reception data register 12. Forms 7, 8
Similarly to the above, an OK or NG signal indicating the determination result is given to notify whether or not a failure has occurred, so that the CPU 2 does not perform the determination.

The other configuration is the same as that of the second embodiment, and the description is omitted here. (Embodiment 10) This embodiment corresponds to Embodiment 3 shown in FIG.
In FIG. 12, a secret code encoding circuit 23 is provided between the transmission data register 11 and the comparison unit 13 as shown in FIG. The encoding circuit 23 encodes the wireless transmission data in the transmission data register 11 with a secret code and provides the encoded data to the comparison unit 11.

That is, in the present embodiment, the failure can be determined in the time division multiplexing circuit 1 by comparing the encoded data with the data stored in the reception data register 12. In the same manner as in the seventh and eighth embodiments, an OK or NG signal indicating a determination result is given to notify whether or not a failure has occurred, and the determination by the CPU 2 is not performed.

The other configuration is the same as that of the third embodiment, and the description is omitted here.

[0036]

According to the first aspect of the present invention, the time division multiplexing circuit in the TDMA-TDD system has a function of transmitting radio transmission data and a function of simultaneously taking in radio transmission data to be transmitted, and transmits the data for transmission. Since the failure of the time division multiplexing circuit is detected based on the wireless transmission data given to the function and the captured wireless transmission data, the failure detection of the time division multiplexing circuit is performed not by controlling a plurality of time division multiplexing circuits. In addition, there is an effect that fault detection can be performed with high efficiency using a single time-division multiplexing circuit.

According to a second aspect of the present invention, in the first aspect of the present invention, there is provided a transmission data register for storing radio transmission data, and a reception data register for taking in and storing radio transmission data transmitted from the transmission data register. A time-division multiplexing circuit which incorporates a comparison unit for comparing the data stored in both registers at once, and a CPU for determining a failure of the time-division multiplexing circuit based on the comparison result of the comparison unit. Therefore, the same effect as the effect of the first aspect can be obtained.

According to a third aspect of the present invention, in the second aspect of the present invention, the radio transmission data transmitted from the transmission data register is scrambled by the scramble circuit, and the coded radio transmission data is fed back in the time division multiplexing circuit. According to a fourth aspect of the present invention, in the second aspect of the present invention, the wireless transmission data transmitted from the transmission data register is subjected to the privacy processing by the privacy circuit and the coded wireless transmission data is fed back in the time division multiplexing circuit. Therefore, according to a fifth aspect of the present invention, in the second aspect of the present invention, the wireless transmission data transmitted from the transmission data register and not subjected to the privacy processing and the scramble processing is fed back in the time division multiplexing circuit. The same effects as those of the second aspect can be obtained.

According to a sixth aspect of the present invention, as in the second aspect of the invention, the wireless transmission data once sent out of the time division multiplexing circuit is fed back into the time division circuit. Effects can be obtained. According to a seventh aspect of the present invention, in the second aspect of the present invention, the wireless transmission data transmitted from the transmission data register is subjected to confidential processing by a privacy circuit and encoded, and the wireless transmission data transmitted from the transmission data register. Wireless transmission data that is scrambled and coded by a scramble circuit, wireless transmission data transmitted from a transmission data register and not subjected to confidential processing and scramble processing, and wireless transmission data transmitted once outside the time division multiplexing circuit. Is returned by switching, a detailed failure state of each block can be detected.

According to an eighth aspect of the present invention, in the first aspect of the present invention, the CPU outside the time division multiplexing circuit fetches the transmission data register into which the wireless transmission data is written and the wireless transmission data transmitted from the transmission data register. A reception data register to be stored, and a register provided in a time-division multiplexing circuit for serially comparing the fetched wireless transmission data with the wireless transmission data in the transmission data register to determine the presence / absence of a failure and providing the determination result in a time-division multiplexing circuit. Is provided in the time-division multiplexing circuit, so that the CPU does not make a failure determination, and the result of the determination as to whether or not the time-division multiplexing circuit itself has failed can be output in one bit. Instead of controlling the time-division multiplexing circuit, the failure detection can be performed by a single time-division multiplexing circuit, so that the processing by the external CPU can be simplified. There is an effect.

According to a ninth aspect of the present invention, in the invention of the eighth aspect, the register is reset when the failure detection mode is released, so that the register can be reset every time the failure detection mode is released. According to a tenth aspect of the present invention, in the first aspect of the present invention, a transmission data register in which the wireless transmission data is written by the CPU outside the time division multiplexing circuit, and a receiving unit that captures and stores the wireless transmission data transmitted from the transmission data register Time-division multiplexing includes a data register, means for encoding the wireless transmission data in the transmission data register with a scramble code, and means for comparing the encoded data with the data in the reception data register to determine whether there is a failure. Since it is provided in the circuit, the time-division multiplexing circuit itself can output a 1-bit determination result as to whether or not there is a failure, without controlling the CPU for failure, and controls a plurality of time-division multiplexing circuits. Instead, the failure detection can be performed by a single time-division multiplexing circuit, so that the processing by the external CPU can be simplified. A.

According to the eleventh and the first aspects of the present invention, a transmission data register into which radio transmission data is written by a CPU outside the time division multiplexing circuit, and a reception for taking in and accumulating the radio transmission data sent from the transmission data register. Time-division multiplexing includes a data register, means for encoding the wireless transmission data in the transmission data register with a secret code, and means for comparing the encoded data with the data in the reception data register to determine whether there is a failure. Since it is provided in the circuit, the time-division multiplexing circuit itself can output 1-bit information as to whether or not there is a failure without making the CPU determine a failure, and instead of controlling a plurality of time-division multiplexing circuits, In addition, since failure detection can be performed by a single time-division multiplexing circuit, there is an effect that processing by an external CPU can be simplified.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the concept of frame division in a failure detection mode according to the method of the present invention.

FIG. 2 is a circuit configuration diagram of Embodiment 1 of the present invention.

FIG. 3 is a circuit configuration diagram according to a second embodiment of the present invention.

FIG. 4 is a circuit configuration diagram according to a third embodiment of the present invention.

FIG. 5 is a circuit configuration diagram according to a fourth embodiment of the present invention.

FIG. 6 is a circuit configuration diagram according to a fifth embodiment of the present invention.

FIG. 7 is a circuit configuration diagram according to a sixth embodiment of the present invention.

FIG. 8 is a circuit configuration diagram according to a seventh embodiment of the present invention.

FIG. 9 is a circuit configuration diagram of the register of Embodiment 1;

FIG. 10 is a circuit configuration diagram of a register according to an eighth embodiment of the present invention.

FIG. 11 is a circuit diagram of a ninth embodiment of the present invention.

FIG. 12 is a circuit configuration diagram according to a tenth embodiment of the present invention.

FIG. 13 is an explanatory diagram of a conventional example.

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04L 29/14 H04L 13/00 315A

Claims (11)

[Claims] In a failure detection method for a time division multiplexing circuit in a TDMA-TDD system, a single time division multiplexing circuit transmits radio transmission data at the same time that radio transmission data to be transmitted is taken in, and radio transmission data before transmission is transmitted. Detecting a failure of the time division multiplexing circuit based on the original data of the time division multiplexing and the fetched wireless transmission data. 2. A transmission data register storing radio transmission data, a reception data register receiving and storing radio transmission data transmitted from the transmission data register, and comparing data stored in both registers at once. A time-division multiplexing circuit, wherein a CPU for determining a failure of the time-division multiplexing circuit based on the comparison result of the comparison unit is provided outside the time-division multiplexing circuit. Failure detection circuit. 3. The time division multiplexing circuit according to claim 2, wherein the radio transmission data sent from the transmission data register is scrambled by a scramble circuit and coded radio transmission data is fed back in a time division multiplexing circuit. Multi-circuit fault detection circuit. 4. The time division multiplexing circuit according to claim 2, wherein the radio transmission data transmitted from the transmission data register is subjected to confidential processing by a confidential circuit and the coded radio transmission data is fed back in a time division multiplexing circuit. Multi-circuit fault detection circuit. 5. The failure detection of a time division multiplexing circuit according to claim 2, wherein the wireless transmission data sent from the transmission data register and not subjected to confidential processing and scrambling processing is fed back in the time division multiplexing circuit. circuit. 6. The failure detection circuit for a time division multiplexing circuit according to claim 2, wherein the radio transmission data once sent out of the time division multiplexing circuit is fed back into the time division multiplexing circuit. 7. A radio transmission data transmitted from a transmission data register and coded by performing a privacy process by a privacy circuit, and a radio transmission data transmitted from the transmission data register is subjected to a scrambling process by a scrambling circuit to code the radio transmission data. Feedback by switching between wireless transmission data that has been converted, wireless transmission data transmitted from the transmission data register and not subjected to confidential processing and scramble processing, and wireless transmission data that has been transmitted once outside the time division multiplexing circuit. 3. A failure detection circuit for a time division multiplexing circuit according to claim 2. 8. A transmission data register in which wireless transmission data is written by a CPU outside the time division multiplexing circuit, a reception data register for receiving and storing the wireless transmission data transmitted from the transmission data register, The time division multiplexing circuit includes means for serially comparing the transmission data with the wireless transmission data in the transmission data register to determine the presence / absence of a failure, and for writing the determination result to a register provided in the time division multiplexing circuit. A failure detection circuit for a time division multiplexing circuit. 9. The fault detection circuit according to claim 8, wherein the register is reset when the mode of the fault detection is released. 10. A transmission data register in which radio transmission data is written by a CPU outside the time division multiplexing circuit, a reception data register for taking in and accumulating the radio transmission data transmitted from the transmission data register, and a transmission data register in the transmission data register. Means are provided in the time-division multiplexing circuit for encoding the radio transmission data with a scramble code and for comparing the encoded data with the data in the reception data register to determine the presence or absence of a failure. Failure detection circuit of a time-division multiplexing circuit. 11. A transmission data register in which radio transmission data is written by a CPU outside the time division multiplexing circuit, a reception data register for taking in and accumulating the radio transmission data transmitted from the transmission data register, and a transmission data register in the transmission data register. Means is provided in the time-division multiplexing circuit for performing means for encoding the radio transmission data using a secret code, and for comparing the encoded data with the data in the reception data register to determine whether there is a failure. Failure detection circuit of a time-division multiplexing circuit.